CN112687616B - Preparation method of radio frequency tube shell and radio frequency tube shell - Google Patents
Preparation method of radio frequency tube shell and radio frequency tube shell Download PDFInfo
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Abstract
The invention is suitable for the technical field of microwave components, and provides a preparation method of a radio frequency tube shell and the radio frequency tube shell, which comprises the following steps: sputtering a plurality of layers of metal on a substrate to obtain a first seed layer, and electroplating gold on a first area and a second area on the first seed layer to respectively prepare gold conductor layers; removing the first seed layer outside the gold conductor layer area, and preparing a thin film resistor between the first area and the second area to obtain a first sample; baking the first sample at a first preset temperature and carrying out air annealing to obtain a second sample; sputtering a plurality of layers of metal on the surface of the second sample to obtain a second seed layer, and electroplating copper on the second seed layer to prepare a copper conductor layer; electroplating copper again on the fourth area in the third area to heighten the copper conductor layer; and removing the second seed layer outside the copper conductor layer area. The invention completes the preparation of the high-precision gold conductor layer, thereby realizing high-density wiring, and prevents electromigration and ensures the long-term stability of the device by preparing the superposed structure of the copper conductor layer and the gold conductor layer.
Description
Technical Field
The invention belongs to the technical field of microwave components, and particularly relates to a preparation method of a radio frequency tube shell and the radio frequency tube shell.
Background
With the continuous optimization of rf chip monolithic in terms of power, efficiency and size, analog circuit functional blocks such as power amplification, filtering, switching, etc. can be realized by a single die or stacking several chips. In order to integrate a microwave component with complete functions in a single package, further improve the integration level and realize microwave component componentization, digital circuit chips such as an AD/DA (analog-to-digital) chip, a power supply control chip, a digital processing chip and the like need to be integrated into a radio frequency tube shell, so that the radio frequency tube shell needs to integrate not only interconnection lines with narrow line width and high density but also thick metal lines for heat dissipation and isolation required by high-density assembly of the radio frequency chip on the premise of meeting the characteristics of high reliability, airtightness and low loss, and the realization difficulty is very high.
At present, in a TR multichannel transceiving component, an antenna, a radio frequency part and a digital part are mutually independent and are interconnected through a motherboard, so that the integration level is low, and the problems of heat dissipation, isolation and the like caused by intensive arrangement of multi-chip interconnection wiring and radio frequency units can be caused after the integration level is improved.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for manufacturing a radio frequency package and a radio frequency package, which aim to solve the problems in the prior art that the integration level is low, and the integration level is increased, which may cause the dense arrangement of multi-chip interconnection wiring and radio frequency units, which requires heat dissipation and isolation.
In order to achieve the above object, a first aspect of the embodiments of the present invention provides a method for manufacturing a radio frequency package, including:
sputtering multilayer metal on a substrate to obtain a first seed layer, and electroplating gold on a first area and a second area on the first seed layer to respectively prepare gold conductor layers, wherein the first area is not connected with the second area;
removing the first seed layer outside the gold conductor layer area, and preparing a thin film resistor between the first area and the second area to obtain a first sample;
baking the first sample at a first preset temperature and carrying out air annealing to obtain a second sample;
sputtering multiple layers of metal on the surface of the second sample to obtain a second seed layer, and electroplating copper on the second seed layer to prepare a copper conductor layer, wherein the copper conductor layer covers a partial area, far away from the first area, in a corresponding area of the gold conductor layer in the second area and a third area on the second seed layer, and the third area is different from the first area and the second area and is connected with the partial area;
electroplating copper again on the fourth area in the third area to heighten the copper conductor layer;
and removing the second seed layer outside the copper conductor layer area.
As another embodiment of the present application, the substrate is a sapphire substrate or a glass substrate.
As another embodiment of the present application, the first seed layer sequentially includes TaN, TiW, and Au from bottom to top;
the second seed layer sequentially comprises Ti, TiW and Cu from bottom to top;
the thickness of the first seed layer and the second seed layer is 50nm to 5000 nm.
As another embodiment of the present application, the electroplating gold on the first area and the second area on the first seed layer to respectively prepare gold conductor layers includes:
coating a first light resistance layer on the first seed layer in a spin coating or film-covering hot pressing mode, and electroplating gold on the exposed first area and the exposed second area after exposure and development to obtain a gold conductor layer;
removing the first photoresist layer;
the thickness of the first photoresist layer is larger than 5 mu m;
the thickness of the gold conductor layer is 2-5 μm.
As another embodiment of the present application, the removing the first seed layer outside the gold conductor layer region, and preparing a thin film resistor between the first region and the second region to obtain a first sample includes:
coating a second light resistance layer on the gold conductor layer and the first seed layer in a spin coating or film-covering hot pressing mode, and sequentially corroding Au and TiW in the area outside the exposed gold conductor layer area after exposure and development;
removing the second photoresist layer;
and coating a third photoresist layer on the gold conductor layer and the first seed layer in a spin coating or film-coating hot pressing mode, etching TaN in the exposed TaN area after exposure and development, and taking the TaN between the residual first area and the residual second area as a thin film resistor to obtain a first sample.
As another embodiment of the present application, the baking and air annealing the first sample at a first preset temperature to obtain a second sample includes:
and (3) annealing the first sample by adopting air with the temperature of 350 ℃ and the time of 30min to obtain a second sample.
As another embodiment of the present application, the step of electroplating copper on the second seed layer to prepare a copper conductor layer includes:
electroplating copper on the second seed layer to prepare a copper conductor layer in a mode of using pulse plating and direct current plating in a combined mode;
grinding the copper conductor layer to thin the copper conductor layer;
carrying out surface polishing treatment on the thinned copper conductor layer;
the total thickness of the copper conductor layer is 50 μm to 5000 μm.
As another embodiment of the present application, a region where the copper conductor layer and the gold conductor layer overlap is greater than or equal to 6 μm by 8 μm.
As another embodiment of the present application, the removing the second seed layer outside the copper conductor layer area includes:
removing Cu in the second seed layer outside the copper conductor layer area by using strong acid washing etching liquid;
sequentially removing TiW and Ti in the second seed layer outside the copper conductor layer area by using oxide etching liquid;
after the step of removing the second seed layer outside the copper conductor layer area, the method further comprises the following steps:
and plating a nickel-gold layer on the copper conductor layer.
A second aspect of an embodiment of the present invention provides a radio frequency package, including:
a substrate;
the first seed layer and the gold conductor layer are sequentially prepared on a first area and a second area on the substrate, and the first area is not connected with the second area;
a thin film resistor fabricated between the first region and the second region;
and the second seed layer and the copper conductor layer are sequentially prepared on a partial area and a third area which are far away from the first area in the area corresponding to the gold conductor layer in the second area, and the third area is different from the first area and the second area and is connected with the partial area.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: compared with the prior art, the method has the advantages that the seed layer is sputtered on the substrate, the pattern is defined by photoetching (the precision reaches 0.1 mu m), the conductor pattern is thickened to obtain the gold conductor layer, and then the seed layer which is not needed is removed by photoetching and etching again to finish the preparation of the high-precision gold conductor layer, so that the high-density wiring is realized. And then, repeatedly sputtering and photoetching, and preparing a copper conductor layer with the thickness reaching millimeters by adopting pulse and direct current superposition electroplating, so that quick heat dissipation and uniform heating are realized, and electromigration is prevented and the long-term stability of the device is ensured by preparing a superposition structure of the copper conductor layer and the gold conductor layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a radio frequency package according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a gold conductor layer according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a radio frequency enclosure provided by an embodiment of the invention;
FIG. 4 is a schematic diagram of a thin film resistor provided in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a second seed layer provided by an embodiment of the invention;
FIG. 6 is a schematic diagram of a copper conductor layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a raised copper conductor layer provided by an embodiment of the present invention;
fig. 8 is a schematic diagram of a nickel layer provided in an embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a radio frequency package according to an embodiment of the present invention, which is described in detail below.
Alternatively, the substrate may be a sapphire substrate or a glass substrate.
Optionally, the step may include sputtering multiple layers of metal on the surface of the cleaned substrate in sequence to form a first seed layer, where the first seed layer includes a TaN layer, a TiW layer, and an Au layer in sequence from bottom to top; wherein the thickness of the seed layer is 50nm to 5000 nm.
Alternatively, the first seed layer may be obtained by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD).
Optionally, when the gold conductor layer is prepared on the seed layer, a first photoresist layer may be coated on the first seed layer by spin coating or film-covering hot-pressing, and gold is electroplated on the exposed first area and the exposed second area after exposure and development to obtain a gold conductor layer; and then removing the first photoresist layer.
Optionally, the photoresist material used for the first photoresist layer may be a high-viscosity photoresist, for example, a THB series negative photoresist; it may also be a high-resolution photosensitive dry film, for example, an ST-series dry film. The thickness of the first photoresist layer is larger than 5 μm, the line resolution is less than 1 μm, and the exposed side wall is steep.
In the electroplating of gold, the surface pattern defined by the first photoconductive layer is thickened to 2 μm to 5 μm by electrochemically depositing gold, that is, the gold conductor layer has a thickness of 2 μm to 5 μm.
The gold conductor layer prepared as shown in fig. 2, the substrate being denoted by 1 in fig. 2, the first seed layer being denoted by 2, the gold conductor layer of the first region being denoted by 31, the gold conductor layer of the second region being denoted by 32, the gold conductor layers of the first region and the second region constituting the total gold conductor layer being denoted by 3. As shown in fig. 3, the gold conductor layer in the first area is rectangular, and the gold conductor layer in the second area is in the shape of two rectangles connected together. The exposed areas of the first photoresist layer after exposure and development are a first area and a second area.
And 102, removing the first seed layer outside the gold conductor layer area, and preparing a thin film resistor between the first area and the second area to obtain a first sample.
Optionally, this step may include:
coating a second light resistance layer on the gold conductor layer and the first seed layer in a spin coating or film-covering hot pressing mode, and sequentially corroding Au and TiW in the area outside the exposed gold conductor layer area after exposure and development;
removing the second photoresist layer;
and coating a third photoresist layer on the gold conductor layer and the first seed layer in a spin coating or film-covering hot pressing mode, etching TaN in the exposed TaN area after exposure and development, and taking the TaN between the rest of the first area and the second area as a thin film resistor to obtain a first sample.
The sheet resistance diagram is shown in fig. 4, and 4 in fig. 4 shows the sheet resistance.
The manufacturing process of adopting the silicon chip on the substrate comprises the steps of firstly sputtering a seed layer, defining a pattern by photoetching, enabling the precision to reach 0.1 mu m, then adopting jet electroplating to thicken a conductor pattern, then photoetching again and etching to remove the unnecessary seed layer, completing the preparation of a high-density gold conductor layer, and realizing high-density wiring.
And 103, baking the first sample at a first preset temperature and carrying out air annealing to obtain a second sample.
Optionally, this step may include: and (3) annealing the first sample by adopting air with the temperature of 350 ℃ and the time of 30min to obtain a second sample. The high-temperature baking can reduce the hardness of the gold conductor layer, accelerate the resistance aging of the film and improve the environmental tolerance.
And 104, sputtering multiple layers of metal on the surface of the second sample to obtain a second seed layer, electroplating copper on the second seed layer to prepare a copper conductor layer, wherein the copper conductor layer covers a partial area, far away from the first area, in an area corresponding to the gold conductor layer in the second area, and a third area on the second seed layer, and the third area is different from the first area and the second area and is connected with the partial area.
The second seed layer sequentially comprises Ti, TiW and Cu from bottom to top, and the thickness of the second seed layer is 50nm to 5000 nm. The second seed layer may be deposited by a method similar to that of the first seed layer, or by physical vapor deposition or chemical vapor deposition. As shown in fig. 5, a schematic diagram of the second seed layer is shown, and 5 in fig. 5 represents the second seed layer, which is uniformly covered on the surface of the device.
Defining a surface copper conductor layer on the second seed layer, coating a fourth photoresist layer on the second seed layer by a spin coating or film-covering hot pressing mode, and electroplating copper in a bare area by adopting a mode of combining pulse plating and direct current plating to prepare the copper conductor layer after exposure and development; grinding the copper conductor layer to thin the copper conductor layer; and carrying out surface polishing treatment on the thinned copper conductor layer. Referring to the schematic diagram of the copper conductor layer shown in fig. 6, the electroplated copper conductor layer is shown as 6, and the fourth photoresist layer is shown as 7. In fig. 6, 6 denotes a copper conductor layer, the copper conductor layer covers a partial region of a region corresponding to the gold conductor layer, and a superposed region of the copper conductor layer and the gold conductor layer is greater than or equal to 6 μm by 8 μm. As shown in fig. 3, the copper conductor layer is formed by two rectangles, the area of the rectangle covering the corresponding region of the gold conductor layer is greater than or equal to 10 μm by 10 μm, and the area of the covered gold conductor layer is greater than or equal to 6 μm by 8 μm, that is, the overlapping region of the copper conductor layer and the gold conductor layer, so as to ensure the interconnection of the gold conductor and the copper conductor.
Referring to fig. 6, the structure of the overlapping area of the copper conductor and the gold conductor viewed longitudinally is: the substrate-the first seed layer (TaN100-300A, TiW 500-1000A, Au300-500A) -the gold conductor layer (0.5-3 μm) -the second seed layer (Ti 500-1000A, TiW 1000 2000A, Cu3000-20000A) -the copper conductor layer (10-5000 μm), and TiW is added into the second sputtered layer of the copper conductor layer to prevent the mutual diffusion of Au and Cu. In the plane direction, the mode that the thick copper conductor layer wraps the thin gold conductor layer is adopted, and mutual diffusion and electromigration of copper and gold are prevented.
The electroplating efficiency can be improved by adopting the mode of combining pulse plating and direct current plating for electroplating copper. The prepared copper conductor layer is ground and polished, so that the metal layer thickness with higher precision and the surface roughness with lower precision can be obtained.
And 105, electroplating copper again on the fourth area in the third area to heighten the copper conductor layer.
Alternatively, when the copper electroplating is performed again, the fourth photoresist layer may not be removed, the copper electroplating is performed again directly on the fourth photoresist layer by the same process as that used in the first copper electroplating, only the electroplating region is different, and then all the resistive layers are removed. As shown in fig. 7, the copper conductor layer at the upper end of the dotted line is a heightened copper conductor layer, and is denoted by 8.
The total thickness of the copper conductor layer is 50 μm to 5000 μm.
As shown in fig. 7, different copper conductor layers are prepared at different design positions, and some copper conductor layers are used as conductors of excessive current, so that loss is reduced; some of the chips are used as surface-mounted bonding pads and radiating grounding channels of chips with high radiating capacity; some of them are used as partition walls for isolating different radio frequency chips. The ultra-thick copper conductor is beneficial to passing large current, dissipating heat or being used as a separation wall.
And 106, removing the second seed layer outside the copper conductor layer area.
Optionally, when the second seed layer is removed, since the second seed layer is sequentially Ti, TiW, and Cu from bottom to top, the Cu, TiW, and Ti are sequentially removed during the removal. Optionally, removing Cu in the second seed layer outside the copper conductor layer area by using a strong acid washing etching solution; sequentially removing TiW and Ti in the second seed layer outside the copper conductor layer area by using oxide etching liquid;
after the removing the second seed layer outside the copper conductor layer area, further comprising:
and plating a nickel-gold layer on the copper conductor layer.
Optionally, the surface and the side surfaces of the copper conductor layer are plated with the nickel layer and the gold layer, and a surface metal pattern area can be protected by adopting a chemical nickel-gold plating mode, so that the environmental tolerance is improved. As shown in fig. 8, 9 in fig. 8 represents a nickel layer.
In the embodiment, the copper conductor layer is made of thick copper, the gold conductor layer is made of thin gold, and two metallization systems of thick copper and thin gold are adopted for multiplexing wiring, so that hybrid integration can be realized. Compatible with various assembly modes and convenient use.
The preparation method of the radio frequency tube shell comprises the steps of sputtering the seed layer on the substrate, defining the pattern by photoetching (the precision reaches 0.1 mu m), electroplating the thickened conductor pattern to obtain the gold conductor layer, photoetching again and etching to remove the unnecessary seed layer, and completing the preparation of the high-precision gold conductor layer, thereby realizing high-density wiring. And then, repeatedly sputtering and photoetching, and preparing a copper conductor layer with the thickness reaching millimeters by adopting pulse and direct current superposition electroplating, so that quick heat dissipation and uniform heating are realized, and electromigration is prevented and the long-term stability of the device is ensured by preparing a superposition structure of the copper conductor layer and the gold conductor layer.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by functions and internal logic of the process, and should not limit the implementation process of the embodiments of the present invention in any way.
An rf package provided in an embodiment of the present invention is prepared by the method for preparing an rf package according to any one of the above embodiments, and as shown in fig. 3 or fig. 8, the apparatus may include:
a substrate 1;
a first seed layer 2 and a gold conductor layer 3 which are sequentially prepared in a first area and a second area on the substrate 1, wherein the first area is not connected with the second area;
a thin film resistor 4 prepared between the first region and the second region;
and a second seed layer 5 and a copper conductor layer 6 sequentially prepared on a partial region and a third region which are far away from the first region in a region corresponding to the gold conductor layer in the second region, wherein the third region is different from the first region and the second region and is connected with the partial region.
Optionally, the nickel layer 9 prepared on the gold conductor layer 3, the thin-film resistor 4 and the copper conductor layer 6 can protect the surface metal pattern region, so as to improve the environmental tolerance.
Optionally, the first seed layer sequentially comprises TaN, TiW and Au from bottom to top; the second seed layer sequentially comprises Ti, TiW and Cu from bottom to top; the thickness of the first seed layer and the second seed layer is 50nm to 5000 nm.
Optionally, the thickness of the gold conductor layer is 2 μm to 5 μm. The gold conductor layer and the thin-film resistor are obtained through air annealing at the temperature of 350 ℃ for 30min, so that the hardness of the gold conductor layer is reduced, the resistance is accelerated to age, and the environmental tolerance is improved.
Optionally, the total thickness of the copper conductor layer is 50 μm to 5000 μm. The ultra-thick copper conductor is beneficial to passing large current, dissipating heat or being used as a separation wall.
The overlapping area of the copper conductor layer and the gold conductor layer is greater than or equal to 6 microns by 8 microns, so that the interconnection of the gold conductor and the copper conductor can be guaranteed.
The structure of the superposed area of the copper conductor and the gold conductor is as follows when viewed longitudinally: the substrate-the first seed layer (TaN100-300A, TiW 500-1000A, Au300-500A) -the gold conductor layer (0.5-3 μm) -the second seed layer (Ti 500-1000A, TiW 1000 2000A, Cu3000-20000A) -the copper conductor layer (10-5000 μm), and TiW is added into the second sputtered layer of the copper conductor layer to prevent the mutual diffusion of Au and Cu. In the plane direction, the mode that the thick copper conductor layer wraps the thin gold conductor layer is adopted, and mutual diffusion and electromigration of copper and gold are prevented.
In the embodiment, the copper conductor layer is made of thick copper, the gold conductor layer is made of thin gold, and two metallization systems of thick copper and thin gold are adopted for multiplexing wiring, so that hybrid integration can be realized. Compatible with various assembly modes and convenient use.
According to the radio frequency tube shell, the preparation of the high-precision gold conductor layer is completed through the gold conductor layer, so that high-density wiring is realized. And then, repeatedly sputtering and photoetching, and preparing a copper conductor layer with the thickness reaching millimeters by adopting pulse and direct current superposition electroplating, so that quick heat dissipation and uniform heating are realized, and electromigration is prevented and the long-term stability of the device is ensured through the superposition structure of the prepared copper conductor layer and the prepared gold conductor layer.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A method of making a radio frequency package comprising:
sputtering multilayer metal on a substrate to obtain a first seed layer, defining a pattern by photoetching to electrically plate a first area and a second area on the first seed layer to respectively prepare gold conductor layers, wherein the first area is not connected with the second area;
removing the first seed layer outside the gold conductor layer area, and preparing a thin film resistor between the first area and the second area to obtain a first sample;
baking the first sample at a first preset temperature and carrying out air annealing to obtain a second sample;
sputtering multiple layers of metal on the surface of the second sample to obtain a second seed layer, and electroplating copper on the second seed layer to prepare a copper conductor layer, wherein the copper conductor layer covers a partial area, far away from the first area, in a corresponding area of the gold conductor layer in the second area and a third area on the second seed layer, and the third area is different from the first area and the second area and is connected with the partial area;
electroplating copper again on a fourth area in the third area, and increasing the thickness of a copper conductor layer, wherein the total thickness of the copper conductor layer is larger than that of the gold conductor layer;
and removing the second seed layer outside the copper conductor layer area.
2. A method of fabricating a radio frequency package as claimed in claim 1, wherein the substrate is a sapphire substrate or a glass substrate.
3. The method of claim 1, wherein the first seed layer comprises TaN, TiW, Au from bottom to top;
the second seed layer sequentially comprises Ti, TiW and Cu from bottom to top;
the thickness of the first seed layer and the second seed layer is 50nm to 5000 nm.
4. A method of fabricating a radio frequency package as claimed in claim 1, wherein said step of electroplating gold on said first seed layer in first and second regions to form respective gold conductor layers comprises:
coating a first light resistance layer on the first seed layer in a spin coating or film-covering hot pressing mode, and electroplating gold on the exposed first area and the exposed second area after exposure and development to obtain a gold conductor layer;
removing the first photoresist layer;
the thickness of the first photoresist layer is larger than 5 mu m;
the thickness of the gold conductor layer is 2-5 μm.
5. The method of claim 3, wherein removing the first seed layer outside the gold conductor layer area and forming a thin film resistor between the first area and the second area to obtain a first sample comprises:
coating a second light resistance layer on the gold conductor layer and the first seed layer in a spin coating or film-covering hot pressing mode, and sequentially corroding Au and TiW in the area outside the exposed gold conductor layer area after exposure and development;
removing the second photoresist layer;
and coating a third photoresist layer on the gold conductor layer and the first seed layer in a spin coating or film-covering hot pressing mode, etching TaN in the exposed TaN area after exposure and development, and taking the TaN between the rest of the first area and the second area as a thin film resistor to obtain a first sample.
6. A method of making a radio frequency case as claimed in claim 1, wherein said baking and air annealing said first sample at a first predetermined temperature to obtain a second sample comprises:
and (3) annealing the first sample by adopting air with the temperature of 350 ℃ and the time of 30min to obtain a second sample.
7. A method of fabricating a radio frequency case as defined in claim 1, wherein electroplating copper on the second seed layer to form a copper conductor layer comprises:
electroplating copper on the second seed layer to prepare a copper conductor layer in a mode of using pulse plating and direct current plating in a combined mode;
grinding the copper conductor layer to thin the copper conductor layer;
carrying out surface polishing treatment on the thinned copper conductor layer;
the total thickness of the copper conductor layer is 50 μm to 5000 μm.
8. A method of fabricating a radio frequency package as claimed in claim 1 or 7, wherein the area of overlap of the copper conductor layer and the gold conductor layer is greater than or equal to 6 μm by 8 μm.
9. A method of fabricating a radio frequency case as claimed in claim 3, wherein said removing the second seed layer outside the area of said copper conductor layer comprises:
removing Cu in the second seed layer outside the copper conductor layer area by using strong acid washing etching liquid;
sequentially removing TiW and Ti in the second seed layer outside the copper conductor layer area by using oxide etching liquid;
after the step of removing the second seed layer outside the copper conductor layer area, the method further comprises the following steps:
and plating a nickel-gold layer on the copper conductor layer.
10. A radio frequency package, comprising:
a substrate;
the first seed layer and the gold conductor layer are prepared on a first area and a second area on the substrate in sequence, and the gold conductor layer is prepared by adopting a photoetching defined pattern, wherein the first area is not connected with the second area;
a thin film resistor fabricated between the first region and the second region;
and the second seed layer and the copper conductor layer are sequentially prepared on a partial area and a third area which are far away from the first area in the area corresponding to the gold conductor layer in the second area, the third area is different from the first area and the second area and is connected with the partial area, and the total thickness of the copper conductor layer is greater than that of the gold conductor layer.
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| CN104717848B (en) * | 2013-12-12 | 2017-12-12 | 深南电路有限公司 | A kind of preparation method of local heavy copper circuit board and local heavy copper circuit board |
| CN105578738B (en) * | 2015-12-21 | 2019-01-25 | 上海交通大学 | The preparation method of stretchable circuit board based on elastic substrate and stretchable circuit board |
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| CN107706173A (en) * | 2017-09-30 | 2018-02-16 | 成都嘉纳海威科技有限责任公司 | Silicon hole interconnection architecture and preparation method thereof and silicon hole RF transmitting structures |
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| CN110010548B (en) * | 2018-12-26 | 2021-08-24 | 浙江集迈科微电子有限公司 | Manufacturing method of cavity structure with bonding pad at bottom |
| CN111696952A (en) * | 2019-03-13 | 2020-09-22 | 住友电工光电子器件创新株式会社 | Microwave integrated circuit |
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2020
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