CN112686386A

CN112686386A - Electronic device

Info

Publication number: CN112686386A
Application number: CN202011024811.7A
Authority: CN
Inventors: 陈士元; 李峻霣; 许瑞福; 陈炯佑; 叶庭懿; 吴俞叡; 张燿均
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-10-17
Filing date: 2020-09-25
Publication date: 2021-04-20
Also published as: TW202118002A; US11276653B2; US20210118826A1; US20240021547A1; US20220199555A1

Abstract

The electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to produce quantum dots. The ring resonator is above the substrate, and includes a conductive ring and an impedance matching element. The conductive ring overlaps the transistor. An impedance matching element is on the conductive ring and is configured to determine a resonant frequency of the ring resonator.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices.

Background

Several milestones have been achieved in building the path diagrams of scalable silicon-based quantum computers. Some examples are listed below: the development of single ion implantation techniques that allow precise placement of individual phosphorus atoms in silicon; advanced nano-fabrication, microwave and low temperature technologies are applied to the production and characteristic analysis of a single-electron transistor (radio-frequency single-electron transistor, rf-SET) with charge sensitivity close to the quantum limit; the control and detection of single electron transfer between single phosphorus donors (donors) is obtained by combining single ion implantation and single electron transistor technology; and, the layout of the quantum device structure for universal fault-tolerant quantum computation (universal-free quantum computation) and subsequent error threshold analysis.

Disclosure of Invention

According to some embodiments of the present disclosure, an electronic device is provided, including: a substrate, a transistor, and a ring resonator. A transistor is located on the substrate, wherein the transistor is configured to produce quantum dots. A ring resonator is located on the substrate, wherein the ring resonator comprises: a conductive ring and an impedance matching element. The conductive ring overlaps the transistor. An impedance matching element is located on the conductive ring and is configured to determine a resonant frequency of the ring resonator.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be understood that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity.

Fig. 1A and 1B are flow diagrams of methods for manufacturing an electronic device in various embodiments according to some aspects of the present disclosure;

2A-13B illustrate methods in various stages of manufacturing an electronic device according to some embodiments of the present disclosure;

FIG. 14A is a top view of the ring resonator and tunnel barrier of FIG. 12A;

14B-14F are top views of a ring resonator and a tunneling barrier according to some embodiments;

fig. 15 is a flow diagram of a method M50 for manufacturing an electronic device in various embodiments according to some aspects of the present disclosure;

fig. 16-19 illustrate methods in various stages of manufacturing an electronic device, according to some embodiments of the present disclosure;

fig. 20 is a top view of an electronic device according to some embodiments of the present disclosure;

fig. 21A-21E are top views of electronic devices according to some embodiments.

[ notation ] to show

101 protective layer

102 contact

104 contact

106 contact

108 contact

110 base plate

110t top surface

112 source/drain regions

114 active region

116 tunnel barrier

120 mask layer

122 opening (c)

130 first isolation layer

132 opening of

140 first dielectric layer

150: depletion gate

150' of a conductive material

152 part (a)

154 part (b)

160 second dielectric layer

170 accumulating grid

170' conductive material

172 part

174 part

180 second spacer layer

185 matching structure, matching structure

190 conducting ring

192 annular portion

192a first part

192b second part

192b1 inner edge

192c third part

192d first part

192e second part

192el inner edge

194 feeding line

198 clearance

199 gap

210 base plate

220 conducting ring

222 annular part

222a first part

222b second part

222b1 inner edge

222c third part

222d first part

222e second part

222e1 inner edge

224 feeding line

226 tunnel barrier

228 gap

229 of the gap

B-B: line

C-C line

C1 matching element, capacitor and inductor

C2 matching element, capacitor and inductor

C3 matching element, capacitor and inductor

D is distance

I impedance matching element

M10 method

M50 method

R is a ring resonator

S, containing space

Operation S11

Operation S12

Operation S14

Operation S16

Operation S18

Operation S20

Operation S22

Operation S24

Operation S26

Operation S28

Operation S30

Operation S52

Operation S54

Operation S56

Operation S58

T is transistor

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms such as "below …," "below …," "below," "above …," "above …," and the like may be used herein to facilitate describing the relationship of one element or feature to another or multiple elements or features as shown. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

As used herein, "about," "approximately," or "substantially" shall generally mean within twenty percent, or within ten percent or within five percent of a given value or range. Numerical values given herein are approximate, meaning that the term "about", "approximately" or "substantially" can be inferred if not expressly stated.

Embodiments of the present disclosure provide an electronic device having a ring resonator to efficiently implement a quantum bit (qubit). The quantum bit is configured for controlling and reading the electron or hole spin (hole spin) of a single dopant in a (semiconductor) substrate. In some embodiments, the transistors used in the quantum bit cells may be implemented on a device selected from the group consisting of planar devices, multi-gate devices, fin field effect transistors (finfets), nanosheet gate field effect transistors, and gated full-ring field effect transistors.

Fig. 1A and 1B are flow diagrams of a method M10 for manufacturing an electronic device in various embodiments according to some aspects of the present disclosure. Various operations of method M10 are discussed in conjunction with the cross-sectional views of fig. 2A-13B. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. In operation S12 of the method M10, the substrate 110 is provided as shown in fig. 2A and 2B, wherein fig. 2B is a cross-sectional view taken along line B-B of fig. 2A. In some embodiments, the substrate 110 may include silicon (Si). Alternatively, the substrate 110 may include germanium (Ge), silicon germanium, gallium arsenide (GaAs), or other suitable semiconductor materials. In some other embodiments, the substrate 110 may include an epitaxial layer. In addition, the substrate 110 may include a semiconductor-on-insulator (SOI) structure having a buried dielectric layer therein. The buried dielectric layer may be, for example, a Buried Oxide (BOX) layer. The semiconductor-on-insulator structure may be formed by a technique known as separation by implantation of Silicon (SIMOX), wafer bonding, Selective Epitaxial Growth (SEG), or other suitable methods.

In operation S14 of the method M10, source/drain regions 112 are formed in the substrate 110, as shown in fig. 2A, 2B, 3A, and 3B, wherein fig. 3B is a cross-sectional view taken along line B-B of fig. 3A. A patterned masking layer 120 (which may be a hard mask layer) is formed over the top surface 110t of the substrate 110. In some embodiments, the patterned masking layer 120 comprises nitride. The mask layer 120 is made of, for example, silicon nitride (SiN). However, other materials, such as silicon oxynitride (SiON), silicon carbide, or combinations thereof, may also be used. The mask layer 120 may be formed by a process such as Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Low Pressure Chemical Vapor Deposition (LPCVD). Alternatively, the mask layer 120 may be made of silicon oxide and then converted into silicon nitride (SiN) through nitridation.

Then, a plurality of openings 122 are formed in the mask layer 120. The patterning of the opening 122 may be accomplished using a combination of photolithography and etching processes. For example, a photoresist may be formed over the mask layer 120. Then, the photoresist is patterned to expose the mask layer 120. The photoresist may be formed using spin-on techniques, and may be patterned using acceptable photolithography techniques. The etching may be an acceptable etching process (e.g., Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), etc., or a combination thereof).

Refer to fig. 3A and 3B. Next, an implantation process is performed to introduce impurities into the substrate 110 to form the source/drain regions 112, and the mask layer 120 (see fig. 2A and 2B) may serve as a mask to substantially prevent the impurities from being implanted into other regions of the substrate 110. The impurity may be an n-type impurity or a p-type impurity. The n-type impurity may be phosphorus, arsenic, etc., and the p-type impurity may be boron, boron difluoride (BF)₂) And the like.

Then, the photoresist and the mask layer 120 are removed. In some embodiments, the photoresist may be removed using a process such as ashing, etching, and the like. Subsequently, the mask layer 120 may be removed using a process such as wet etching or the like. After the removal process, the substrate 110 with the source/drain regions 112 is exposed. One or more annealing processes may be performed to activate the source/drain regions 112. The annealing process includes Rapid Thermal Annealing (RTA) and/or laser annealing. The anneal process may repair implant damage caused by impurities on the bottom and sidewalls of the source/drain regions 112.

In operation S16 of the method M10, a first isolation layer 130 is formed over the substrate 110, as shown in fig. 4A and 4B, wherein fig. 4B is a cross-sectional view taken along line B-B of fig. 4A. Specifically, the first isolation layer 130 may include an oxide such as Tetraethoxysilane (TEOS), undoped silicate glass or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG)), and/or other suitable dielectric materials. The first isolation layer 130 may be deposited by a plasma enhanced chemical vapor deposition process or other suitable deposition technique.

In operation S18 of the method M10, an opening 132 is formed in the first isolation layer 130 to define an active region 114 in the substrate 110, as shown in fig. 5A and 5B, wherein fig. 5B is a cross-sectional view taken along line B-B of fig. 5A. In some embodiments, the opening 132 may be formed using a combination of photolithography and etching processes as described above. The opening 132 exposes a portion of the substrate 110 and a portion of the source/drain region 112 between the source/drain regions 112. The exposed portion of the substrate 110 is defined as an active region 114. The top view of the active region 114 may be circular, oval, rectangular, square, or other shapes with or without rounded corners.

In operation S20 of the method M10, a first dielectric layer 140 and a plurality of depletion gates (or barrier gates) 150 are formed over the active region 114 of the substrate, as shown in fig. 6A, 6B, 7A, and 7B. Reference is made to fig. 6A and 6B, wherein fig. 6B is a cross-sectional view taken along line B-B of fig. 6A. A first dielectric layer 140 is conformally formed in the opening 132. A first dielectric layer 140 is over the active region 114 and the source/drain regions 112. In some embodiments, the first dielectric layer 140 may comprise silicon dioxide, silicon nitride, or other suitable materials. Alternatively, the first dielectric layer 140 may be a dielectric constant (k) higher than silicon dioxide (SiO)₂) A high-k dielectric layer having a dielectric constant of (i.e., > 3.9). The first dielectric layer 140 may include lanthanum oxide (LaO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Strontium titanate (SrTiO)₃(STO)), barium titanate (BaTiO)₃(BTO)), barium zirconium oxide (BaZrO), hafnium zirconium oxide (HfZrO), hafnium lanthanum oxide (HfLaO), hafnium silicon oxide (HfSiO), lanthanum silicon oxide (LaSiO), silicon-aluminum oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium titanate (BaTiO)₃) Strontium titanate (SrTiO)₃) Barium Strontium Titanate (BST), aluminum oxide (Al)₂O₃) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), or other suitable material. The first dielectric layer 140 may be deposited by techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, thermal oxidation, combinations thereof, or other suitable techniques.

Then, a conductive material 150' is formed over the first dielectric layer 140. The conductive material 150' includes one or more layers of conductive material. Examples of the conductive material 150' include tungsten (W), titanium (Ti), titanium aluminum carbide (TiAlC), aluminum (Al), titanium aluminide (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), tantalum carbide (TaC), aluminum (Al), titanium aluminide (TiAl), hafnium titanium (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi), titanium aluminum carbide (TiAlC), combinations thereof, and the like. The conductive material 150' may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) including sputtering, Atomic Layer Deposition (ALD), or other suitable methods.

Reference is made to fig. 7A and 7B, wherein fig. 7B is a cross-sectional view taken along line B-B of fig. 7A. The conductive material 150' is then patterned to form the depletion gate 150. The patterning of the conductive material 150' may be formed using a combination of photolithography and etching processes as described above. A portion 152 of each depletion gate 150 is over the active region 114 and between the source/drain regions 112 of the substrate 110. Another portion 154 of each depleted gate 150 extends over the first isolation layer 130 to become a landing pad for a subsequently formed contact 104 (see fig. 13A). The depletion gates 150 are spaced apart from each other. A portion 152 of the depletion gate 150 defines a tunnel barrier 116 in the active region 114. The distance D between the portions 152 of the depletion gate 150 may be in a range of about 20 nanometers (nm) to about 100 nm. If the distance D is less than about 20nm, quantum dots (quantum dots) may not be formed in the active region 114 and between the depletion gates 150. If the distance D is greater than about 100nm, more than one charge (quantum dot) may form in the active region 114 and between the depletion gates 150.

In operation S22 of the method M10, a second dielectric layer 160 and an accumulation gate 170 are formed on the first dielectric layer 140 and the depletion gate 150, as shown in fig. 8A, 8B, 9A, and 9B. Reference is made to fig. 8A and 8B, wherein fig. 8B is a cross-sectional view taken along line B-B of fig. 8A. A second dielectric layer 160 is conformally formed over the first dielectric layer 140 and the depleted gate 150 such that the second dielectric layer 160 covers the first dielectric layer 140 and the depleted gate 150. In some embodiments, the second dielectric layer 160 may comprise silicon dioxide, silicon nitride, or other suitable materials. Alternatively, the second dielectric layer 160 may be a dielectric constant (k) higher than silicon dioxide (SiO)₂) A high-k dielectric layer having a dielectric constant of (i.e., > 3.9). The second dielectric layer 160 may include lanthanum oxide (LaO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Strontium titanate (SrTiO)₃(STO)), barium titanate (BaTiO)₃(BTO)), barium zirconium oxide (BaZrO), hafnium zirconium oxide (HfZrO), hafnium lanthanum oxide (HfLaO), hafnium silicon oxide (HfSiO), lanthanum silicon oxide (LaSiO), silicon-aluminum oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium titanate (BaTiO)₃) Strontium titanate (SrTiO)₃) Barium Strontium Titanate (BST), aluminum oxide (Al)₂O₃) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), or other suitable material. The second dielectric layer 160 may be deposited by techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, thermal oxidation, combinations thereof, or other suitable techniques.

Then, another conductive material 170' is formed on the second dielectric layer 160. The conductive material 170' includes one or more layers of conductive material. Examples of the conductive material 170' include tungsten (W), titanium (Ti), titanium aluminum carbide (TiAlC), aluminum (Al), titanium aluminide (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), tantalum carbide (TaC), aluminum (Al), titanium aluminide (TiAl), hafnium titanium (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi), titanium aluminum carbide (TiAlC), combinations thereof, and the like. The conductive material 170' may be formed by chemical vapor deposition, physical vapor deposition including sputtering, atomic layer deposition, or other suitable methods. Conductive materials 150 'and 170' (i.e., depletion gate 150 and subsequently formed accumulation gate 170) are made of the same or different materials.

Reference is made to fig. 9A and 9B, where fig. 9B is a cross-sectional view taken along line B-B of fig. 9A. Then, the conductive material 170' is patterned to form the accumulation gate 170. The patterning of the conductive material 170' may be formed using a combination of photolithography and etching processes as described above. A portion 172 of accumulation gate 170 is over active region 114 and source/drain region 112 and across depletion gate 150. This portion 172 of accumulation gate 170 and depletion gate 150 extend in different directions. For example, portion 172 of accumulation gate 170 may be substantially perpendicular to portion 152 of depletion gate 150. Another portion 174 of accumulation gate 170 extends over first isolation layer 130 to become a landing pad for subsequently formed contact 106 (see fig. 13A). Source/drain regions 112, active region 114, depletion gate 150 and accumulation gate 170 form transistor T.

In operation S24 of the method M10, a second isolation layer 180 is formed over the second dielectric layer 160 and the accumulation gate 170, as shown in fig. 10A and 10B, wherein fig. 10B is a cross-sectional view taken along line B-B of fig. 10A. Specifically, the second isolation layer 180 covers the accumulation gate 170, and may include an oxide such as Tetraethoxysilane (TEOS), undoped silicate glass or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG)), and/or other suitable dielectric materials. The second isolation layer 180 may be deposited by a plasma enhanced chemical vapor deposition process or other suitable deposition technique.

In operation S26 of the method M10, a matching structure 185 is formed over the second isolation layer 180, as shown in fig. 11A and 11B, where fig. 11B is a cross-sectional view taken along line C-C of fig. 11A. In some embodiments, the matching structure 185 may be formed outside of the active region 114 from a top view. That is, the matching structure 185 is disposed over the first isolation layer 130. In some embodiments, a dielectric layer is formed over the second isolation layer 180 and patterned using a combination of photolithography and etch processes to form the matching structure 185. The material of the matching structure 185 may depend on the capacitance of the subsequently formed capacitor C3 (see fig. 12D). In some embodiments, the matching structure 185 may include a material such as a Tetraethoxysilane (TEOS) formed oxide, undoped silicate glass or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG)), and/or other suitable dielectric material. The matching structure 185 may be deposited by an atomic layer deposition process or other suitable deposition technique.

In operation S28 of the method M10, a conductive ring 190 is formed over the second isolation layer 180, as shown in fig. 12A-12D, where fig. 12B is a cross-sectional view taken along line B-B of fig. 12A, fig. 12C is a cross-sectional view taken along line C-C of fig. 12A, and fig. 12B is an enlarged view of the conductive ring 190 and the matching structure 185 in fig. 12A. For example, another conductive material is formed over the second isolation layer 180 and patterned using a combination of photolithography and etching processes to form the conductive ring 190. In some embodiments, the conductive ring 190 comprises one or more layers of conductive material. Examples of the conductive ring 190 include tungsten (W), titanium (Ti), titanium aluminum carbide (TiAlC), aluminum (Al), titanium aluminum (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), tantalum carbide (TaC), aluminum (Al), titanium aluminum (TiAl), hafnium titanium (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi), titanium aluminum carbide (TiAlC), combinations thereof, and the like. The conductive ring 190 may be formed by chemical vapor deposition, physical vapor deposition including sputtering, atomic layer deposition, or other suitable methods.

In fig. 12A, the conductive ring 190 overlaps the tunnel barrier 116. Thus, the magnetic field formed in the conductive ring 190 resonates with the dopants in the tunnel barrier 116 and forms a quantum bit in the tunnel barrier 116. The conductive ring 190 includes a ring portion 192 and two feeding lines 194. The annular portion 192 forms a receiving space S. The receiving space S overlaps the tunnel barrier 116. A gap 198 is formed between one end of the annular portion 192 and one of the in-feed lines 194, and another gap 199 is formed between the other end of the annular portion 192 and the other in-feed line 194. Thus, the annular portion 192 and the feed line 194 form two (series) capacitors C1 and C2 with

gaps

198 and 199. In some embodiments, the capacitance of the capacitors C1 and C2 is substantially the same, such that the current flowing in the in-feed line 194 may be substantially the same, but in opposite directions. In some embodiments,

gaps

198 and 199 have substantially the same distance, and the distance of

gaps

198 and 199 is dependent on the desired capacitance of capacitors C1 and C2. Furthermore, in some other embodiments,

gaps

198 and 199 may be filled with a dielectric material to adjust the capacitance of capacitors C1 and C2.

Further, the ring portion 192 is in contact with the matching structure 185 such that the ring portion 192 and the matching structure 185 form a (parallel) capacitor C3, as shown in fig. 12C. The capacitance of the capacitor C3 depends on the dielectric constant of the matching structure 185 and the distance between the feed-in lines 194. In FIG. 12A, the conductive ring 190 and the matching structure 185 form a ring resonator R. The capacitors C1, C2, and C3 form an impedance matching element I of the ring resonator R. The impedance matching element I is configured to determine the resonance frequency of the ring resonator R. In some embodiments, the impedance matching element I includes capacitors C1, C2, and C3. However, in some other embodiments, the impedance matching element I includes capacitors C1 and C2 or only capacitor C3.

In operation S30 of the method M10, a plurality of

contacts

102, 104, 106, and 108 are formed over the transistor T and the ring resonator R, as shown in fig. 13A and 13B, where fig. 13B is a cross-sectional view taken along line B-B of fig. 13A. In some casesIn the embodiment, the protective layer 101 is formed over the transistor T and the ring resonator R. In some embodiments, protective layer 101 may comprise silicon dioxide, silicon nitride, or other suitable material. Alternatively, the protective layer 101 may be a material having a dielectric constant (k) higher than that of silicon dioxide (SiO)₂) A high-k dielectric layer having a dielectric constant of (i.e., > 3.9). The protective layer 101 may include lanthanum oxide (LaO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Strontium titanate (SrTiO)₃(STO)), barium titanate (BaTiO)₃(BTO)), barium zirconium oxide (BaZrO), hafnium zirconium oxide (HfZrO), hafnium lanthanum oxide (HfLaO), hafnium silicon oxide (HfSiO), lanthanum silicon oxide (LaSiO), silicon-aluminum oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium titanate (BaTiO)₃) Strontium titanate (SrTiO)₃) Barium Strontium Titanate (BST), aluminum oxide (Al)₂O₃) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), or other suitable material. The protective layer 101 may be deposited by techniques such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, thermal oxidation, combinations thereof, or other suitable techniques. In some embodiments, the material of the protective layer 101 fills in the

gaps

198 and 199 of the conductive ring 190. However, in some other embodiments, the protective layer 101 is over the

gaps

198 and 199 and air is filled in the

gaps

198 and 199. The fill material (material of protective layer 101 or air) in

gaps

198 and 199 determines the capacitance of capacitors C1 and C2.

Then, the protective layer 101 is etched to form a plurality of openings by various methods including dry etching, wet etching, or a combination of dry etching and wet etching. Openings extend through the protective layer 101 (and the underlying dielectric layer) and expose the source/drain regions 112, the depletion gate 150, the accumulation gate 170, and the conductive ring 190, respectively. A fill material is then formed in the opening. The fill material is connected to the source/drain regions 112, the depletion gate 150, the accumulation gate 170, or the conductive ring 190. In some embodiments, a filler material may be filled in the openings, and excess portions of the filler material are removed by performing a chemical mechanical planarization process to form the

contacts

102, 104, 106, and 108. Contacts 102 are connected to the source/drain regions 112, respectively, contacts 104 are connected to portions 154 of the depletion gate 150, contacts 106 are connected to portions 174 of the accumulation gate 170, and contacts 108 are connected to feed-in lines 194 of the conductive ring 190, respectively.

Contacts

102, 104, 106, and 108 may be made of tungsten, aluminum, copper, or other suitable material.

In fig. 12A, accumulation gate 170 creates a gate-induced charge layer in active region 114 when the electronic device is in operation. The depleted gate 150 then forms a tunnel barrier 116, which tunnel barrier 116 blocks the gate induced charge layer with a single dopant implanted in the active region 114. The depleted gate 150 also has a Fermi level (E) that is the dopant level and lead_F) The function of resonance. The dopant energy state of Zeeman splitting (Zeeman-split) can also be resolved in the presence of a magnetic field. By applying a source-drain bias and adjusting the dopant level at resonance with the fermi level of the gate induced charge layer, a sharp conductance peak is expected to be observed. Spin-dependent tunneling is observed through zeeman splitting of electron or hole spin states induced by an external magnetic field. Due to charge accumulation effects, resonant charge tunneling is continuous, that is, only one charge at a time can pass through the energy barrier by passing through the dopant energy level. Coherent manipulation of the quantum states of a spin quantum bit can be achieved by applying a magnetic field having a frequency that matches zeeman splitting of the spin states. The frequency is determined by the impedance matching element. In some embodiments, the magnetic field oscillates at microwave frequencies to excite spin resonance, i.e., Electron Spin Resonance (ESR), of a single electron (dopant).

The magnetic field may be strong to allow the spin states to oscillate rapidly. At the same time, it is desirable that there is no electric field in the tunnel barrier region to ensure proper operation of the electronic device. In particular, the electric field may cause certain effects, such as, for example, photo-assisted tunneling (photo-assisted tunneling), disrupting the operation of the electronic device and causing localized heating of the electronic device. Embodiments of the present disclosure solve the problems in the prior art methods by providing a ring resonator R with a strong magnetic field and a weak or negligible electric field at the tunnel barrier 116.

In more detail, when a current flows in the ring resonator R in fig. 12A, a strong magnetic field and a weak or negligible electric field can be obtained in the receiving space S of the conductive ring 190. Therefore, when the tunnel barrier 116 overlaps the accommodation space S, a strong magnetic field and a weak or negligible electric field generated by the ring resonator R are applied to a single dopant (i.e., quantum dot) implanted in the active region 114, and the efficiency of the quantum bit cell can be demonstrated.

Fig. 14A is a top view of the ring resonator R and the tunnel barrier 116 in fig. 12A. In FIG. 14A, the loop portion 192 of the conductive loop 190 forms a rectangular loop. That is, the accommodating space S is rectangular. The annular portion 192 includes two first portions 192a, one second portion 192b and two third portions 192 c. Each of the first portions 192a interconnects the second portion 192b and one of the third portions 192C, and the third portion 192C forms capacitors C1 and C2 with the feed-in line 194, respectively. In fig. 14A, the first portion 192a is longer than the second portion 192 b. In some embodiments, the tunnel barrier 116 overlaps the inner edge 192b1 of the second portion 192 b. That is, the tunnel barrier 116 is spaced apart from the feed-in line 194. In some embodiments, the tunnel barrier 116 overlaps corners of a third portion 192c of the receiving space S away from the annular portion 192. In other embodiments, the tunnel barrier 116 overlaps the inner edge 192b1 of the second portion 192b, but is spaced apart from the first portion 192 a. With this arrangement, the tunnel barrier 116 is spaced from the electric field formed in the feed-in line 194.

Fig. 14B-14F are top views of the ring resonator R and the tunnel barrier 116 according to some embodiments. In fig. 14B, the annular portion 192 of the conductive ring 190 forms a square ring. That is, the accommodating space S is square. The first portion 192a has substantially the same length as the second portion 192 b. In some embodiments, the tunnel barrier 116 overlaps the inner edge 192b1 of the second portion 192 b. That is, the tunnel barrier 116 is spaced apart from the feed-in line 194. In some embodiments, the tunnel barrier 116 overlaps corners of a third portion 192c of the receiving space S away from the annular portion 192. The tunnel barrier 116 overlaps the inner edge 192b1 of the second portion 192b, but is spaced apart from the first portion 192 a. With this arrangement, the tunnel barrier 116 is spaced from the electric field formed in the feed-in line 194.

In FIG. 14C, the annular portion 192 of the conductive ring 190 forms a rectangular ring. That is, the accommodating space S is rectangular. The first portion 192a is shorter than the second portion 192 b. In some embodiments, the tunnel barrier 116 overlaps the inner edge 192b1 of the second portion 192 b. That is, the tunnel barrier 116 is spaced apart from the feed-in line 194. In some embodiments, the tunnel barrier 116 overlaps corners of a third portion 192c of the receiving space S away from the annular portion 192. In some other embodiments, the tunnel barrier 116 overlaps the inner edge 192b1 of the second portion 192b, but is spaced apart from the first portion 192 a. With this arrangement, the tunnel barrier 116 is spaced from the electric field formed in the feed-in line 194.

In fig. 14D, the annular portion 192 of the conductive ring 190 forms a circular ring. That is, the receiving space S is circular. The annular portion 192 includes two first portions 192d and one second portion 192e interconnecting the two first portions 192 d. The second portion 192e is spaced apart from the feed-in line 194, and the first portion 192d and the feed-in line 194 form capacitors C1 and C2, respectively. In some embodiments, the second portion 192e is a semi-circular ring and the first portion 192d has substantially the same shape. In some embodiments, the tunnel barrier 116 overlaps the inner edge 192e1 of the second portion 192 e. That is, the tunnel barrier 116 is spaced apart from the feed-in line 194. With this configuration, the tunnel barrier 116 is spaced apart from the electric field formed in the feed-in line 194.

In fig. 14E and 14F, the annular portion 192 of the conductive ring 190 forms an elliptical ring. That is, the accommodation space S is elliptical. The annular portion 192 includes two first portions 192d and one second portion 192e interconnecting the first portions 192 d. The second portion 192e is spaced apart from the feed-in line 194, and the first portion 192d and the feed-in line 194 form capacitors C1 and C2, respectively. In some embodiments, the second portion 192e is a semi-elliptical ring and the first portion 192d has substantially the same shape. In some embodiments, the tunnel barrier 116 overlaps the inner edge 192e1 of the second portion 192 e. That is, the tunnel barrier 116 is spaced apart from the feed-in line 194. With this configuration, the tunnel barrier 116 is spaced apart from the electric field formed in the feed-in line 194.

Fig. 15 is a flow diagram of a method M50 for manufacturing an electronic device in various embodiments according to some aspects of the present disclosure. Various operations of method M50 are discussed in conjunction with the cross-sectional views of fig. 16-19. Like reference numerals are used to indicate like elements throughout the various views and illustrative embodiments. In operation S52 of method M50, a substrate 210 is provided, as shown in fig. 16, which is a top view of an electronic device according to some embodiments. In some embodiments, the substrate 210 may be of the same material as the substrate 110 shown in fig. 2A. In some other embodiments, the substrate 210 may be a Printed Circuit Board (PCB).

In operation S54 of the method M50, the conductive ring 220 is formed over the substrate 210, as shown in FIGS. 17A and 17B, wherein FIG. 17B is a cross-sectional view taken along line B-B of FIG. 17A. For example, a conductive material is formed on the substrate 210 and patterned using a combination of photolithography and etching processes to form the conductive ring 220. In some embodiments, the conductive ring 220 includes one or more layers of conductive material. Examples of the conductive ring 220 include tungsten (W), titanium (Ti), titanium aluminum carbide (TiAlC), aluminum (Al), titanium aluminum (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), tantalum carbide (TaC), aluminum (Al), titanium aluminum (TiAl), hafnium titanium (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi), titanium aluminum carbide (TiAlC), combinations thereof, and the like. The conductive ring 220 may be formed by chemical vapor deposition, physical vapor deposition including sputtering, atomic layer deposition, or other suitable methods.

In fig. 17A, the conductive ring 220 includes a ring-shaped portion 222 and two feed lines 224. The annular portion 222 forms an accommodation space S. A gap 228 is formed between one end of the annular portion 222 and one of the in-feed lines 224, and another gap 229 is formed between the other end of the annular portion 222 and the other in-feed line 224. In some embodiments, the

gaps

228 and 229 have substantially the same distance such that the electric fields respectively formed in the in-feed line 224 may be cancelled out.

In operation S56 of the method M50, an impedance matching element I is formed on the substrate 220, wherein the impedance matching element I is in contact with the conductive loop 220, as shown in fig. 18. In some embodiments, the impedance matching element I includes a first matching element C1, a second matching element C2, and a third matching element C3. The first matching element C1, the second matching element C2, and the third matching element C3 may be bonded to the conductive ring 220. A first matching element C1 is disposed in the gap 228 (refer to fig. 17A) and interconnects the annular portion 222 with one of the in-feed lines 224, a second matching element C2 is disposed in the gap 229 (refer to fig. 17A) and interconnects the annular portion 222 and the other in-feed line 224, and a third matching element C3 is disposed between the in-feed lines 224 and interconnects the in-feed lines 224. In some embodiments, the matching elements C1, C2, and C3 are capacitors. The matching elements C1 and C2 are capacitors in series, while the third capacitor C3 is a capacitor in parallel. The capacitance of the capacitors C1, C2, and C3 depends on the desired resonant frequency of the qubit of the electronic device. In some embodiments, the capacitors C1 and C2 have substantially the same capacitance, such that the current flowing in the feed line 224 may be substantially the same, but in opposite directions. In some other embodiments, the matching elements C1, C2, and C3 are inductors. The matching elements C1 and C2 are series inductors, while the third inductor C3 is a parallel inductor. The inductance of inductors C1, C2, and C3 depends on the desired resonant frequency of the qubit of the electronic device. In some embodiments, the inductors C1 and C2 have substantially the same inductance, such that the current flowing in the feed line 224 may be substantially the same, but in opposite directions. In some other embodiments, the matching elements C1 and C2 are inductors and the matching element C3 is a capacitor. Alternatively, the matching elements C1 and C2 are capacitors, and the matching element C3 is an inductor.

In fig. 18, the conductive loop 220 and the impedance matching element I form a ring resonator R. The impedance matching element I is configured to determine the resonance frequency of the ring resonator R. In some embodiments, the impedance matching element I includes matching elements C1, C2, and C3; however, in some other embodiments, the impedance matching element I includes matching elements C1 and C2, or only matching element C3.

In operation S58 of the method M50, as shown in fig. 19, a transistor T is formed over the substrate 210 and in the accommodating space S. In some embodiments, the transistor T may be bonded to the substrate 210. The transistor T may have the same or similar configuration as the transistor T shown in fig. 9A and 9B, and thus, the transistor T is configured to generate a single charge (quantum dot) at a time. In some embodiments, operations S56 and S58 may be performed together. That is, the impedance matching element I and the transistor T may be bonded to the substrate 210 in the same process. In some other embodiments, operation S56 may be performed after operation S58.

In FIG. 19, the annular portion 222 of the conductive ring 220 forms a rectangular ring. That is, the accommodating space S is rectangular. The annular portion 222 includes two first portions 222a, one second portion 222b, and two third portions 222 c. Each first portion 222a interconnects the second portion 222b and one of the third portions 222C, and the third portions 222C are connected to mating elements C1 and C2, respectively. In fig. 19, the first portion 222a is longer than the second portion 222 b. In some embodiments, (the tunnel barrier of) the transistor T is adjacent to the inner edge 222b1 of the second portion 222 b. That is, the transistor T is spaced apart from the feed-in line 224. In some embodiments, the transistor T overlaps a corner of the third portion 222c of the receiving space S away from the ring portion 222. In some other embodiments, the transistor T overlaps the inner edge 222b1 of the second portion 222b, but is spaced apart from the first portion 222 a. With this configuration, the tunnel barrier 226 is spaced apart from the electric field formed in the feed-in line 224.

The electronic device can efficiently realize the quantum bit. In some embodiments, the substrate is a ceramic-filled Polytetrafluoroethylene (PTFE) composite/laminate (e.g., Rogers RO 3010). The thickness of the substrate was about 640 micrometers (μm). The ring size is about 70 μm (width) and 130 μm (length). The line width of the conductive ring is about 10 μm. The conductive ring has a thickness of about 1 μm. The conductive ring is made of copper. The distance between the feed-in lines is about 15 μm. Reflection coefficient (| S)₁₁|) lower than-6 decibels (dB). The resulting resonant frequency is about 30 gigahertz (GHz). At about 30GHz and an input power of 0 decibel-milliwatts (dBm), the amplitude of the microwave magnetic field generated by the electronic device is greater than about 10 milli-Tesla (mT), which is sufficient for spin-based quantum bit controlAnd (4) receiving the result. Furthermore, a sufficient microwave magnetic field may result in a lack of input power, which may increase the electric field. The frequency response (frequency response) of the magnitude ratio of the Z-polarized magnetic field (millitesla (mT)) to the total electric field (million volts/meter (MV/m)) is greater than about 1650 millitesla x meter/million volts (mT x m/MV). In some other embodiments, the frequency response of the ratio of the magnitude of the Z-polarized magnetic field to the total electric field is greater than about 10000mT m/MV. For embodiments having a frequency response greater than about 10000mT x m/MV, the input power can be further increased to increase the magnetic field without a significant increase in the total electric field.

Fig. 20 is a top view of an electronic device according to some embodiments of the present disclosure. The difference between the electronic devices of fig. 20 and 19 relates to the configuration of the matching elements C1, C2 and C3. In fig. 20, the matching elements C1, C2, and C3 are referred to as interdigitated capacitors. Each of the matching elements C1, C2, and C3 has a plurality of fingers extending toward opposite electrodes of the capacitor. The fingers are advantageous in increasing their capacitance in a smaller layout area. The interdigitated capacitor may be formed during operation S54 (see fig. 15). If the matching elements C1, C2, and C3 are referred to as fork capacitors, operation S56 in fig. 15 may be omitted. In some other embodiments, some of the matching elements C1, C2, and C3 are referred to as fork capacitors, while the remaining matching elements C1, C2, and C3 are bonded capacitors (bonded capacitors). Other relevant structural details of the electronic device in fig. 20 are similar to those of the electronic device in fig. 19, and therefore, the description in this regard will not be repeated hereinafter.

Fig. 21A-21E are top views of electronic devices according to some embodiments. In FIG. 21A, annular portion 222 of conductive ring 220 forms a square ring. That is, the accommodating space S is square. The first portion 222a has substantially the same length as the second portion 222 b. In some embodiments, the transistor T (and its tunnel barrier) is adjacent to the inner edge 222b1 of the second portion 222 b. That is, the transistor T is spaced apart from the feed-in line 224. In some embodiments, the transistor T overlaps a corner of the third portion 222c of the receiving space S away from the ring portion 222. In some other embodiments, the transistor T is adjacent the inner edge 222b1 of the second portion 222b, but spaced apart from the first portion 222 a. With this configuration, the transistor T is spaced from the electric field formed in the feed-in line 224.

In FIG. 21B, the loop portion 222 of the conductive loop 220 forms a rectangular loop. That is, the accommodating space S is rectangular. The first portion 222a is shorter than the second portion 222 b. In some embodiments, the transistor T (and its tunnel barrier) is adjacent to the inner edge 222b1 of the second portion 222 b. That is, the transistor T is spaced apart from the feed-in line 224. In some embodiments, the transistor T overlaps a corner of the third portion 222c of the receiving space S away from the ring portion 222. In some other embodiments, the transistor T is adjacent the inner edge 222b1 of the second portion 222b, but spaced apart from the first portion 222 a. With this configuration, the transistor T is spaced from the electric field formed in the feed-in line 224.

In FIG. 21C, the annular portion 222 of the conductive ring 220 forms a circular ring. That is, the receiving space S is circular. The annular portion 222 includes two first portions 222d and one second portion 222e interconnecting the two first portions 222 d. The second portion 222e is spaced apart from the in-feed line 224, and the first portion 222d is connected to the matching elements C1 and C2, respectively. In some embodiments, the second portion 222e is a semi-circular ring and the first portion 222d has substantially the same shape. In some embodiments, the transistor T is adjacent the inner edge 222e1 of the second portion 222 e. That is, the transistor T is spaced apart from the feed-in line 224. With this configuration, the transistor T is spaced apart from the electric field formed in the feed-in line 224.

In fig. 21D and 21E, the annular portion 222 of the conductive ring 220 forms an elliptical ring. That is, the accommodation space S is elliptical. The annular portion 222 includes two first portions 222d and one second portion 222e interconnecting the first portions 222 d. The second portion 222e is spaced apart from the in-feed line 224, and the first portion 222d is connected to the matching elements C1 and C2, respectively. In some embodiments, the second portion 222e is a semi-elliptical ring and the first portion 222d has substantially the same shape. In some embodiments, the transistor T is adjacent the inner edge 222e1 of the second portion 222 e. That is, the transistor T is spaced apart from the feed-in line 224. With this configuration, the transistor T is spaced apart from the electric field formed in the feed-in line 224.

Based on the above discussion, it can be seen that the present disclosure provides benefits. However, it is to be understood that other embodiments may provide additional benefits, and that not all of the benefits are necessarily disclosed herein, and that no particular benefit is required for all embodiments. One of the benefits is that the ring resonator is capable of generating a strong magnetic field as well as a weak or negligible electric field across the transistor, so that the quantum bit generated in the transistor has a high efficiency. In addition, the ring resonator has a simple structure and can be integrated for integrated circuit design and printed circuit board design. In addition, the resonance frequency can be adjusted by the impedance matching element, so that the qubit can be applied over a wide frequency range.

According to some embodiments, an electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to produce quantum dots. The ring resonator is above the substrate, and includes a conductive ring and an impedance matching element. The conductive ring overlaps the transistor. An impedance matching element is on the conductive ring and is configured to determine a resonant frequency of the ring resonator.

In some embodiments, the conductive ring includes an annular portion and two feeding lines, the annular portion defines a receiving space therein, and the feeding lines are spaced apart from the annular portion respectively.

In some embodiments, the impedance matching element comprises a first capacitor and a second capacitor, wherein the first capacitor comprises a first end of the loop portion and a portion of one of the feed-in lines, and the second capacitor comprises a second end of the loop portion and a portion of the other of the feed-in lines.

In some embodiments, the first capacitor and the second capacitor have substantially the same capacitance.

In some embodiments, the first capacitor is a fork capacitor.

In some embodiments, the impedance matching element further comprises a matching structure in contact with the conductive ring, such that the matching structure and the conductive ring define a third capacitor of the impedance matching element.

In some embodiments, the impedance matching element includes a first matching element interconnecting one end of the loop portion with one of the feed lines and a second matching element interconnecting one end of the loop portion with another of the feed lines.

In some embodiments, the first matching element and the second matching element are capacitors, inductors, or a combination thereof.

In some embodiments, the impedance matching element further comprises a third matching element interconnected with the feed-in line.

In some embodiments, the third matching element is a capacitor or an inductor.

According to some embodiments, an electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is above the substrate and overlaps the transistor. The ring resonator includes a conductive ring and an impedance matching element. The conductive ring comprises an annular portion and two feed-in lines. The annular portion has two first portions and a second portion. Each of the first portions of the ring portion interconnects the second portion of the ring portion and one of the feed-in lines, and the tunnel barrier of the transistor is closer to the second portion than the feed-in line. The impedance matching element is closer to the feed-in line than the second portion.

In some embodiments, the annular portion is a rectangular ring, a square ring, a circular ring, or an elliptical ring.

In some embodiments, the transistor includes a plurality of depletion gates and an accumulation gate over the depletion gates.

According to some embodiments, a method for manufacturing an electronic device includes forming a transistor over a substrate. The transistor is configured to produce quantum dots. The conductive ring is above the substrate, such that the conductive ring overlaps the transistor. An impedance matching element is formed over the substrate and on the conductive ring.

In some embodiments, forming a transistor includes forming a plurality of source/drain regions in a substrate; forming an active region in the substrate and between the source/drain regions; forming a plurality of depletion gates on the active region; and forming an accumulation grid on the depletion grid.

In some embodiments, forming the conductive ring includes forming a conductive film on the substrate; and patterning the conductive film to form a conductive ring, so that the conductive ring comprises an annular part and two feed-in lines, wherein the two feed-in lines are respectively separated from the annular part by the two feed-in lines.

In some embodiments, the method further comprises forming an isolation layer over the transistor, and the conductive ring is formed over the isolation layer.

In some embodiments, forming the impedance matching element includes forming a matching structure on the substrate and forming the conductive ring in contact with the matching structure, wherein the matching structure includes a dielectric material.

In some embodiments, forming the transistor includes bonding the transistor on the substrate.

In some embodiments, the impedance matching element comprises a first matching element, and forming the impedance matching element comprises bonding the first matching element to the conductive loop.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same benefits of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An electronic device, comprising:

a substrate;

a transistor on the substrate, wherein the transistor is configured to generate a quantum dot; and

a ring resonator on the substrate, wherein the ring resonator comprises:

a conductive ring overlapping the transistor; and

an impedance matching element is located on the conductive ring and configured to determine a resonant frequency of the ring resonator.