CN112684861A - Data processing system and method - Google Patents
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Abstract
The invention discloses a data processing system and a data processing method, and belongs to the technical field of exposure. The system integrates a graphic acceleration card, a plurality of communication board cards and a driving board card on an industrial personal computer, wherein the graphic acceleration card carries out vector transformation or bitmap transformation according to Block graphics; a plurality of modules are instantiated in an FPGA for parallel synchronous processing, serial execution is not needed like CPU processing, the processing rate is improved, and the processing time delay is shortened, so that the problems that the prior data processing capacity is insufficient, a plurality of PCs are needed, and the data processing time delay is long are solved; through the communication board card, the transmission rate is improved, 10Gbit/s data transmission can be carried out on N receiving terminals through one pcie data processing board, and therefore under the condition that no pcie slot is added, more receiving terminals can be supported to transmit data simultaneously. Because this application has set up a plurality of communication integrated circuit boards, so can adopt the transmission of net twine mode realization data, weaken the requirement to equipment wiring.
Description
Technical Field
The invention relates to a data processing system and a data processing method, and belongs to the technical field of exposure.
Background
The laser direct writing exposure equipment is equipment which transmits user graphs to a graph generator after carrying out digital processing and carries out exposure by matching with the movement of a workbench and an optical imaging principle, wherein the digital processing and the transmission of the graphs are very important links, the data volume of the graphs becomes larger and larger along with the higher and higher requirements of the equipment on the graph precision, and the processing capacity and the transmission rate of data gradually become bottlenecks which restrict productivity.
In the existing laser direct writing exposure equipment, graphic data are processed on a plurality of different layers, and each layer is at a different physical position of the equipment, so that the graphic data of different layers inevitably have data interaction between layers, and the data size of the graphic processed by each layer is different.
For example, in the existing method of implementing digital processing and transmission of images by using two or more PCs, the PC + implements 40Gbits/s data transmission by using an FPGA-based chip, a network card based on FPGA is inserted into a standard PCIE slot of the PC on the PC side to implement 40Gbits/s single-channel data transmission, a 40Gbit/s interface is used on the bottom layer to be docked with a home-made network card in the PC to implement data transmission, and the transmission medium is optical fiber communication. The digital processing of the graphics on the PC side mostly needs two or more PCs to be realized, one PC is used as a control layer and a user interface layer, and the remaining one or more PCs are used as special graphics processing PCs.
However, the digital processing and transmission of images by two or more PCs have the following problems:
1. the single communication board card cannot realize the multi-channel data transmission of 10Gbit/s level of 1vs N. If multi-path data transmission needs to be realized, the number of the pcie slots of one PC is limited, and the number of the pcie slots of one PC is not more than 6 in most cases, so that the expansion capacity of the number of the optical paths of the equipment is restricted, and the capacity is influenced finally.
2. The transmission medium is an optical fiber, which puts higher requirements on the wiring of the equipment, and the optical fiber is more suitable for being used under a static condition. For a continuous uninterrupted motion process, if the optical fiber is arranged in the drag chain and continuously moves along with the receiving end, the probability of packet error is greatly increased due to packet loss caused by bending of the optical fiber in the motion process.
3. The graphic data of the PC layer are processed on different PCs, and the different PCs adopt a TCP/IP mode for communication, so that time delay exists, and the data processing time is long.
Disclosure of Invention
To solve the problems existing at present, the present invention provides a data processing system, comprising: the system comprises an industrial personal computer, a graphic acceleration card, a communication board card and a driving board card; the graphic accelerator card and the communication board card are inserted into a main board pci slot of the industrial personal computer in a pci interface mode; the communication board card is connected with the drive board card; the driving board card is connected with the DMD; the graphic accelerator card, the communication board card and the driving board card are all board cards based on an FPGA chip.
Optionally, the graphics accelerator card is used for assisting the industrial personal computer CPU to perform hardware acceleration processing on graphics data; the communication board card is used for converting the pcie data format into the format of a communication data packet and sending the communication data packet to the driver board card, and the driver board card converts the data transmitted by the communication board card into a data grid required by the DMD after receiving the data and sends the data grid to the DMD for displaying the graph.
Optionally, the communication interfaces of the communication board card and the drive board card are optical fiber modules or network interfaces, and the communication interfaces of the communication board card and the drive board card are used in a paired manner.
Optionally, the pci interfaces of the graphic accelerator card and the communication board card adopt standards of pci 3.0 x8 or more.
The application also provides a data processing method, which is applied to an LDI exposure system, and the method adopts the data processing system to carry out digital processing on an original graph in a material number system in the LDI exposure system and then sends the original graph to DMD equipment in the LDI exposure system, and the method comprises the following steps:
step 1: the CPU of the industrial personal computer performs corresponding graph transformation on the original graph according to the received original graph and corresponding graph transformation parameters;
step 2: a CPU of the industrial personal computer cuts an original graph into graph blocks related to the DMDs according to the position relation among the DMDs, the strip width and the height of a Block in the LDI exposure system;
and step 3: debugging the well divided graphic blocks to a graphic acceleration card by a CPU of the industrial personal computer, instantiating a plurality of modules in the FPGA to perform vector transformation or bitmap transformation on the plurality of graphic blocks synchronously in parallel;
and 4, step 4: after the graphics accelerator card finishes the graphics block transmission conversion processing, the data obtained after the graphics accelerator card processing is sent to the corresponding DMD communication board card through the dispatching of a CPU;
and 5: the communication board card receives data scheduled by the CPU, packages the data into a self-defined data format and sends the data to a communication interface of the drive board card;
step 6: the driving board receives data of a custom data format sent by the driving board through the communication interface, the data is analyzed from the custom data format and is cached in a DDR (double data rate) in the driving board, after a platform synchronizing signal sent by the platform controller is received, the data is read from the DDR, and the data is put on the DMD in a data format required by the DMD to be matched with the platform synchronizing signal to turn over an image to start scanning.
Optionally, the graph transformation parameters in step 1 include a rotation parameter, a translation parameter, and a harmomegathus parameter.
Optionally, the communication interfaces of the communication board card and the driving board card include an RJ45 interface or an optical module interface.
Optionally, the communication interfaces of the communication board card and the driving board card adopt RJ45 interfaces.
The invention has the beneficial effects that:
the method comprises the following steps that by means of a scheme of an industrial PC + a self-made graphic acceleration card, the self-made graphic acceleration card carries out vector transformation or bitmap transformation according to Block graphics; because the graph is processed according to the Block Block, a plurality of modules can be instantiated in the FPGA for parallel synchronous processing, serial execution is not needed like CPU processing, the processing rate can be improved, the processing time delay can be shortened, and the problems that the former data processing capacity is insufficient, a plurality of PCs are needed, and the data processing time delay is long are solved; through the scheme of an industry PC + self-control communication card, promote transmission rate, a pcie data processing board can carry out 10 Gbit/s's data transmission for N receiving terminals to under the condition of not increasing the pcie slot, can support more receiving terminals data transmission simultaneously. Because a plurality of communication board cards are arranged in the data processing system provided by the application, a network cable mode can be adopted instead of optical fiber transmission, so that the requirement on equipment wiring is weakened, for example, when the data processing system is applied to an exposure device and needs a continuous uninterrupted motion process, the network cable mode can be adopted, and the problems that in the prior art, optical fiber transmission is required to be adopted for achieving a high transmission rate, and the optical fiber is bent to generate packet loss, packet error and shortened service life of the optical fiber due to the uninterrupted motion are solved. The data processing system provided by the application can select a proper transmission medium according to actual conditions, and is flexible and various.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a block diagram of a data processing system provided in one embodiment of the present invention.
FIG. 2 is a block diagram of an image accelerator card in a data processing system provided in one embodiment of the invention.
Fig. 3 is a block diagram of a communication board in the data processing system according to an embodiment of the present invention.
Fig. 4 is a block diagram of a driver board in the data processing system according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a Block graph cut from a graph in the data processing method provided in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
the present embodiment provides a data processing system, referring to fig. 1, the system includes: the system comprises an industrial personal computer, a graphic acceleration card, a communication board card and a driving board card; the graphic accelerator card, the communication board card and the driving board card are all board cards based on an FPGA chip.
As shown in fig. 1, a CPU of the industrial personal computer is used for task scheduling at a control level and a user interface level; the graphic acceleration card is inserted into a main board pci slot of the industrial personal computer in a pci interface mode, and the main function of the graphic acceleration card is to assist the CPU to perform hardware acceleration processing on graphic data so as to improve data processing capacity and processing time delay. The communication board card is inserted into a main board pci slot of the industrial personal computer in a pci interface mode, the main function is data format conversion, the pci data format is converted into a communication data packet format to be sent to the driving board card, and meanwhile, some simple data processing is carried out. According to the design of the device, a plurality of communication boards can be inserted into the PC1 mainboard to realize data transmission of N × M channels. The driving board card is mainly used for receiving data transmitted by the PC layer, converting the data into data grids required by the DMD and sending the data grids to the DMD to display a graph.
The material number system in fig. 1 can be realized by a common PC; for the convenience of subsequent description, the industrial personal computer is called PC1, and the material number system is called PC 2; in practical application, the communication board interface on the PC1 and the communication interface on the drive board card may be an optical fiber module or an RJ45 interface at 10Gbit/s, and the transmission medium may be an optical fiber or a cat6a network cable, and the specific manner of use may be determined according to practical situations, and generally, the network cable manner is more suitable for an LDI machine than the optical fiber manner, and the optical fiber manner is only a reserved interface.
As shown in fig. 2, the graphic accelerator card has a pci interface and a memory card, and its main chip is FPGA, which may be selected from mainstream FPGAs of xilinx corporation and altera corporation, such as xilinx corporation: the V7/A7/K7/KU/VU series and the like can be adopted, and the selection of the chip model is mainly determined by considering the data processing performance; the pcie interface can adopt the standard of pcie3.0 x8 or above. The memory card DDR3/DDR4 is used for storing data.
As shown in fig. 3, the communication board has a pci interface and a memory card, and the main chip FPGA may be a main stream FPGA of xilinx corporation and altera corporation, such as xilinx corporation: V7/A7/K7/KU/VU series and the like, wherein the main chip is selected mainly considering the conditions of meeting the functions, such as selecting the optimal cost and volume; the pcie interface generally adopts the standard of pcie3.0 x8 or above. The mass storage (granules and memory banks) of DDR3/DDR4 is used for caching data. N-2 or 4 is a common design and 4 is an optimal design. The communication board card receives the graphic data processed by the PC layer through the pcie interface, selects a sending channel, packages the data according to the data format required by the interface, and sends the data to the corresponding data channel. And simple data processing can be performed at normal time.
As shown in fig. 4, the driving board receives the graphic data of the PC layer through an optical module interface or RJ45(10Gbit/s) interface, and sends the data to the DMD according to a certain format, and drives the DMD to display the relevant graphic in cooperation with the motion of the workbench and the optical system, thereby achieving the exposure function. The main chip FPGA of the board card can be selected from mainstream FPGAs of xilinx company, such as xilinx company: the series of V5/V6/V7/A7/K7/KU/VU and the like can be used, and the main chip is selected mainly under the condition of meeting the function, such as selecting the optimal cost and volume. The selection of the optical fiber or the network cable can be selected according to actual conditions. The mass storage (granules and memory banks) of DDR3/DDR4 is used for storing intermediate data.
Example two:
the embodiment provides a data processing method, which comprises the following steps:
step 1: the CPU of the PC1 receives the original graphics and graphics transformation parameters from the PC2, and performs corresponding graphics transformation on the original graphics according to the received original graphics and graphics transformation parameters (rotation, translation, harmomegathus, etc.).
Step 2: the CPU of the PC1 cuts the original pattern into pattern blocks related to the DMDs, that is, a pattern is divided into individual Block patterns, and the Block patterns are combined to form a complete pattern, based on the positional relationship (L1, L2, …, Ln) between the DMDs, the stripe width (the stripe width is the width of the Block), and the height of the Block. As shown in fig. 5;
and step 3: and debugging the segmented Block graphics to a graphics accelerator card by the CPU, and carrying out vector transformation or bitmap transformation on the graphics accelerator card according to the Block graphics. Because the graph is processed according to the Block Block, a plurality of modules can be instantiated in the FPGA to be processed synchronously in parallel, serial execution is not needed like CPU processing, and the processing rate can be improved and the processing time delay can be shortened.
And 4, step 4: and after the graphic accelerator card finishes processing the data, the data are sent to the corresponding DMD communication board card through the dispatching of the CPU.
And 5: the communication board card receives data scheduled by the CPU, packages the data into a self-defined data format, and sends the data to the RJ45 interface or the optical module interface.
Step 6: the driving board receives data sent by an upper layer through the RJ45 or an optical module interface, analyzes the data from a user-defined data format, caches the data in the DDR, reads the data from the DDR after receiving a platform synchronizing signal sent by the platform controller, and puts the data in a data format required by the DMD on the DMD to match the platform synchronizing signal to turn over an image to start scanning.
The method comprises the steps that an industrial PC + self-made graphic acceleration card is adopted, wherein the self-made graphic acceleration card carries out vector transformation or bitmap transformation according to Block graphics; because the graph is processed according to the Block Block, a plurality of modules can be instantiated in the FPGA for parallel synchronous processing, serial execution is not needed like CPU processing, the processing rate can be improved, the processing time delay can be shortened, and the problems that the former data processing capacity is insufficient, a plurality of PCs are needed, and the data processing time delay is long are solved; through the scheme of an industry PC + self-control communication integrated circuit board, promote transmission rate, a pcie data processing board can carry out 10 Gbit/s's data transmission for N receiving terminals to under the condition of not increasing the pcie slot, can support more receiving terminals data transmission simultaneously. Because a plurality of communication board cards are arranged in the data processing system provided by the application, a network cable mode can be adopted instead of optical fiber transmission, so that the requirement on equipment wiring is weakened, for example, when the data processing system is applied to an exposure device and needs a continuous uninterrupted motion process, the network cable mode can be adopted, and the problems that in the prior art, optical fiber transmission is required to be adopted for achieving a high transmission rate, and the optical fiber is bent to generate packet loss, packet error and shortened service life of the optical fiber due to the uninterrupted motion are solved. The data processing system provided by the application can select a proper transmission medium according to actual conditions, and is flexible and various.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. A data processing system, characterized in that the system comprises: the system comprises an industrial personal computer, a graphic acceleration card, a communication board card and a driving board card; the graphic accelerator card and the communication board card are inserted into a main board pci slot of the industrial personal computer in a pci interface mode; the communication board card is connected with the drive board card; the driving board card is connected with the digital micromirror DMD; the graphic accelerator card, the communication board card and the driving board card are all board cards based on an FPGA chip.
2. The system of claim 1, wherein the graphics accelerator card is configured to assist an industrial personal computer CPU in performing hardware acceleration processing on graphics data; the communication board card is used for converting the pcie data format into the format of a communication data packet and sending the communication data packet to the driver board card, and the driver board card converts the data transmitted by the communication board card into a data grid required by the DMD after receiving the data and sends the data grid to the DMD for displaying the graph.
3. The system of claim 2, wherein the communication interfaces of the communication board and the driving board are optical fiber modules or network interfaces, and the communication interfaces of the communication board and the driving board are paired for use.
4. The system of claim 3, wherein the pci interfaces of the graphic accelerator card and the communication board are in accordance with the standards of pci 3.0 x8 or above.
5. A data processing method applied to an LDI exposure system, wherein the method employs the data processing system of any one of claims 1 to 4 to digitally process an original pattern from a material number system in the LDI exposure system and send the processed pattern to a DMD device in the LDI exposure system, and the method comprises:
step 1: the CPU of the industrial personal computer performs corresponding graph transformation on the original graph according to the received original graph and corresponding graph transformation parameters;
step 2: a CPU of the industrial personal computer cuts an original graph into graph blocks related to the DMDs according to the position relation among the DMDs, the strip width and the height of a Block in the LDI exposure system;
and step 3: debugging the well divided graphic blocks to a graphic acceleration card by a CPU of the industrial personal computer, instantiating a plurality of modules in the FPGA to perform vector transformation or bitmap transformation on the plurality of graphic blocks synchronously in parallel;
and 4, step 4: after the graphics accelerator card finishes the graphics block transmission conversion processing, the data obtained after the graphics accelerator card processing is sent to the corresponding DMD communication board card through the dispatching of a CPU;
and 5: the communication board card receives data scheduled by the CPU, packages the data into a self-defined data format and sends the data to a communication interface of the drive board card;
step 6: the driving board receives data of a custom data format sent by the communication board through the communication interface, the data is analyzed from the custom data format and is cached in a DDR (double data rate) in the driving board, after a platform synchronizing signal sent by the platform controller is received, the data is read from the DDR, and the data is put on the DMD in a data format required by the DMD to be matched with the platform synchronizing signal to turn over an image to start scanning.
6. The method according to claim 5, wherein the graphics transformation parameters in step 1 include rotation parameters, translation parameters and harmomegathus parameters.
7. The method of claim 6, wherein the communication interfaces of the communication board and the driver board comprise RJ45 interfaces or optical module interfaces.
8. The method of claim 6, wherein the communication interface between the communication board and the driver board is an RJ45 interface.
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