CN112671625B - Network chip pipeline processing method and device - Google Patents
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- CN112671625B CN112671625B CN202011521072.2A CN202011521072A CN112671625B CN 112671625 B CN112671625 B CN 112671625B CN 202011521072 A CN202011521072 A CN 202011521072A CN 112671625 B CN112671625 B CN 112671625B
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Abstract
The invention discloses a network chip pipeline processing method and a network chip pipeline processing device, wherein the method comprises the following steps: a flexible pipeline bus is additionally arranged in a network chip pipeline; each functional module in the network chip stores the generated processing result in the flexible flow bus through the control of a configured coding process; and each functional module controls the extraction of a processing result from the flexible pipeline bus through a configured decoding process. The invention realizes the flexibility and the programmability of the network exchange chip pipeline, meets the requirements of unexpected network characteristics and prolongs the service characteristics of the chip.
Description
Technical Field
The invention belongs to a processing technology of intermediate processing in a network chip pipeline, and particularly relates to a network chip pipeline processing method and device.
Background
When the network switching chip processes and forwards the message, the message analysis, the network service list search, the forwarding table item search, the access control list search and other advanced characteristics are mainly included, and the modules cooperate with each other to complete the message forwarding and the strategy processing. Through the cooperative cooperation of the modules, the message generates an intermediate result processed by the modules in the pipeline process of the network chip, and the intermediate result is stored in a packetInfo BUS (message information flow BUS) for the subsequent modules to continue using. When the advanced characteristic module carries out policy processing on message forwarding, the result needs to be processed by the previous module, and therefore, what processing result needs to be stored in the packetInfo BUS by the previous module is particularly important.
Because the number of the results processed by the modules is huge, all the processing results cannot be stored in the PacketInfo BUS, and only results which are commonly used or known to be used are stored in the PacketInfo BUS. Therefore, the PacketInfo BUS of the conventional network switching chip is in a fixed format, the result can be stored in the PacketInfo only through a predefined PacketInfo field, and the result processed by the module can be stored in the PacketInfo only through chip hard logic coding. For example, for an ACL (Access Control List) module, when matching a message characteristic attribute, it is necessary to distinguish whether a host routing table entry or a network segment routing table entry is matched, and a search result needs to identify whether the host routing or the network segment routing, and store the result information in PacketInfo, so that the ACL can finally perform correct policy processing according to whether the host routing or the network segment routing is matched. If the identification field is not designed in the packetInfo at this time, the user requirement cannot be realized, and the flexibility of the chip use is greatly reduced.
Therefore, it is necessary to provide a flexible network chip pipeline processing scheme to overcome the defects that the prior art satisfies the intermediate result of the chip function module using the preorder processing through the logic hard code, and cannot satisfy the customer-defined characteristic requirement and the chip is compatible with the newly added network protocol characteristic.
Disclosure of Invention
In view of the above, the present invention provides a method and an apparatus for pipeline processing of a network chip.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a network chip pipeline processing method, the method comprising:
s100, adding a flexible pipeline bus in a network chip pipeline;
s200, each functional module in the network chip stores the generated processing result in the flexible pipeline bus through the control of a configured coding process;
s300, each functional module controls to take out the processing result from the flexible pipeline bus through a configured decoding process.
In one embodiment, the flexible pipeline bus is a set of data values, the data values including data values of multiple lengths.
In one embodiment, the flexible pipeline runs through a network chip pipeline, and each functional module is accessible and can be read and written.
In one embodiment, the S200 includes:
s201, reading an encoding process table entry through a data packet type, and acquiring encoding process content;
s202, traversing the whole processing result data through a preset step length, acquiring a preset length data value each time, and adding 1 to a corresponding index value each time the processing result data value is acquired;
s203, selecting the corresponding processing result to be stored in the flexible pipeline bus and the position of storing the processing result in the flexible pipeline bus through the control of the content of the coding process.
In an embodiment, the encoding process content includes an enable storage field, a location field, and a mask field, in S203, whether to store the acquired processing result data in the flexible pipeline bus is controlled by the enable storage field, the location field controls to store the processing result data in the location of the flexible pipeline bus, and the mask field controls to select to store part or all of the fields in the processing result data in the flexible pipeline bus.
In one embodiment, the S300 includes:
s301, reading a decoding process table entry according to the data packet type, and acquiring the content of the decoding process;
s302, selecting a processing result with a corresponding length from the flexible pipeline bus through the content control of the decoding process.
In an embodiment, the decoding process content includes an offset field and a length field, and in S302, the offset field controls a start position of data in the flexible pipeline bus to be acquired, and the length field controls a length of the acquired processing result data.
The technical scheme provided by one embodiment of the invention is as follows:
a network chip pipeline processing apparatus, the apparatus comprising:
the bus adding module is used for adding a flexible pipeline bus in a network chip pipeline;
the coding process module is used for storing the generated processing result in the flexible flow bus by each functional module in the network chip through the control of the configured coding process;
and the decoding process module is used for controlling each functional module to take out the processing result from the flexible pipeline bus through the configured decoding process.
In one embodiment, the encoding process module further comprises:
the coding process reading unit is used for reading the coding process table entry through the data packet type and acquiring the coding process content;
the data traversing unit is used for traversing the whole processing result data through a preset step length, acquiring a preset length data value each time, and adding 1 to a corresponding index value each time the processing result data value is acquired;
and the data storage unit is used for controlling and selecting the corresponding processing result to be stored in the flexible pipeline bus and the position of the processing result in the flexible pipeline bus through the content of the coding process.
In one embodiment, the decoding process module comprises:
the decoding process reading unit is used for reading the decoding process table entry through the data packet type and acquiring the decoding process content;
and the data reading unit is used for controlling the processing result with the corresponding length selected from the flexible pipeline bus through the content of the decoding process.
The invention has the following beneficial effects:
the invention achieves the flexibility and the programmability of the network exchange chip pipeline by adding a group of flexible pipeline buses and controlling the encoding and the decoding of the flexible pipeline bus data through the user-defined process, meets the requirements of unexpected network characteristics, prolongs the use characteristics of the chip, and solves the defects that the network chip hard logic encoding pipeline can not meet the user-defined requirements and can not compatibly use new network characteristics.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow diagram of the process of the present invention;
FIG. 2 is a flowchart illustrating step S200 according to the present invention;
FIG. 3 is a schematic block diagram of step S200 of the present invention;
FIG. 4 is a flowchart illustrating step S300 according to the present invention;
FIG. 5 is a schematic block diagram of step S300 of the present invention;
FIG. 6 is a block diagram of the apparatus of the present invention;
FIG. 7 is a block diagram illustrating the structure of an encoding process module according to the present invention;
FIG. 8 is a block diagram illustrating a decoding process module according to the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the network chip pipeline processing method disclosed in the present invention includes the following steps:
and S100, adding a flexible pipeline bus in a network chip pipeline.
Specifically, in the present invention, in addition to the Fixed pipelined BUS (Fixed packet info BUS, message information Fixed pipelined BUS) existing in the network chip pipeline, a set of Flexible pipelined BUS (Flexible packet info BUS, message information Flexible pipelined BUS) is added, which is simply referred to as X packet info for convenience of description.
Specifically, the X packetnfo is a set of flexible pipelined BUS (BUS) without any field parameter meaning, i.e., is a set of Data (Data) values, where 1bit is 1 Raw, 4bits is 1 nibble (nibble), 2 nibbles is 1 Byte, 2 bytes is 1 Word, 2 words is 1 Dword, and 2 dwords are 1 Qword.
The specific encoding process is as follows:
wherein, gRaw, gNibbel, GByte, gWord, gDWord and gQWord share a set of BUS (namely X PacketInfo BUS), and data with the length of 4bits, 8bits, 16bits and the like can be taken out only by different coding means. The X PacketInfo is a flexible BUS running through a network chip pipeline, and any functional module in the network chip can access the X PacketInfo and can read and write.
Referring to fig. 2 and fig. 3, in S200, each functional module in the network chip stores the generated processing result in the flexible pipeline bus by means of configured encoding process control.
Specifically, the encoding process (Encode Profile, encoding control process) may control which processing result is selected and stored in which position of the X packetnfo. The S200 specifically includes the following steps:
s201, reading an encoding process (Profile) entry through the data packet type (PacketType), and acquiring the encoding process content.
In this embodiment, the content of the encoding process specifically includes an enable storage field, a location field, and a mask field. In this embodiment, the enable storage field is defined as profile, gnibble [ index ]. enable, the location field is defined as profile, gnibble [ index ]. nibbleId, and the Mask field is defined as profile, gnibble [ index ]. Mask. The enabling storage field is used for controlling whether the read processing data is stored in the X PacketInfo, the position field is used for controlling the position of the processing result data stored in the X PacketInfo, and the mask field is used for controlling and selecting to store part or all of fields in the processing result data in the flexible pipeline bus.
And S202, traversing the whole processing result data through a preset step length, acquiring a preset length data value each time, and adding 1 to the corresponding index value each time the processing result data value is acquired.
In this embodiment, the preset step length is 4bits, the entire intermediate processing result Data (parseresult Data, message analysis Data) generated by each functional module is traversed by the 4bits step length, the da-ta value of 4bits is obtained each time, and the corresponding index value (index) is increased by 1 each time the processing result Data value is obtained.
S203, selecting corresponding processing results to be stored in the flexible pipeline bus and the position of the flexible pipeline bus through the control of the content of the coding process.
Specifically, whether the ParserResult Data of the 4bits needs to be stored in the X packetInfo is controlled by profile.
As shown in fig. 4 and 5, in S300, each functional module controls to fetch a processing result from the flexible pipeline bus through a configured decoding process.
Specifically, the S300 specifically includes the following steps:
s301, reading the decoding process table entry according to the data packet type, and acquiring the decoding process content.
Specifically, in this embodiment, the decoding process content includes an offset field and a Length field, the offset field is defined as Profile [ index ]. offset, and the Length field is defined as Profile [ index ]. Length.
S302, selecting a processing result with a corresponding length from the flexible pipeline bus through decoding process content control.
Specifically, the start position of data in the X packetnfo is acquired by Profile [ index ]. offset control, and the Length of the acquired processing result data is controlled by Profile [ index ]. Length. Currently, 4bits, 8bits, 16bits, 32bits and 64bits are supported. Index is the number of times that support can extract X Packet Data. The extracted X PacketInfo Data can be used by the functional module, so that the result parameters of other modules are flexibly controlled and used by the Profile, the requirement of a user-defined chip is met, and the programmable effect of a chip assembly line is achieved.
As shown in fig. 6, corresponding to the above method, the network chip pipeline processing apparatus disclosed in the present invention includes:
and the bus adding module is used for adding a flexible pipeline bus in the network chip pipeline.
And the coding process module is used for controlling each functional module in the network chip to store the generated processing result in the flexible flow bus through the configured coding process.
As shown in fig. 7, the encoding progress module further includes:
the coding process reading unit is used for reading the coding process table entry through the data packet type and acquiring the coding process content;
the data traversing unit is used for traversing the whole processing result data through a preset step length, acquiring a preset length data value each time, and adding 1 to a corresponding index value each time the processing result data value is acquired;
and the data storage unit is used for controlling and selecting the corresponding processing result to be stored in the flexible pipeline bus and the position of the processing result in the flexible pipeline bus through the content of the coding process.
And the decoding process module is used for controlling each functional module to take out the processing result from the flexible pipeline bus through a configured decoding process.
As shown in fig. 8, wherein the decoding process module includes:
the decoding process reading unit is used for reading the decoding process table entry through the data packet type and acquiring the decoding process content;
and the data reading unit is used for controlling the processing result with the corresponding length selected from the flexible pipeline bus through the content of the decoding process.
The bus extension module, the encoding process module, and the decoding process module may refer to the descriptions in steps S100 to S300, which are not described herein again.
According to the technical scheme, the invention has the following advantages: when the hard logic coding assembly line of the network chip can be solved, the defects that the user-defined requirement of a client can not be met and the new network characteristics can not be used compatibly are overcome, the characteristics of the user-defined assembly line are achieved through the flexible assembly line BUS, the requirement of the unexpected network characteristics is met, and the service characteristics of the chip are prolonged.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions.
For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the modules may be implemented in the same one or more software and/or hardware implementations in implementing one or more embodiments of the present description.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
One or more embodiments of the specification may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. One or more embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A network chip pipeline processing method is characterized by comprising the following steps:
s100, adding a flexible pipeline bus in a network chip pipeline;
s200, each functional module in the network chip stores a generated processing result in the flexible pipeline bus through configured encoding process control, where the S200 includes:
s201, reading an encoding process table entry through a data packet type, and acquiring encoding process content;
s202, traversing the whole processing result data through a preset step length, acquiring a preset length data value each time, and adding 1 to a corresponding index value each time the processing result data value is acquired;
s203, controlling and selecting corresponding processing results to be stored in the flexible pipeline bus and the position of the processing results in the flexible pipeline bus through the content of the coding process; the coding process content includes an enable storage field, a position field and a mask field, in S203, whether the obtained processing result data is stored in the flexible pipeline bus is controlled by the enable storage field, the processing result data is stored in the position in the flexible pipeline bus is controlled by the position field, and a part or all of the fields in the processing result data are stored in the flexible pipeline bus is controlled and selected by the mask field;
s300, each functional module controls to take out the processing result from the flexible pipeline bus through a configured decoding process.
2. The network chip pipeline processing method of claim 1, wherein the agile pipeline bus is a set of data values, and wherein the data values comprise data values of a plurality of lengths.
3. The network chip pipeline processing method of claim 1, wherein the flexible pipeline runs through a network chip pipeline, and each functional module is accessible and can be read and written.
4. The network chip pipeline processing method according to claim 1, wherein the S300 comprises:
s301, reading a decoding process table entry according to the data packet type, and acquiring the content of the decoding process;
s302, selecting a processing result with a corresponding length from the flexible pipeline bus through the content control of the decoding process.
5. The network chip pipeline processing method of claim 4, wherein the decoding process content includes an offset field and a length field, and in the S302, the offset field controls a start position of data in the flexible pipeline bus, and the length field controls a length of the obtained processing result data.
6. A network chip pipeline processing apparatus, the apparatus comprising:
the bus adding module is used for adding a flexible pipeline bus in a network chip pipeline;
a coding process module, configured to enable each functional module in the network chip to store a generated processing result in the flexible pipeline bus through configured coding process control, where the coding process module further includes:
the coding process reading unit is used for reading the coding process table entry through the data packet type and acquiring the coding process content;
the data traversing unit is used for traversing the whole processing result data through a preset step length, acquiring a preset length data value each time, and adding 1 to a corresponding index value each time the processing result data value is acquired;
the data storage unit is used for controlling and selecting corresponding processing results to be stored in the flexible flow bus and the position of the flexible flow bus through the coding process content, the coding process content comprises an enabling storage field, a position field and a mask field, whether the obtained processing result data is stored in the flexible flow bus or not is controlled through the enabling storage field in the data storage unit, the position of the processing result data in the flexible flow bus is controlled through the position field, and part or all of the fields in the processing result data are stored in the flexible flow bus through the mask field;
and the decoding process module is used for controlling each functional module to take out the processing result from the flexible pipeline bus through a configured decoding process.
7. The network chip pipeline processing device of claim 6, wherein the decoding process module comprises:
the decoding process reading unit is used for reading the decoding process table entry through the data packet type and acquiring the decoding process content;
and the data reading unit is used for controlling the processing result with the corresponding length selected from the flexible pipeline bus through the content of the decoding process.
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| US6665755B2 (en) * | 2000-12-22 | 2003-12-16 | Nortel Networks Limited | External memory engine selectable pipeline architecture |
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| US6219736B1 (en) * | 1997-04-24 | 2001-04-17 | Edwin E. Klingman | Universal serial bus (USB) RAM architecture for use with microcomputers via an interface optimized for integrated services device network (ISDN) |
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