CN111555901A - Chip configuration network system for flexibly supporting hybrid bus protocol - Google Patents
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Abstract
The invention belongs to the technical field of chip configuration networks, and particularly relates to a chip configuration network system flexibly supporting a hybrid bus protocol, which comprises a configuration network master-slave interface, a protocol analysis and address mapping module and a core interconnection network; protocol analysis and address mapping modules are respectively added at a master interface and a slave interface of the configuration network; the protocol analysis and address mapping module is used for realizing the conversion between the bus read-write request/read-write response address and the network ID, converting the read-write request or the read-write response of different bus protocols into a data packet form according to a uniform format and injecting the data packet into the core interconnection network, or converting the data packet received from the core interconnection network into a corresponding bus signal time sequence according to different bus protocols. The invention can flexibly support network interconnection and protocol bridging of the same or different bus protocols, greatly reduces the design complexity and technical threshold of a chip configuration network, and has good expandability and reusability.
Description
Technical Field
The invention belongs to the technical field of chip configuration networks, and particularly relates to a chip configuration network system flexibly supporting a hybrid bus protocol.
Background
The chip configuration network is mainly used for supporting configuration and management of each main configuration interface (such as I2C, JTAG, PCIE and the like) in the chip on related registers or RAM spaces in the chip, and providing basic guarantee for realization of functions and performance of the chip. With the increasing of the chip design scale, the design scale and the design complexity of the chip internal configuration network are also increased. On one hand, the scale of Master (Master) Slave (Slave) interfaces supported by a configuration network is larger and larger, and the number of the Master interfaces and the Slave interfaces of the internal configuration network of a large-scale system chip is over 100; on the other hand, in order to shorten the time to market, a variety of commercial IPs (intellectual property cores) are usually integrated inside the chip, and these commercial IPs may be located at the Master (Master) position of the configuration network and at the Slave (Slave) position of the configuration network in the chip, and even have both the Slave interface and the Master interface connected to the configuration network. In addition, different commercial IPs may adopt different bus protocols (such as AXI, AHB, APB, etc.), so that bus configuration requirements of multiple different protocol types may exist simultaneously inside a chip, thereby resulting in a drastic increase in design complexity.
For example, a configuration network of an SRIO switch chip is designed as shown in fig. 1. According to the overall design requirements, the master-slave interface scale of the internal configuration network of the SRIO switching chip reaches nearly hundreds, and various different bus protocol types such as an AXI bus, an AHB bus, an SRIO maintenance packet (bus read-write request), a Localbus and the like exist at the same time. In order to meet the configuration requirements of a chip, a conventional design idea is to integrate a plurality of bus interconnection Matrix matrixes (used in a multi-master and multi-slave communication scenario) of corresponding protocols and Bridge modules (Bridge) of different protocols inside the chip, so as to implement data forwarding between master and slave interfaces of the same bus protocol and protocol conversion between different bus protocols. As shown in fig. 1, AXI _ Matrix is used To implement communication between multiple AXI protocol master-slave interfaces, AHB _ Matrix is used To implement communication between multiple AHB protocol master-slave interfaces, AXI _ To _ AHB _ Bridge is used To implement conversion between the AXI protocol and the AHB protocol, AHB _ To _ Localbus _ Bridge is used To implement conversion between the AHB protocol and a Localbus bus, and SRIO MPM (Maintenance Processing Module) is used To implement conversion between an SRIO Maintenance packet configuration request and an AXI bus protocol. The integration of a large number of bus interconnect Matrix and Bridge modules in a configuration network will present significant challenges to both design and validation in view of the complexity and compatibility of the bus protocol processing.
Under the application communication requirements of numerous master-slave interfaces and mixed multiple bus protocols, the design method of the bus interconnection Matrix and the bus Bridge widely adopted in the existing configuration network design generally has the following defects:
(1) the design difficulty is big, the technical threshold is high. The design of the bus interconnection Matrix and the bus Bridge usually performs signal level processing on read-write address signals, data signals and read-write response signals, and a designer needs to be familiar with not only the dependency relationship and processing flow among the signals of the bus protocol, but also master the design method of the corresponding protocol interconnection Matrix and the conversion implementation among different bus protocols, so that the design difficulty is high, and a high technical threshold is provided.
(2) Compatibility and consistency of the different bus protocol conversions is difficult to guarantee. The design of the bus interconnection Matrix and the bus Bridge needs to strictly follow the corresponding bus protocol, the compatibility and consistency of conversion of different bus protocols are difficult to ensure, the deadlock phenomenon of a network is easily caused by improper design, and even the function and the performance of the whole chip are influenced.
(3) Scalability and reusability are poor. Once the design of the bus interconnection Matrix and the bus Bridge is determined, a small amount of change of the network scale or change of the bus interface protocol introduces a large design modification and verification workload, and is difficult to flexibly expand to different communication scales and application communication scenes, so that the expandability and the reusability are poor.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a chip configuration network system flexibly supporting a hybrid bus protocol, which can flexibly support network interconnection and protocol bridging of various bus protocols such as commonly used AMBA buses (such as AXI/AHB/APB, and the like), processor secondary buses (such as Localbus, and the like), SRIO maintenance packet configuration buses, user-defined buses, and the like, can greatly reduce the design complexity and technical threshold of a chip configuration network, and has good expandability and reusability.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention relates to a chip configuration network system for flexibly supporting a hybrid bus protocol, which comprises: configuring a network master-slave interface, a protocol analysis and address mapping module and a core interconnection network; protocol analysis and address mapping modules are respectively added at a master interface and a slave interface of the configuration network, and the protocol analysis and address mapping modules are connected with a core interconnection network; the protocol analysis and address mapping module is used for realizing the conversion between the bus read-write request/read-write response address and the network ID, converting the read-write request or the read-write response of different bus protocols into a data packet form according to a uniform format and injecting the data packet into the core interconnection network, or converting the data packet received from the core interconnection network into a corresponding bus signal time sequence according to different bus protocols, wherein the data packet has protocol independence when being transmitted in the core interconnection network.
Further, the protocol analysis and address mapping module comprises a synchronous processing sub-module, a protocol packet processing sub-module, an address mapping sub-module, a protocol unpacking processing sub-module, an input queue sub-module and an output queue sub-module;
the synchronous processing submodule is used for finishing clock domain crossing processing of signals between a bus clock and a network clock;
the protocol packet processing submodule is used for encapsulating the bus read-write request/read-write response into a data packet form according to a bus protocol;
the address mapping submodule is used for mapping between a bus read-write request/read-write response address and a network DEST _ ID, and the DEST _ ID is packaged into a data packet and used for selecting a route in a core interconnection network;
the protocol unpacking processing submodule is used for receiving data packets transmitted in a network and converting the data packets into corresponding bus signal time sequences according to different bus protocols;
the input queue submodule is used for receiving a data packet transmitted by a network, generating a corresponding back pressure signal and transmitting the back pressure signal to the network, and uploading the data packet to the protocol unpacking processing submodule to carry out subsequent unpacking processing under the control of the bus read-write request/read-write response signal;
and the output queue submodule is used for receiving a data packet generated after the bus read-write request/read-write response passes through the protocol packet processing submodule, generating a corresponding back pressure signal to the bus interface, and injecting the data packet in the output queue submodule into the network when the network is idle.
Further, the read-write requests or read-write responses of different bus protocols have a uniform data packet format in the network, and the data packet format is as follows:
| Tail | Body | … | Body | Header |
the data packet consists of three data structures, namely a Header Flit (Header Flit), a Body Flit (Body Flit) and a Tail Flit (Tail Flit), wherein the Header Flit carries routing information and related bus control information, the Body Flit and the Tail Flit carry read-write data information and a data packet end indication, and the data widths of the three flits are all matched with the data bit width of a network interface.
Further, the format of the header flit is as follows:
| Tag | Resp | Data | Des_ID | Src_ID | Wr_addr | Pkt_type | Pro_type | Flit_type |
the format of the body or tail flits is as follows:
| Data | Data | Data | Data | Flit_type |
flit _ type represents the type of Flit, Pro _ type represents the type of protocol, Pkt _ type represents the type of Data packet, Wr _ addr represents the bus read-write address, Src _ ID represents the source ID address of the message, Des _ ID represents the destination ID address of the message, Data represents the bus read-write Data, Resp represents the read-write response, and Tag represents the storage of other important control information that needs attention in the bus protocol.
Further, a Crossbar Switch mode or an NOC on-chip interconnection mode is adopted for a core interconnection network in the chip configuration network, when the number of master nodes and slave nodes of the chip configuration network is small, a Crossbar Switch structure is adopted, and when the number of master nodes and slave nodes of the chip configuration network is large, an NOC on-chip interconnection structure is adopted.
Compared with the existing bus interconnection Matrix and bus Bridge design method, the method has the following advantages:
1. the complexity of the configuration network design is reduced: the chip configuration network system flexibly supporting the hybrid bus protocol solves the problem of design complexity of bus interconnection Matrix and bus Bridge, and can flexibly support network interconnection between the same protocols and bridging processing between different protocols by performing encapsulation and unpacking processing on read-write requests or read-write responses of different bus protocols at a protocol resolution and address mapping module (PRAM) interface, avoid various complex signal dependency guarantees and protocol processing flows in network protocol processing, and easily ensure the compatibility and consistency of protocol processing.
2. Avoiding the occurrence of network deadlock, livelock and starvation phenomena: different bus protocols are transmitted in the network in a uniform data packet format, and the phenomena of network deadlock, livelock and starvation can be effectively avoided by adopting a mature deadlock-free routing algorithm or a fair arbitration strategy in the network.
3. The method has better reusability and expansibility: by increasing the communication scale of the core interconnection network and the protocol applicability of the PRAM interface, the method can be flexibly suitable for communication scenes with different network scales and different protocol types. In addition, the PRAM module which is fully verified can be directly applied to different application scenes, and has better reusability.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a configuration network of an SRIO switch chip in the prior art;
FIG. 2 is a schematic structural diagram of a chip configuration network system flexibly supporting a hybrid bus protocol according to an embodiment of the present invention;
FIG. 3 is a block diagram of a protocol resolution and address mapping module according to an embodiment of the present invention;
fig. 4 is a flowchart of the protocol packet processing submodule and the protocol unpacking submodule according to the embodiment of the present invention, where (a) is a flowchart of the protocol packet processing submodule and (b) is a flowchart of the protocol unpacking processing submodule;
fig. 5 is a schematic diagram of a 2D-MESH NOC-based chip configuration network structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
Example one
Different from the conventional bus interconnection Matrix and bus Bridge design method, in the network transmission layer, complex signal level processing needs to be performed for read-write address signals, data signals, read-write response signals and the like of different bus protocols, respectively, as shown in fig. 2, the chip configuration network system flexibly supporting the hybrid bus protocol provided by this embodiment includes a configuration network master-slave interface, a protocol parsing and address mapping module, and a core interconnection network; protocol Resolution and Address Mapping (PRAM) modules are respectively added at a master interface and a slave interface of the configuration network, and the Protocol Resolution and Address Mapping modules are connected with a core interconnection network; the protocol analysis and address mapping module is used for realizing the conversion between a bus read-write request/read-write response address and a network ID, converting the read-write request or the read-write response of different bus protocols into a data packet form according to a uniform format and injecting the data packet into a core interconnection network, or converting the data packet received from the core interconnection network into a corresponding bus signal time sequence according to different bus protocols, wherein the data packet has protocol independence during transmission in the network, and further simplifying the function of the core interconnection network from a bus signal-based protocol processing and forwarding process to a data packet-based forwarding processing process, avoiding various complex signal dependency guarantees and processing flows in network protocol processing, and improving the compatibility and consistency of the protocol processing.
As shown in fig. 3, the protocol parsing and address mapping module includes a synchronization processing sub-module, a protocol packet processing sub-module, an address mapping sub-module, a protocol unpacking processing sub-module, an input queue sub-module, and an output queue sub-module.
And the synchronous processing submodule is used for finishing clock domain crossing processing of the signals between the bus clock and the network clock.
And the protocol packet processing submodule is used for encapsulating the bus read-write request/read-write response into a data packet form according to the bus protocol. According to the bus time sequence of different bus protocols, information such as bus protocol type, read-write request type, address, control, data and response is respectively acquired, and different bus operations such as bus read request, write request, read response, write response and the like can be packaged into the forms of a read request data packet, a write request data packet, a read response data packet and a write response data packet by combining with the network DEST _ ID output by the address mapping submodule, and then the read request, the write request, the read response, the write response and the like are injected into the network, as shown in fig. 4 (a). The data packets of different bus protocols adopt a uniform data packet format in the network so as to be compatible with the read-write request/read-write response of different bus protocols and the data bit width of a network interface.
And the address mapping submodule is used for mapping between the bus read-write request/read-write response address and the network DEST _ ID, and corresponds to an address resolution module in the conventional bus interconnection Matrix module. When various data packets generated after bus operation of different bus protocol types passes through the protocol packet processing submodule are transmitted in the network, routing is carried out based on DEST _ ID.
And the protocol unpacking processing submodule is used for receiving the data packet transmitted in the network and converting the data packet into a bus signal time sequence of a corresponding interface. After receiving an effective data packet transmitted by a network, the protocol unpacking processing submodule first parses information such as a corresponding bus protocol type, a read-write request type, an address, control, data, response and the like according to a uniform data packet format, and completes generation of a corresponding bus signal time sequence according to a current bus protocol, such as a bus read request, a bus write response, a bus read response and the like, so as to maintain a dependency relationship and a handshake time sequence among bus signals, as shown in fig. 4 (b).
And the input queue submodule is used for receiving the data packet transmitted by the network, generating a corresponding back pressure signal and transmitting the back pressure signal to the network, and uploading the data packet to the protocol unpacking processing submodule to carry out subsequent unpacking processing under the control of the bus read-write request/read-write response signal.
And the output queue submodule is used for receiving a data packet generated after the bus read-write request/read-write response passes through the protocol packet processing submodule, generating a corresponding back pressure signal to the bus interface, and injecting the data packet in the output queue submodule into the network when the network is idle.
The read-write requests or read-write responses of different bus protocols have a uniform data packet format in the network, and the data packet format is as follows:
| Tail | Body | … | Body | Header |
in order to simplify the structural design of a core network and be compatible with read-write requests/read-write responses of different bus protocols, a data packet consists of three data structures, namely a Header Flit (Header Flit), a Body Flit (Body Flit) and a Tail Flit (Tail Flit), wherein the Header Flit carries routing information and related bus control information, the Body Flit and the Tail Flit carry read-write data information and a data packet end indication, and the data widths of the three flits are matched with the data bit width of a network interface.
The format and bit width of the header flit are as follows:
| Tag | Resp | Data | Des_ID | Src_ID | Wr_addr | Pkt_type | Pro_type | Flit_type |
| 130-82bit | 81-80bit | 79-48bit | 47-40bit | 39-32bit | 31-8bit | 7-6bit | 5-3bit | 2-0bit |
the format and bit width of the body flit or the tail flit are as follows:
| Data | Data | Data | Data | Flit_type |
| 130-99bit | 98-67bit | 66-35bit | 34-3bit | 2-0bit |
(1) the Flit _ type represents the type of flits, wherein 001 represents a head Flit, 010 represents a body Flit, 100 represents a tail Flit, and 101 is a single Flit message and represents both the head Flit and the tail Flit.
(2) Pro _ type represents the type of protocol, and a bit field width of 3 bits can support a maximum of 8 bus protocols.
(3) Pkt _ type indicates the type of packet, and for a chip configuration network, four packet types are generally included, where 00 indicates a write request, 01 indicates a read request, 10 indicates a write response, and 11 indicates a read response.
(4) Wr _ addr represents the bus read and write address.
(5) The Src _ ID represents the source ID address of the message, the configuration network assigns a network ID address to each bus interface, and the data packet is transmitted in the network to perform routing based on the ID.
(6) Des _ ID represents the destination ID address of the message, and is converted from the read-write address of the bus through address mapping.
(7) Data represents the bus read and write Data, representing write Data for write request packets and read Data for read response packets, while the bit field Data is not of interest for both read request and write response packets.
(8) Resp denotes read and write responses, and Resp signals have different meanings according to different bus protocols.
(9) Tag represents other important control information needing attention in the bus protocol, for example, for the AXI4 protocol, corresponding control signals such as read-write Cache, Prot, Lock, Burst Length and the like can be stored in a Tag bit domain.
Generally, for different bus protocols, if Burst read-write operation does not need to be supported, a single Flit message (Flit _ type 101) can completely represent a read-write request or a read-write response. When complex Burst bus operation needs to be supported, a situation that one microchip cannot represent a complete read/write request may occur, and at this time, a packet processing needs to be performed on the bus read/write request in a multi-microchip data packet mode. For example, for the AXI4 bus write operation supporting Burst Length of 15, since 16 data are continuously written to the corresponding continuous address space for one write operation, the data packet needs to be accompanied by 3 flits and 1 trailer flit message for transmitting 16 beats of write data in addition to the head flit.
The design of the core interconnection network in the chip configuration network can adopt the traditional Crossbar Switch mode and can also support the data communication among a plurality of master-slave bus interfaces based on the NOC on-chip interconnection mode. Generally, when the number of master nodes and slave nodes of the chip configuration network is small, a traditional Crossbar Switch structure can be adopted, but for an application scenario that the number of master nodes and slave nodes of the chip configuration network is large (greater than 100), the adoption of a NOC-based on-chip interconnection structure with stronger expansibility generally has better expandability and communication performance.
Fig. 5 shows a 2D-MESH NOC-based chip configuration network structure, where each bus master-slave interface is connected to a Router on chip (Router, R) through a protocol resolution and address mapping interface (PRAM), and the routers are connected to each other through data links. When the bus read-write request or the read-write response completes the packet processing in the PRAM, the data packet completes the routing process in the network according to the Dest _ ID and sequentially passes through each intermediate router until reaching the destination network node. And after the data packet reaches the destination network node, the data packet is unpacked in the corresponding PRAM module, and the data packet is restored into a corresponding bus time sequence according to an interface bus protocol. It can be seen that, aiming at different configuration network design requirements, the communication scale of the core network and the protocol applicability of the PRAM interface are modified, so that the method can be flexibly applied to network communication with different network scales and different protocol types, and has good expansibility and reusability. The 2D-MESH NOC structure is taken as an example to describe the packet and unpacking of the bus protocol and the transmission process of the data packet in the network, and other on-chip interconnection structures such as Butterfly, Fat-Tree, etc. may also be adopted in practical applications.
The invention respectively adds corresponding protocol analysis and address mapping modules at the master interface and the slave interface of the configuration network, and is used for converting the read-write request or the read-write response of the bus protocol into a data packet form according to a certain format and injecting the data packet into the network, or converting the data packet received from the network into a corresponding bus signal time sequence according to a corresponding bus interface protocol, thereby realizing protocol isolation, converting the signal-level processing of the configuration network into the data packet-level processing, and simplifying the protocol processing complexity in the network. The read-write requests or read-write responses of different bus protocols have a uniform data packet format in a network, can be converted into different bus signal time sequences after being unpacked by different PRAM modules, has a natural protocol bridging function, and can flexibly support interconnection and intercommunication of data among different protocols.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it is to be noted that: the above description is only a preferred embodiment of the present invention, and is only used to illustrate the technical solutions of the present invention, and not to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (5)
1. A chip configuration network system for flexibly supporting a hybrid bus protocol, comprising: configuring a network master-slave interface, a protocol analysis and address mapping module and a core interconnection network; protocol analysis and address mapping modules are respectively added at a master interface and a slave interface of the configuration network, and the protocol analysis and address mapping modules are connected with a core interconnection network; the protocol analysis and address mapping module is used for realizing the conversion between the bus read-write request/read-write response address and the network ID, converting the read-write request or the read-write response of different bus protocols into a data packet form according to a uniform format and injecting the data packet into the core interconnection network, or converting the data packet received from the core interconnection network into a corresponding bus signal time sequence according to different bus protocols, wherein the data packet has protocol independence when being transmitted in the core interconnection network.
2. The chip configuration network system flexibly supporting a hybrid bus protocol according to claim 1, wherein the protocol parsing and address mapping module comprises a synchronization processing sub-module, a protocol packet processing sub-module, an address mapping sub-module, a protocol unpacking processing sub-module, an input queue sub-module and an output queue sub-module;
the synchronous processing submodule is used for finishing clock domain crossing processing of signals between a bus clock and a network clock;
the protocol packet processing submodule is used for encapsulating the bus read-write request/read-write response into a data packet form according to a bus protocol;
the address mapping submodule is used for mapping between a bus read-write request/read-write response address and a network DEST _ ID, and the DEST _ ID is packaged into a data packet and used for selecting a route in a core interconnection network;
the protocol unpacking processing submodule is used for receiving data packets transmitted in a network and converting the data packets into corresponding bus signal time sequences according to different bus protocols;
the input queue submodule is used for receiving a data packet transmitted by a network, generating a corresponding back pressure signal and transmitting the back pressure signal to the network, and uploading the data packet to the protocol unpacking processing submodule to carry out subsequent unpacking processing under the control of the bus read-write request/read-write response signal;
and the output queue submodule is used for receiving a data packet generated after the bus read-write request/read-write response passes through the protocol packet processing submodule, generating a corresponding back pressure signal to the bus interface, and injecting the data packet in the output queue submodule into the network when the network is idle.
3. The chip configuration network system flexibly supporting hybrid bus protocols according to claim 1, wherein the read-write requests or read-write responses of different bus protocols have a uniform data packet format in the network, and the data packet format is as follows:
the data packet consists of three data structures, namely a Header Flit (Header Flit), a Body Flit (Body Flit) and a Tail Flit (Tail Flit), wherein the Header Flit carries routing information and related bus control information, the Body Flit and the Tail Flit carry read-write data information and a data packet end indication, and the data widths of the three flits are all matched with the data bit width of a network interface.
4. The chip configuration network system for flexibly supporting a hybrid bus protocol according to claim 3, wherein the format of the header flit is as follows:
the format of the body or tail flits is as follows:
flit _ type represents the type of Flit, Pro _ type represents the type of protocol, Pkt _ type represents the type of Data packet, Wr _ addr represents the bus read-write address, Src _ ID represents the source ID address of the message, Des _ ID represents the destination ID address of the message, Data represents the bus read-write Data, Resp represents the read-write response, and Tag represents the storage of other important control information that needs attention in the bus protocol.
5. The system of claim 1, wherein the core interconnect network in the chip configuration network is implemented in a Crossbar Switch or a NOC-based on-chip interconnect, and the Crossbar Switch is implemented when there are fewer master nodes and slave nodes in the chip configuration network, and the NOC-based on-chip interconnect is implemented when there are more master nodes and slave nodes in the chip configuration network.
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| CN115189977A (en) * | 2022-09-09 | 2022-10-14 | 太初(无锡)电子科技有限公司 | Broadcast transmission method, system and medium based on AXI protocol |
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| CN114785660B (en) * | 2022-03-15 | 2023-08-29 | 桂林电子科技大学 | NoC high-speed data acquisition topological structure and synchronization method thereof |
| CN114610667B (en) * | 2022-05-10 | 2022-08-12 | 沐曦集成电路(上海)有限公司 | Multiplex data bus device and chip |
| CN114610667A (en) * | 2022-05-10 | 2022-06-10 | 沐曦集成电路(上海)有限公司 | Multiplex data bus device and chip |
| CN115189977A (en) * | 2022-09-09 | 2022-10-14 | 太初(无锡)电子科技有限公司 | Broadcast transmission method, system and medium based on AXI protocol |
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| CN116800837A (en) * | 2022-12-16 | 2023-09-22 | 无锡芯光互连技术研究院有限公司 | Communication conversion method, device and medium for communication between master and slave devices |
| CN115827532A (en) * | 2022-12-26 | 2023-03-21 | 无锡众星微系统技术有限公司 | PCIe HBA IOC internal bus network interconnection method |
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