CN112671383A - Laser phase rapid locking device with continuously tunable frequency - Google Patents
Laser phase rapid locking device with continuously tunable frequency Download PDFInfo
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- CN112671383A CN112671383A CN202110133096.9A CN202110133096A CN112671383A CN 112671383 A CN112671383 A CN 112671383A CN 202110133096 A CN202110133096 A CN 202110133096A CN 112671383 A CN112671383 A CN 112671383A
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Abstract
The invention relates to a laser phase locking technology, in particular to a laser phase rapid locking device with continuously tunable frequency. The invention solves the problem that the existing laser phase locking technology can not continuously tune the frequency of the second beam of laser under the condition of not unlocking. A laser phase quick locking device with continuously tunable frequency comprises a first BNC joint, a phase-locked loop frequency synthesizer, a second BNC joint, a first isolating circuit, an RC filter circuit, a voltage-controlled oscillator, a second capacitor, a bias processing circuit, a symmetry processing circuit, a thirteenth resistor, a third BNC joint, a first inverter circuit, a first switch, a seventeenth resistor, an eighteenth resistor, a first adjustable proportional integrating circuit, a second switch, a first in-phase adder circuit, a twenty-third resistor, a twenty-fourth resistor, a fourth BNC joint, a second inverter circuit, a third switch, a twenty-eighth resistor and a twenty-ninth resistor. The invention is suitable for phase locking between two beams of laser.
Description
Technical Field
The invention relates to a laser phase locking technology, in particular to a laser phase rapid locking device with continuously tunable frequency.
Background
Laser has the advantages of good monochromaticity, high coherence, good directivity and high brightness, and is widely applied to the aspects of life, production, national defense, scientific research and the like. In many applications, phase locking between two lasers is often required. The phase locking between the two laser beams is as follows: the method comprises the steps of firstly taking a first laser beam as a reference laser, locking the frequency of the reference laser to the resonance transition frequency of atoms, molecules or an F-P cavity, then taking a second laser beam as a laser to be locked, carrying out beat frequency on the laser to be locked and the reference laser, and then locking the frequency of a beat frequency signal, thereby realizing the phase locking between the two laser beams. Under the prior art, people generally perform phase locking between two beams of laser light through effective combination of a radio frequency device and a PID feedback circuit. Such a laser phase locking technique has the following problems due to the limitations of the elements used: after the frequency of the beat signal is locked, the frequency of the beat signal cannot be continuously tuned, and thus the frequency of the second laser beam cannot be continuously tuned without unlocking. Therefore, if the frequency of the second laser needs to be modified, the phase locking between the two lasers must be manually performed again, which results in time-consuming and labor-consuming operation and poor application flexibility. Therefore, it is necessary to invent a laser phase fast locking device with continuously tunable frequency to solve the problem that the existing laser phase locking technology cannot continuously tune the frequency of the second beam of laser without unlocking.
Disclosure of Invention
The invention provides a laser phase rapid locking device with continuously tunable frequency, aiming at solving the problem that the existing laser phase locking technology can not continuously tune the frequency of a second beam of laser without unlocking.
The invention is realized by adopting the following technical scheme:
a laser phase quick locking device with continuously tunable frequency comprises a first BNC joint, a phase-locked loop frequency synthesizer, a second BNC joint, a first isolating circuit, an RC filter circuit, a voltage-controlled oscillator, a second capacitor, a bias processing circuit, a symmetrical processing circuit, a thirteenth resistor, a third BNC joint, a first inverter circuit, a first switch, a seventeenth resistor, an eighteenth resistor, a first adjustable proportional integrating circuit, a second switch, a first in-phase adder circuit, a twenty-third resistor, a twenty-fourth resistor, a fourth BNC joint, a second inverter circuit, a third switch, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eleventh resistor, a second adjustable proportional integrating circuit, a fourth switch, a second in-phase circuit, a thirty-sixth resistor, a thirty-seventh resistor, a fifth BNC joint, a sixth BNC joint, a frequency-adjustable proportional integrating circuit, a voltage-controlled oscillator, a voltage-up converter, a voltage-, The circuit comprises a second isolation circuit, a forty-second resistor, a fifth switch, a forty-third resistor and a biasing circuit;
the first isolation circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a first operational amplifier; the RC filter circuit comprises a sixth resistor and a first capacitor;
the bias processing circuit comprises a seventh resistor, an eighth resistor, a ninth resistor and a second operational amplifier; the symmetrical processing circuit comprises a tenth resistor, an eleventh resistor, a twelfth resistor and a third operational amplifier;
the first inverter circuit comprises a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a fourth operational amplifier;
the first adjustable proportional-integral circuit comprises a nineteenth resistor, a third capacitor, a fourth capacitor and a fifth operational amplifier; the first in-phase adder circuit comprises a twentieth resistor, a twenty-first resistor, a twenty-second resistor and a sixth operational amplifier;
the second inverter circuit comprises a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor and a seventh operational amplifier;
the second adjustable proportional-integral circuit comprises a thirty-second resistor, a fifth capacitor, a sixth capacitor and an eighth operational amplifier; the second in-phase adder circuit comprises a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor and a ninth operational amplifier;
the second isolation circuit comprises a thirty-eighth resistor, a thirty-ninth resistor, a fortieth resistor, a forty-first resistor and a tenth operational amplifier; the bias circuit comprises a forty-fourth resistor and a forty-fifth resistor;
the fifth resistor, the sixth resistor, the eighteenth resistor, the nineteenth resistor, the twenty-third resistor, the twenty-eighth resistor, the thirty-first resistor, the thirty-second resistor, the thirty-sixth resistor, the forty-second resistor and the forty-fourth resistor are all adjustable resistors;
the first switch and the third switch are both change-over switches;
the first BNC connector is connected with the radio frequency input end of the phase-locked loop frequency synthesizer;
the second BNC connector is connected with the positive input end of the first operational amplifier through a first resistor; one end of the second resistor is grounded, and the other end of the second resistor is connected with the positive input end of the first operational amplifier; one end of the third resistor is grounded, and the other end of the third resistor is connected with the negative input end of the first operational amplifier; one end of the fourth resistor is grounded, and the other end of the fourth resistor is connected with the negative input end of the first operational amplifier; one fixed end of the fifth resistor is connected with the +15V power supply end, the other fixed end of the fifth resistor is grounded, and the sliding end of the fifth resistor is connected with the reference voltage end of the first operational amplifier; the output end of the first operational amplifier is connected with one fixed end of the sixth resistor; the sliding end of the sixth resistor is connected with the frequency adjusting end of the voltage-controlled oscillator; one end of the first capacitor is grounded, and the other end of the first capacitor is connected with the frequency adjusting end of the voltage-controlled oscillator; the output end of the voltage-controlled oscillator is connected with the reference input end of the phase-locked loop frequency synthesizer;
one end of the second capacitor is grounded, and the other end of the second capacitor is connected with the output end of the phase-locked loop frequency synthesizer; the output end of the phase-locked loop frequency synthesizer is connected with the negative input end of the second operational amplifier through a seventh resistor; the positive input end of the second operational amplifier is connected with a +1.68V power supply end; the output end of the second operational amplifier is connected with the negative input end of the second operational amplifier through an eighth resistor on one hand, and is connected with the negative input end of the third operational amplifier through a ninth resistor on the other hand; one end of the eleventh resistor is connected with the +5V power supply end, and the other end of the eleventh resistor is connected with the positive input end of the third operational amplifier; one end of the twelfth resistor is grounded, and the other end of the twelfth resistor is connected with the positive input end of the third operational amplifier; the output end of the third operational amplifier is connected with the negative input end of the third operational amplifier through a tenth resistor on one hand, and is connected with a third BNC connector through a thirteenth resistor on the other hand;
one end of the fourteenth resistor is connected with the output end of the third operational amplifier, and the other end of the fourteenth resistor is connected with the negative input end of the fourth operational amplifier; one end of the sixteenth resistor is grounded, and the other end of the sixteenth resistor is connected with the positive input end of the fourth operational amplifier; the output end of the fourth operational amplifier is connected with the negative input end of the fourth operational amplifier through a fifteenth resistor on one hand, and is connected with the first static contact of the first switch on the other hand; the second stationary contact of the first switch is connected with the output end of the third operational amplifier;
one end of the seventeenth resistor is connected with the moving contact of the first switch, and the other end of the seventeenth resistor is connected with one fixed end of the eighteenth resistor; the sliding end of the eighteenth resistor is connected with the negative input end of the fifth operational amplifier; the positive input end of the fifth operational amplifier is grounded; the output end of the fifth operational amplifier is connected with the negative input end of the fifth operational amplifier through a fourth capacitor on one hand, and is connected with the negative input end of the sixth operational amplifier through a twentieth resistor on the other hand; the sliding end of the nineteenth resistor is connected with the output end of the fifth operational amplifier, and one fixed end of the nineteenth resistor is connected with the negative input end of the fifth operational amplifier through a third capacitor; two ends of the second switch are respectively connected with the negative input end of the fifth operational amplifier and the output end of the fifth operational amplifier; one end of the twenty-second resistor is grounded, and the other end of the twenty-second resistor is connected with the positive input end of the sixth operational amplifier; the output end of the sixth operational amplifier is connected with the negative input end of the sixth operational amplifier through the twenty-first resistor on one hand, and is connected with one fixed end of the twenty-third resistor on the other hand; the other fixed end of the twenty-third resistor is grounded, and the sliding end of the twenty-third resistor is connected with the fourth BNC connector through a twenty-fourth resistor;
one end of the twenty-fifth resistor is connected with the output end of the first operational amplifier, and the other end of the twenty-fifth resistor is connected with the negative input end of the seventh operational amplifier; one end of the twenty-seventh resistor is grounded, and the other end of the twenty-seventh resistor is connected with the positive input end of the seventh operational amplifier; the output end of the seventh operational amplifier is connected with the negative input end of the seventh operational amplifier through a twenty-sixth resistor on one hand, and is connected with the first static contact of the third switch on the other hand; the second stationary contact of the third switch is connected with the output end of the first operational amplifier; the moving contact of the third switch is connected with one fixed end of the twenty-eighth resistor; the other fixed end of the twenty-eighth resistor is grounded, and the sliding end of the twenty-eighth resistor is connected with the negative input end of the sixth operational amplifier through a twenty-ninth resistor;
one end of the thirtieth resistor is connected with the moving contact of the first switch, and the other end of the thirtieth resistor is connected with one fixed end of the thirty-first resistor; the other fixed end of the thirty-first resistor is grounded, and the sliding end of the thirty-first resistor is connected with the negative input end of the eighth operational amplifier; the positive input end of the eighth operational amplifier is grounded; the output end of the eighth operational amplifier is connected with the negative input end of the eighth operational amplifier through a sixth capacitor on the one hand, and is connected with the positive input end of the ninth operational amplifier through a thirteenth resistor on the other hand; the sliding end of the thirty-second resistor is connected with the output end of the eighth operational amplifier, and one fixed end of the thirty-second resistor is connected with the negative input end of the eighth operational amplifier through a fifth capacitor; two ends of the fourth switch are respectively connected with the negative input end of the eighth operational amplifier and the output end of the eighth operational amplifier; one end of the thirty-fifth resistor is grounded, and the other end of the thirty-fifth resistor is connected with the negative input end of the ninth operational amplifier; the output end of the ninth operational amplifier is connected with the positive input end of the ninth operational amplifier through a thirty-fourth resistor on one hand, and is connected with one fixed end of a thirty-sixth resistor on the other hand; the other fixed end of the thirty-sixth resistor is grounded, and the sliding end of the thirty-sixth resistor is connected with the fifth BNC connector through a thirty-seventh resistor;
the sixth BNC connector is connected with the positive input end of the tenth operational amplifier through a thirty-eighth resistor on one hand, and is connected with the negative input end of the tenth operational amplifier through a forty-fourth resistor on the other hand; one end of the thirty-ninth resistor is grounded, and the other end of the thirty-ninth resistor is connected with the positive input end of the tenth operational amplifier; one end of the forty-first resistor is grounded, and the other end of the forty-first resistor is connected with the negative input end of the tenth operational amplifier; the output end of the tenth operational amplifier is connected with one fixed end of a forty-second resistor; the other fixed end of the forty-second resistor is grounded, and the sliding end of the forty-third resistor is connected with the positive input end of the ninth operational amplifier through a fifth switch and a forty-third resistor in sequence; two fixed ends of the forty-fourth resistor are respectively connected with a +15V power supply end and a-15V power supply end, and the sliding end of the forty-fourth resistor is connected with the positive input end of the ninth operational amplifier through the forty-fifteenth resistor.
The first operational amplifier, the seventh operational amplifier and the tenth operational amplifier are INA114 type operational amplifiers; the second operational amplifier is an OP27 type operational amplifier; the third operational amplifier, the fourth operational amplifier, the fifth operational amplifier and the sixth operational amplifier are respectively four operational amplifiers of an OP467 type operational amplifier; the eighth operational amplifier and the ninth operational amplifier are respectively two operational amplifiers of the AD712 type operational amplifier.
The phase-locked loop frequency synthesizer is an ADF4007 type phase-locked loop frequency synthesizer; the voltage-controlled oscillator is a POS-50 voltage-controlled oscillator.
Two lasers are selected for operation. The first laser beam (namely the laser beam output by the first laser) is used as a reference laser beam, and the frequency of the reference laser beam is locked to the resonance transition frequency of the atom, the molecule or the F-P cavity. And taking the second laser beam (namely the laser beam output by the second laser) as the laser beam to be locked. And carrying out beat frequency on the laser to be locked and the reference laser, and transmitting beat frequency signals to a radio frequency input end of a phase-locked loop frequency synthesizer through a first BNC connector. And the second BNC connector is connected with the output end of the PC. And the third BNC connector is connected with the input end of the oscilloscope. And the fourth BNC joint is connected with the current feedback end of the second laser. And the fifth BNC joint is connected with the piezoelectric ceramic feedback end of the second laser. And the sixth BNC connector is connected with the output end of the scanning signal source.
The specific working process is as follows: first, the second switch, the fourth switch and the fifth switch are closed, the first fixed contact of the first switch is communicated with the movable contact, and the first fixed contact of the third switch is communicated with the movable contact. Then, the bias circuit outputs a bias voltage signal. And the bias voltage signal is transmitted to the piezoelectric ceramic feedback end of the second laser through the second in-phase adder circuit, the thirty-sixth resistor, the thirty-seventh resistor and the fifth BNC connector in sequence. Meanwhile, the scanning signal source outputs a scanning voltage signal. The scanning voltage signal is firstly isolated by the second isolating circuit, then is subjected to voltage division by the forty-second resistor, and then is transmitted to the piezoelectric ceramic feedback end of the second laser through the fifth switch, the forty-third resistor, the second in-phase adder circuit, the thirty-sixth resistor, the thirty-seventh resistor and the fifth BNC connector in sequence. Then, the PC outputs a control voltage signal. The control voltage signal is isolated and filtered by the first isolation circuit and the RC filter circuit in sequence and then transmitted to the frequency adjusting end of the voltage-controlled oscillator, so that the voltage-controlled oscillator outputs a radio frequency signal with determined frequency. The radio frequency signal is transmitted to a reference input end of the phase-locked loop frequency synthesizer. Meanwhile, the control voltage signal is subjected to phase inversion processing through the second inverter circuit, and then is fed back to the current feedback end of the second laser through the third switch, the twenty-eighth resistor, the twenty-ninth resistor, the first in-phase adder circuit, the twenty-third resistor, the twenty-fourth resistor and the fourth BNC connector in sequence. In this process, if the second fixed contact of the third switch is connected to the movable contact, the inversion process of the control voltage signal is omitted, so that the polarity of the control voltage signal can be changed, thereby ensuring rapid positive feedback of the control voltage signal. The radio frequency signal and the beat signal are then mixed in a phase-locked loop frequency synthesizer, thereby causing the phase-locked loop frequency synthesizer to output a current signal related to the frequency difference. The current signal is converted into a digital signal through the seventh resistor. The digital signal is subjected to bias processing and symmetrical processing by the bias processing circuit and the symmetrical processing circuit in sequence to form an error signal. And the error signal is transmitted to the input end of the oscilloscope through the thirteenth resistor and the third BNC connector in sequence. Meanwhile, the error signal is firstly subjected to phase inversion processing through a first phase inverter circuit, then passes through a first switch, and then is divided into two paths: the first path of error signal is fed back to the current feedback end of the second laser through a seventeenth resistor, an eighteenth resistor, a second switch, a first in-phase adder circuit, a twenty-third resistor, a twenty-fourth resistor and a fourth BNC connector in sequence. And the second path of error signal is fed back to the piezoelectric ceramic feedback end of the second laser through a thirtieth resistor, a thirty-first resistor, a fourth switch, a second in-phase adder circuit, a thirty-sixth resistor, a thirty-seventh resistor and a fifth BNC connector in sequence. In this process, if the second fixed contact of the first switch is connected to the movable contact, the inversion process of the error signal is omitted, and thus the feedback polarity of the error signal can be changed. Then, the bias voltage signal is continuously adjusted by adjusting the resistance value of the forty-fourth resistor, thereby adjusting the frequency of the second laser beam to be near the target value. At this time, the error signal is displayed correctly on the oscilloscope, and the error signal is monitored. Then, the amplitude of the divided scanning voltage signal is adjusted to zero by continuously adjusting the resistance value of the forty-second resistor. And then, the second switch and the fourth switch are sequentially switched off, and the first adjustable proportional-integral circuit and the second adjustable proportional-integral circuit sequentially start to work. And then, the fifth switch is switched off, and the first path of error signal is fed back to the current feedback end of the second laser through a seventeenth resistor, an eighteenth resistor, a first adjustable proportional-integral circuit, a first in-phase adder circuit, a twenty-third resistor, a twenty-fourth resistor and a fourth BNC joint in sequence. And the second path of error signal is fed back to the piezoelectric ceramic feedback end of the second laser through a thirtieth resistor, a thirty-first resistor, a second adjustable proportional-integral circuit, a second in-phase adder circuit, a thirty-sixth resistor, a thirty-seventh resistor and a fifth BNC joint in sequence. Under the combined action of the two paths of error signals, the frequency of the beat frequency signal and the frequency of the control voltage signal always keep a definite ratio relation, so that the frequency of the beat frequency signal is locked, and the phase locking between the two beams of laser is realized. In the process, the proportion of the first adjustable proportional-integral circuit can be continuously adjusted by adjusting the resistance value of the nineteenth resistor. By adjusting the resistance of the thirty-second resistor, the proportion of the second adjustable proportional-integral circuit can be continuously adjusted. After that, the frequency of the beat frequency signal can be changed by adjusting the frequency of the control voltage signal through the PC, so that the frequency of the beat frequency signal is continuously tuned, and the frequency of the second laser beam is continuously tuned without unlocking. Therefore, if the frequency of the second laser beam needs to be modified, the phase locking between the two laser beams does not need to be carried out again in a manual mode, and the frequency of the control voltage signal only needs to be modified through a PC.
Based on the process, compared with the existing laser phase locking technology, the laser phase quick locking device with the continuously tunable frequency realizes the continuous tuning of the frequency of the second beam of laser under the condition of no unlocking based on a brand new principle. Therefore, if the frequency of the second laser beam needs to be modified, the phase locking between the two laser beams does not need to be carried out again in a manual mode, and only the frequency of the control voltage signal needs to be modified through a PC, so that the operation is time-saving and labor-saving, and the application flexibility is stronger. In addition, the invention can rapidly change the frequency of the beat frequency signal along with the frequency of the control voltage signal by introducing current feedback (compared with the common voltage feedback, the current feedback is a relatively rapid feedback) on one hand and feeding the control voltage signal back to the current feedback end of the second laser on the other hand, thereby rapidly tuning the frequency of the beat frequency signal and rapidly tuning the frequency of the second laser without unlocking.
The invention effectively solves the problem that the frequency of the second laser beam cannot be continuously tuned under the condition of no unlocking in the existing laser phase locking technology, and is suitable for phase locking between the two laser beams.
Drawings
Fig. 1 is a circuit schematic of the present invention.
Detailed Description
A laser phase rapid locking device with continuously tunable frequency comprises a first BNC joint J1, a phase-locked loop frequency synthesizer H, a second BNC joint J2, a first isolation circuit, an RC filter circuit, a voltage-controlled oscillator P, a second capacitor C2, a bias processing circuit, a symmetrical processing circuit, a thirteenth resistor R13, a third BNC joint J3, a first inverter circuit, a first switch S1, a seventeenth resistor R17, an eighteenth resistor R18, a first adjustable proportional integral circuit, a second switch S2, a first in-phase adder circuit, a twenty-third resistor R23, a twenty-fourth resistor R24, a fourth BNC joint J4, a second inverter circuit, a third switch S3, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirty resistor R30, a thirty-first resistor R31, a second adjustable proportional integral circuit, a fourth switch S4, a sixth in-phase adder circuit, a thirty-third resistor R36, A thirty-seventh resistor R37, a fifth BNC connector J5, a sixth BNC connector J6, a second isolation circuit, a forty-second resistor R42, a fifth switch S5, a forty-third resistor R43 and a bias circuit;
the first isolation circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a first operational amplifier U1; the RC filter circuit comprises a sixth resistor R6 and a first capacitor C1;
the bias processing circuit comprises a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a second operational amplifier U2; the symmetrical processing circuit comprises a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12 and a third operational amplifier U3;
the first inverter circuit comprises a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a fourth operational amplifier U4;
the first adjustable proportional-integral circuit comprises a nineteenth resistor R19, a third capacitor C3, a fourth capacitor C4 and a fifth operational amplifier U5; the first in-phase adder circuit comprises a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22 and a sixth operational amplifier U6;
the second inverter circuit comprises a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27 and a seventh operational amplifier U7;
the second adjustable proportional-integral circuit comprises a thirty-second resistor R32, a fifth capacitor C5, a sixth capacitor C6 and an eighth operational amplifier U8; the second in-phase adder circuit comprises a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35 and a ninth operational amplifier U9;
the second isolation circuit comprises a thirty-eighth resistor R38, a thirty-ninth resistor R39, a forty-fourth resistor R40, a forty-first resistor R41 and a tenth operational amplifier U10; the bias circuit comprises a forty-fourth resistor R44 and a forty-fifth resistor R45;
the fifth resistor R5, the sixth resistor R6, the eighteenth resistor R18, the nineteenth resistor R19, the twenty-third resistor R23, the twenty-eighth resistor R28, the thirty-first resistor R31, the thirty-second resistor R32, the thirty-sixth resistor R36, the forty-second resistor R42 and the forty-fourth resistor R44 are all adjustable resistors;
the first switch S1 and the third switch S3 are both switches;
the first BNC connector J1 is connected with the radio frequency input end of the phase-locked loop frequency synthesizer H;
the second BNC joint J2 is connected with the positive input end of the first operational amplifier U1 through a first resistor R1; one end of the second resistor R2 is grounded, and the other end is connected with the positive input end of the first operational amplifier U1; one end of the third resistor R3 is grounded, and the other end of the third resistor R3 is connected with the negative input end of the first operational amplifier U1; one end of the fourth resistor R4 is grounded, and the other end of the fourth resistor R4 is connected with the negative input end of the first operational amplifier U1; one fixed end of the fifth resistor R5 is connected with the +15V power supply end, the other fixed end is grounded, and the sliding end is connected with the reference voltage end of the first operational amplifier U1; the output end of the first operational amplifier U1 is connected with one fixed end of a sixth resistor R6; the sliding end of the sixth resistor R6 is connected with the frequency adjusting end of the voltage-controlled oscillator P; one end of the first capacitor C1 is grounded, and the other end is connected with the frequency adjusting end of the voltage-controlled oscillator P; the output end of the voltage-controlled oscillator P is connected with the reference input end of the phase-locked loop frequency synthesizer H;
one end of the second capacitor C2 is grounded, and the other end is connected with the output end of the phase-locked loop frequency synthesizer H; the output end of the phase-locked loop frequency synthesizer H is connected with the negative input end of the second operational amplifier U2 through a seventh resistor R7; the positive input end of the second operational amplifier U2 is connected with the +1.68V power supply end; the output end of the second operational amplifier U2 is connected with the negative input end of the second operational amplifier U2 through an eighth resistor R8 on one hand, and is connected with the negative input end of the third operational amplifier U3 through a ninth resistor R9 on the other hand; one end of the eleventh resistor R11 is connected with the +5V power supply end, and the other end of the eleventh resistor R11 is connected with the positive input end of the third operational amplifier U3; one end of the twelfth resistor R12 is grounded, and the other end of the twelfth resistor R12 is connected with the positive input end of the third operational amplifier U3; the output end of the third operational amplifier U3 is connected to the negative input end of the third operational amplifier U3 through a tenth resistor R10 on the one hand, and is connected to the third BNC junction J3 through a thirteenth resistor R13 on the other hand;
one end of a fourteenth resistor R14 is connected with the output end of the third operational amplifier U3, and the other end of the fourteenth resistor R14 is connected with the negative input end of the fourth operational amplifier U4; one end of the sixteenth resistor R16 is grounded, and the other end of the sixteenth resistor R16 is connected with the positive input end of the fourth operational amplifier U4; the output end of the fourth operational amplifier U4 is connected to the negative input end of the fourth operational amplifier U4 through a fifteenth resistor R15 on the one hand, and to the first stationary contact of the first switch S1 on the other hand; the second stationary contact of the first switch S1 is connected with the output end of the third operational amplifier U3;
one end of the seventeenth resistor R17 is connected to the moving contact of the first switch S1, and the other end is connected to one fixed end of the eighteenth resistor R18; the sliding end of the eighteenth resistor R18 is connected with the negative input end of the fifth operational amplifier U5; the positive input end of the fifth operational amplifier U5 is grounded; the output end of the fifth operational amplifier U5 is connected to the negative input end of the fifth operational amplifier U5 through a fourth capacitor C4 on the one hand, and is connected to the negative input end of the sixth operational amplifier U6 through a twentieth resistor R20 on the other hand; the sliding end of the nineteenth resistor R19 is connected with the output end of the fifth operational amplifier U5, and one fixed end of the nineteenth resistor R19 is connected with the negative input end of the fifth operational amplifier U5 through a third capacitor C3; two ends of the second switch S2 are respectively connected with the negative input end of the fifth operational amplifier U5 and the output end of the fifth operational amplifier U5; one end of the twenty-second resistor R22 is grounded, and the other end of the twenty-second resistor R22 is connected with the positive input end of the sixth operational amplifier U6; the output end of the sixth operational amplifier U6 is connected to the negative input end of the sixth operational amplifier U6 through a twenty-first resistor R21 on the one hand, and is connected to one fixed end of a twenty-third resistor R23 on the other hand; the other fixed end of the twenty-third resistor R23 is grounded, and the sliding end is connected with the fourth BNC connector J4 through a twenty-fourth resistor R24;
one end of a twenty-fifth resistor R25 is connected with the output end of the first operational amplifier U1, and the other end of the twenty-fifth resistor R25 is connected with the negative input end of the seventh operational amplifier U7; one end of the twenty-seventh resistor R27 is grounded, and the other end of the twenty-seventh resistor R27 is connected with the positive input end of the seventh operational amplifier U7; the output end of the seventh operational amplifier U7 is connected to the negative input end of the seventh operational amplifier U7 through a twenty-sixth resistor R26 on the one hand, and to the first stationary contact of the third switch S3 on the other hand; the second stationary contact of the third switch S3 is connected with the output end of the first operational amplifier U1; the moving contact of the third switch S3 is connected with one fixed end of a twenty-eighth resistor R28; the other fixed end of the twenty-eighth resistor R28 is grounded, and the sliding end is connected with the negative input end of the sixth operational amplifier U6 through a twenty-ninth resistor R29;
one end of the thirty-first resistor R30 is connected with the moving contact of the first switch S1, and the other end is connected with one fixed end of the thirty-first resistor R31; the other fixed end of the thirty-first resistor R31 is grounded, and the sliding end of the thirty-first resistor R31 is connected with the negative input end of the eighth operational amplifier U8; the positive input end of the eighth operational amplifier U8 is grounded; the output end of the eighth operational amplifier U8 is connected to the negative input end of the eighth operational amplifier U8 through a sixth capacitor C6 on the one hand, and is connected to the positive input end of the ninth operational amplifier U9 through a thirteenth resistor R33 on the other hand; a sliding end of the thirty-second resistor R32 is connected with an output end of the eighth operational amplifier U8, and a fixed end of the thirty-second resistor R32 is connected with a negative input end of the eighth operational amplifier U8 through a fifth capacitor C5; two ends of the fourth switch S4 are respectively connected to the negative input terminal of the eighth operational amplifier U8 and the output terminal of the eighth operational amplifier U8; one end of the thirty-fifth resistor R35 is grounded, and the other end of the thirty-fifth resistor R35 is connected with the negative input end of the ninth operational amplifier U9; the output end of the ninth operational amplifier U9 is connected to the positive input end of the ninth operational amplifier U9 through a thirty-fourth resistor R34 on the one hand, and to one fixed end of a thirty-sixth resistor R36 on the other hand; the other fixed end of the thirty-sixth resistor R36 is grounded, and the sliding end is connected with the fifth BNC joint J5 through a thirty-seventeenth resistor R37;
the sixth BNC junction J6 is connected to the positive input terminal of the tenth operational amplifier U10 through a thirty-eighth resistor R38 on the one hand, and to the negative input terminal of the tenth operational amplifier U10 through a forty-fourth resistor R40 on the other hand; one end of the thirty-ninth resistor R39 is grounded, and the other end of the thirty-ninth resistor R39 is connected with the positive input end of the tenth operational amplifier U10; one end of a forty-first resistor R41 is grounded, and the other end of the forty-first resistor R41 is connected with the negative input end of the tenth operational amplifier U10; the output end of the tenth operational amplifier U10 is connected with one fixed end of a forty-second resistor R42; the other fixed end of the forty-second resistor R42 is grounded, and the sliding end is connected with the positive input end of the ninth operational amplifier U9 through a fifth switch S5 and a forty-third resistor R43 in sequence; two fixed ends of a forty-fourth resistor R44 are respectively connected with a +15V power supply end and a-15V power supply end, and a sliding end is connected with a positive input end of a ninth operational amplifier U9 through a forty-fifth resistor R45.
The first operational amplifier U1, the seventh operational amplifier U7 and the tenth operational amplifier U10 are INA114 type operational amplifiers; the second operational amplifier U2 is an OP27 type operational amplifier; the third operational amplifier U3, the fourth operational amplifier U4, the fifth operational amplifier U5 and the sixth operational amplifier U6 are respectively four operational amplifiers of an OP467 type operational amplifier; the eighth operational amplifier U8 and the ninth operational amplifier U9 are two operational amplifiers of an AD712 type operational amplifier respectively.
The phase-locked loop frequency synthesizer H is an ADF4007 type phase-locked loop frequency synthesizer; the voltage-controlled oscillator P is a POS-50 type voltage-controlled oscillator.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (3)
1. A laser phase rapid locking device with continuously tunable frequency is characterized in that: the phase-locked loop comprises a first BNC joint (J1), a phase-locked loop frequency synthesizer (H), a second BNC joint (J2), a first isolation circuit, an RC filter circuit, a voltage-controlled oscillator (P), a second capacitor (C2), a bias processing circuit, a symmetry processing circuit, a thirteenth resistor (R13), a third BNC joint (J3), a first inverter circuit, a first switch (S1), a seventeenth resistor (R17), an eighteenth resistor (R18), a first adjustable proportional integrating circuit, a second switch (S2), a first in-phase adder circuit, a twenty-third resistor (R23), a twenty-fourth resistor (R24), a fourth BNC joint (J4), a second inverter circuit, a third switch (S3), a twenty-eighth resistor (R28), a twenty-ninth resistor (R29), a third resistor (R30), a third eleventh resistor (R31), a second adjustable proportional integrating circuit, a fourth switch (S4), a twenty-ninth resistor (R28), a thirty resistor (R29), A second in-phase adder circuit, a thirty-sixth resistor (R36), a thirty-seventh resistor (R37), a fifth BNC connector (J5), a sixth BNC connector (J6), a second isolation circuit, a forty-second resistor (R42), a fifth switch (S5), a forty-third resistor (R43), and a bias circuit;
the first isolation circuit comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5) and a first operational amplifier (U1); the RC filter circuit comprises a sixth resistor (R6) and a first capacitor (C1);
the bias processing circuit comprises a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9) and a second operational amplifier (U2); the symmetrical processing circuit comprises a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12) and a third operational amplifier (U3);
the first inverter circuit comprises a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16) and a fourth operational amplifier (U4);
the first adjustable proportional-integral circuit comprises a nineteenth resistor (R19), a third capacitor (C3), a fourth capacitor (C4) and a fifth operational amplifier (U5); the first in-phase adder circuit comprises a twentieth resistor (R20), a twenty-first resistor (R21), a twenty-second resistor (R22), and a sixth operational amplifier (U6);
the second inverter circuit comprises a twenty-fifth resistor (R25), a twenty-sixth resistor (R26), a twenty-seventh resistor (R27) and a seventh operational amplifier (U7);
the second adjustable proportional-integral circuit comprises a thirty-second resistor (R32), a fifth capacitor (C5), a sixth capacitor (C6) and an eighth operational amplifier (U8); the second in-phase adder circuit comprises a thirty-third resistor (R33), a thirty-fourth resistor (R34), a thirty-fifth resistor (R35) and a ninth operational amplifier (U9);
the second isolation circuit comprises a thirty-eighth resistor (R38), a thirty-ninth resistor (R39), a forty-fourth resistor (R40), a forty-first resistor (R41) and a tenth operational amplifier (U10); the bias circuit comprises a forty-fourth resistor (R44), a forty-fifth resistor (R45);
the fifth resistor (R5), the sixth resistor (R6), the eighteenth resistor (R18), the nineteenth resistor (R19), the twenty-third resistor (R23), the twenty-eighth resistor (R28), the thirty-first resistor (R31), the thirty-second resistor (R32), the thirty-sixth resistor (R36), the forty-second resistor (R42) and the forty-fourth resistor (R44) are all adjustable resistors;
the first switch (S1) and the third switch (S3) are both change-over switches;
wherein the first BNC connector (J1) is connected with the radio frequency input end of the phase-locked loop frequency synthesizer (H);
the second BNC connector (J2) is connected with the positive input end of the first operational amplifier (U1) through a first resistor (R1); one end of the second resistor (R2) is grounded, and the other end of the second resistor (R2) is connected with the positive input end of the first operational amplifier (U1); one end of the third resistor (R3) is grounded, and the other end of the third resistor (R3) is connected with the negative input end of the first operational amplifier (U1); one end of the fourth resistor (R4) is grounded, and the other end of the fourth resistor (R4) is connected with the negative input end of the first operational amplifier (U1); one fixed end of the fifth resistor (R5) is connected with the +15V power supply end, the other fixed end of the fifth resistor is grounded, and the sliding end of the fifth resistor is connected with the reference voltage end of the first operational amplifier (U1); the output end of the first operational amplifier (U1) is connected with one fixed end of a sixth resistor (R6); the sliding end of the sixth resistor (R6) is connected with the frequency adjusting end of the voltage-controlled oscillator (P); one end of the first capacitor (C1) is grounded, and the other end of the first capacitor (C1) is connected with the frequency adjusting end of the voltage-controlled oscillator (P); the output end of the voltage-controlled oscillator (P) is connected with the reference input end of the phase-locked loop frequency synthesizer (H);
one end of the second capacitor (C2) is grounded, and the other end of the second capacitor is connected with the output end of the phase-locked loop frequency synthesizer (H); the output end of the phase-locked loop frequency synthesizer (H) is connected with the negative input end of the second operational amplifier (U2) through a seventh resistor (R7); the positive input end of the second operational amplifier (U2) is connected with the +1.68V power supply end; the output end of the second operational amplifier (U2) is connected with the negative input end of the second operational amplifier (U2) through an eighth resistor (R8) on one hand, and is connected with the negative input end of the third operational amplifier (U3) through a ninth resistor (R9) on the other hand; one end of an eleventh resistor (R11) is connected with a +5V power supply end, and the other end of the eleventh resistor (R11) is connected with the positive input end of a third operational amplifier (U3); one end of the twelfth resistor (R12) is grounded, and the other end of the twelfth resistor (R12) is connected with the positive input end of the third operational amplifier (U3); the output end of the third operational amplifier (U3) is connected with the negative input end of the third operational amplifier (U3) through a tenth resistor (R10) on one hand, and is connected with a third BNC connector (J3) through a thirteenth resistor (R13) on the other hand;
one end of a fourteenth resistor (R14) is connected with the output end of the third operational amplifier (U3), and the other end of the fourteenth resistor (R14) is connected with the negative input end of the fourth operational amplifier (U4); one end of a sixteenth resistor (R16) is grounded, and the other end of the sixteenth resistor is connected with the positive input end of a fourth operational amplifier (U4); the output end of the fourth operational amplifier (U4) is connected with the negative input end of the fourth operational amplifier (U4) through a fifteenth resistor (R15) on one hand, and is connected with the first static contact of the first switch (S1) on the other hand; the second stationary contact of the first switch (S1) is connected with the output end of the third operational amplifier (U3);
one end of a seventeenth resistor (R17) is connected with the moving contact of the first switch (S1), and the other end is connected with one fixed end of an eighteenth resistor (R18); the sliding end of the eighteenth resistor (R18) is connected with the negative input end of the fifth operational amplifier (U5); the positive input end of the fifth operational amplifier (U5) is grounded; the output end of the fifth operational amplifier (U5) is connected with the negative input end of the fifth operational amplifier (U5) through a fourth capacitor (C4) on one hand, and is connected with the negative input end of the sixth operational amplifier (U6) through a twentieth resistor (R20) on the other hand; the sliding end of a nineteenth resistor (R19) is connected with the output end of a fifth operational amplifier (U5), and one fixed end of the nineteenth resistor is connected with the negative input end of the fifth operational amplifier (U5) through a third capacitor (C3); two ends of the second switch (S2) are respectively connected with the negative input end of the fifth operational amplifier (U5) and the output end of the fifth operational amplifier (U5); one end of the twenty-second resistor (R22) is grounded, and the other end of the twenty-second resistor (R22) is connected with the positive input end of the sixth operational amplifier (U6); the output end of the sixth operational amplifier (U6) is connected with the negative input end of the sixth operational amplifier (U6) through a twenty-first resistor (R21) on one hand, and is connected with one fixed end of a twenty-third resistor (R23) on the other hand; the other fixed end of the twenty-third resistor (R23) is grounded, and the sliding end of the twenty-third resistor (R23) is connected with the fourth BNC connector (J4) through a twenty-fourth resistor (R24);
one end of a twenty-fifth resistor (R25) is connected with the output end of the first operational amplifier (U1), and the other end of the twenty-fifth resistor is connected with the negative input end of the seventh operational amplifier (U7); one end of a twenty-seventh resistor (R27) is grounded, and the other end of the twenty-seventh resistor is connected with the positive input end of a seventh operational amplifier (U7); the output end of the seventh operational amplifier (U7) is connected to the negative input end of the seventh operational amplifier (U7) through a twenty-sixth resistor (R26) on the one hand, and is connected to the first stationary contact of the third switch (S3) on the other hand; the second stationary contact of the third switch (S3) is connected with the output end of the first operational amplifier (U1); the moving contact of the third switch (S3) is connected with one fixed end of a twenty-eighth resistor (R28); the other fixed end of the twenty-eighth resistor (R28) is grounded, and the sliding end is connected with the negative input end of the sixth operational amplifier (U6) through a twenty-ninth resistor (R29);
one end of the thirtieth resistor (R30) is connected with the moving contact of the first switch (S1), and the other end is connected with one fixed end of the thirty-first resistor (R31); the other fixed end of the thirty-first resistor (R31) is grounded, and the sliding end of the thirty-first resistor is connected with the negative input end of the eighth operational amplifier (U8); the positive input end of the eighth operational amplifier (U8) is grounded; the output end of the eighth operational amplifier (U8) is connected with the negative input end of the eighth operational amplifier (U8) through a sixth capacitor (C6) on one hand, and is connected with the positive input end of the ninth operational amplifier (U9) through a thirteenth resistor (R33) on the other hand; the sliding end of a thirty-second resistor (R32) is connected with the output end of the eighth operational amplifier (U8), and one fixed end of the thirty-second resistor is connected with the negative input end of the eighth operational amplifier (U8) through a fifth capacitor (C5); two ends of the fourth switch (S4) are respectively connected with the negative input end of the eighth operational amplifier (U8) and the output end of the eighth operational amplifier (U8); one end of a thirty-fifth resistor (R35) is grounded, and the other end of the thirty-fifth resistor is connected with the negative input end of the ninth operational amplifier (U9); the output end of the ninth operational amplifier (U9) is connected with the positive input end of the ninth operational amplifier (U9) through a thirty-fourth resistor (R34) on one hand, and is connected with one fixed end of a thirty-sixth resistor (R36) on the other hand; the other fixed end of the thirty-sixth resistor (R36) is grounded, and the sliding end is connected with the fifth BNC joint (J5) through a thirty-seventh resistor (R37);
the sixth BNC connector (J6) is connected with the positive input end of the tenth operational amplifier (U10) through a eighteenth resistor (R38) on one hand, and is connected with the negative input end of the tenth operational amplifier (U10) through a fortieth resistor (R40) on the other hand; one end of a thirty-ninth resistor (R39) is grounded, and the other end of the thirty-ninth resistor is connected with the positive input end of a tenth operational amplifier (U10); one end of a forty-first resistor (R41) is grounded, and the other end of the forty-first resistor is connected with the negative input end of a tenth operational amplifier (U10); the output end of the tenth operational amplifier (U10) is connected with one fixed end of a forty-second resistor (R42); the other fixed end of the forty-second resistor (R42) is grounded, and the sliding end of the forty-third resistor (R43) is connected with the positive input end of the ninth operational amplifier (U9) through a fifth switch (S5) and a forty-third resistor (R43); two fixed ends of a forty-fourth resistor (R44) are respectively connected with a +15V power supply end and a-15V power supply end, and a sliding end is connected with a positive input end of a ninth operational amplifier (U9) through a forty-fifth resistor (R45).
2. A laser phase fast lock apparatus with continuously tunable frequency as claimed in claim 1, wherein: the first operational amplifier (U1), the seventh operational amplifier (U7) and the tenth operational amplifier (U10) are INA114 type operational amplifiers; the second operational amplifier (U2) is an OP27 type operational amplifier; the third operational amplifier (U3), the fourth operational amplifier (U4), the fifth operational amplifier (U5) and the sixth operational amplifier (U6) are respectively four operational amplifiers of an OP467 type operational amplifier; and the eighth operational amplifier (U8) and the ninth operational amplifier (U9) are two operational amplifiers of the AD712 type operational amplifier respectively.
3. A laser phase fast lock apparatus with continuously tunable frequency as claimed in claim 1, wherein: the phase-locked loop frequency synthesizer (H) is an ADF4007 type phase-locked loop frequency synthesizer; the voltage-controlled oscillator (P) is a POS-50 type voltage-controlled oscillator.
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