CN112670371B - Side gate transistor terahertz detector and preparation method thereof - Google Patents
Side gate transistor terahertz detector and preparation method thereof Download PDFInfo
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- CN112670371B CN112670371B CN202011566704.7A CN202011566704A CN112670371B CN 112670371 B CN112670371 B CN 112670371B CN 202011566704 A CN202011566704 A CN 202011566704A CN 112670371 B CN112670371 B CN 112670371B
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Abstract
The invention discloses a preparation method of a side gate transistor terahertz detector and the side gate transistor terahertz detector, wherein the method comprises the following steps: manufacturing a source electrode and a drain electrode on a substrate; spin-coating resists on the substrate, the source electrode and the drain electrode, removing part of the resists by using an exposure technology, exposing part of the substrate, and forming a mesa resist mask; etching a part of the substrate with a preset depth according to the mesa resist mask to form a mesa of the substrate; making a gate image on the mesa resist mask and the substrate and forming a gate electrode; removing the mesa resist mask, and simultaneously stripping the top gate on the mesa resist mask to form double-gate electrodes on two sides of the mesa; and manufacturing antenna patterns on the surfaces of the substrate, the source electrode, the drain electrode and the double-grid electrode, and forming an antenna and a lead to obtain the side-grid transistor terahertz detector.
Description
Technical Field
The invention relates to the field of semiconductor material and device manufacturing, in particular to a side gate transistor terahertz detector and a preparation method thereof.
Background
In recent years, a terahertz detector for wide-range commercial use is a diode detector, and the terahertz detector cannot be applied to precise terahertz detection due to low responsivity and low response speed in practical application. Therefore, laboratories in various countries are researching the performance characterization of Field Effect Transistors (FETs) for terahertz detection and performing various performance optimizations. The resonance probing of the FET probe has a higher responsivity than the non-resonance probing in theoretical studies, but it is difficult to study because it is not easily detectable at room temperature. The side gate transistor is just one structure designed to solve the resonance problem.
A side Gate Transistor (Lateral Gate Transistor) terahertz detector is a novel high electron mobility Transistor terahertz detector structure and comprises a table board, a source electrode, a drain electrode, a Gate electrode and an antenna, wherein the Gate electrode and the antenna are located on two sides of a channel. Compared with the traditional terahertz detector structure of the high-electron-mobility transistor, the side-gate transistor can change the effective gate width of the two-dimensional electron gas through the additional gate voltage of the two side gates, control the width of a two-dimensional electron gas channel and eliminate a stray plasma wave mode, so that the terahertz resonance detection responsivity of the device is improved, and the bandwidth of a resonance detection response peak of the device is reduced.
In the process of manufacturing the side gate transistor, a multilayer process needs to be performed for multiple times of alignment. The overlay is an important process parameter in the control of the exposure process, and is also one of the main factors influencing the yield of the product. In order to meet the requirement of alignment precision, alignment matching must be made.
The existing preparation method of the side gate transistor is a traditional alignment process, the alignment process is to directly align the side gates to two sides of the table top by using an electron beam exposure machine, and due to the influence of various factors, such as the heat treatment process outside the alignment process, the deformation of a sample wafer, the quality of alignment marks of the alignment process, and the like, the offset between the upper layer of graph and the lower layer of graph, namely the offset between the table top and the side gates can be influenced, the conditions that the side gates are lapped on the table top, the side gates are far away from the table top or other poor contacts can occur, so that the accuracy of alignment is difficult to ensure, and the performance of a device can be influenced finally.
Disclosure of Invention
In view of this, in order to ensure accurate alignment effect and contact effect of the gate and the mesa, the invention provides a side-gate transistor terahertz detector and a manufacturing method thereof, so as to improve the performance of the side-gate transistor terahertz detector.
In order to achieve the above object, in one aspect, the present invention provides a method for manufacturing a side-gate transistor terahertz detector, including: manufacturing a source electrode and a drain electrode on a substrate; spin-coating resists on the substrate, the source electrode and the drain electrode, removing part of the resists by using an exposure technology, exposing part of the substrate, and forming a mesa resist mask; etching a part of the substrate with a preset depth according to the mesa resist mask to form a mesa of the substrate; making a grid image on the mesa resist mask and the substrate and forming a grid electrode; removing the mesa resist mask, and simultaneously stripping the top gate on the mesa resist mask to form dual-gate electrodes on two sides of the mesa; and manufacturing antenna patterns on the surfaces of the substrate, the source electrode, the drain electrode and the double-grid electrode, and forming an antenna and a lead to obtain the side-grid transistor terahertz detector.
According to an embodiment of the present invention, wherein fabricating the source electrode and the drain electrode on the substrate comprises: spin-coating first photoresist on a substrate, and removing part of the first photoresist by using a micro-nano processing technology to form a source region graph and a drain region graph; depositing a metal layer on the residual first photoresist and the source region graph and the drain region graph; and removing the residual first photoresist, simultaneously stripping the deposited metal layer outside the source region pattern and the drain region pattern area, and performing rapid thermal annealing to form a source electrode and a drain electrode.
According to an embodiment of the invention, wherein the substrate material comprises one of: silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, indium phosphide; the first photoresist is electron beam photoresist or ultraviolet photoresist.
According to an embodiment of the invention, wherein the exposure technique comprises one of: electron beam exposure, ion beam exposure, X-ray exposure, holographic exposure, optical contact exposure, optical projection exposure.
According to an embodiment of the present invention, wherein the predetermined depth is 1nm to 10 μm.
According to an embodiment of the present invention, wherein the making a gate image and forming a gate electrode on a mesa resist mask and a substrate comprises: spin-coating a second photoresist on the mesa resist mask and the substrate, removing part of the second photoresist by using a micro-nano processing technology, and manufacturing a grid pattern; depositing a grid metal layer on the residual second photoresist and the grid pattern; and removing the residual second photoresist and simultaneously stripping the gate metal layer deposited outside the gate pattern region to obtain the gate electrode.
According to an embodiment of the invention, wherein the depositing comprises: thermal evaporation, electron beam evaporation and magnetron sputtering; the material of the metal layer comprises one or more of the following combinations: ti, al, ni, mo, pt, au, pd, W.
According to an embodiment of the invention, the etching method comprises one of the following steps: inductively coupled plasma etching, reactive ion beam etching, and wet etching.
According to an embodiment of the invention, wherein the resist comprises one of: photoresist, electron beam resist, organic matter, dielectric.
On the other hand, the invention also provides the side gate transistor terahertz detector prepared by the preparation method.
According to the embodiment of the invention, the mesa is etched by utilizing the mesa resist mask, the grid is manufactured under the condition that the mesa resist mask is not removed, the top grid is stripped by taking the resist as the top grid stripping sacrificial layer, and the metal side grids are formed on two sides of the mesa, so that the problems of low alignment precision and poor or over-contact of the side grids and the mesa are solved, the high-precision alignment effect and the contact effect of the side grids and the mesa are realized, and the device performance is better improved; the preparation method has the advantages of self-alignment, high controllability, good repeatability and the like, and is simple and easy to realize.
Drawings
Fig. 1 schematically shows a flowchart of a method for manufacturing a side-gate transistor terahertz detector according to an embodiment of the invention;
fig. 2-11 schematically show a flow chart of a method for manufacturing a side-gate transistor terahertz detector according to an embodiment of the invention.
[ legends of drawings ]
A substrate 10; a table top 11; a first photoresist 20; a source drain region pattern 21; a metal layer 30; source-drain region ohmic contact electrode 31; a mesa resist mask 41; a second photoresist 50; a gate pattern 51; a gate metal layer 60; a gate electrode 61; a double gate electrode 62; a metal antenna and a lead 71.
Detailed Description
In order to solve the problems of low alignment accuracy of a side gate and a table top and poor contact caused by a traditional alignment process, so that the performance of a device is influenced, the invention provides a preparation method of a side gate transistor terahertz detector to solve the technical problems.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings in combination with the embodiments.
Fig. 1 schematically shows a flowchart of a method for manufacturing a side-gate transistor terahertz detector according to an embodiment of the invention; fig. 2-11 schematically show a flow chart of a method for manufacturing a side-gate transistor terahertz detector according to an embodiment of the invention. The method for manufacturing the side-gate transistor terahertz detector provided by the invention is described in detail with reference to fig. 1 and fig. 2 to fig. 11.
As shown in fig. 1, the method for manufacturing a side-gate transistor terahertz detector provided by the invention includes operations S101 to S106.
In operation S101, a source electrode and a drain electrode are fabricated on a substrate.
In an embodiment of the present invention, fabricating the source electrode and the drain electrode on the substrate includes:
(a) A first photoresist 20 is spin-coated on the substrate 10, and a micro-nano processing technology is used to remove a portion of the first photoresist, so as to form a source region pattern and a drain region pattern (hereinafter referred to as a source/drain region pattern 21). As shown in fig. 2.
According to an embodiment of the present invention, the substrate 10 may be made of silicon, germanium, or a III-V semiconductor such as silicon carbide, gallium nitride, gallium arsenide, or indium phosphide.
According to the embodiment of the invention, the forming of the source/drain region pattern 21 by using the micro-nano processing technology comprises the following steps: by using the photolithography technique, a source/drain region pattern is formed by exposing, developing and fixing the first photoresist 20. According to the embodiment of the present invention, the first photoresist 20 is an electron beam resist or an ultraviolet resist, and optionally, the first photoresist may be an electron beam positive resist which is easy to strip; the exposure mode includes one of the following: electron beam exposure, ion beam exposure, X-ray exposure, holographic exposure, optical contact exposure, optical projection exposure.
According to the different sizes of the designed source-drain region patterns 21, the types of the first photoresist 20 to be selected are different, so that different exposure modes are selected according to the different types of the first photoresist 20.
For example, the size of the designed source/drain region pattern 21 is smaller than 0.1 μm, an electron beam glue can be used, and modes such as electron beam exposure, ion beam exposure, X-ray exposure and the like can be selected to expose the source/drain region pattern 21; the size of the designed source drain region pattern 21 is more than or equal to 0.1 mu m, ultraviolet photoresist can be used, and optical contact type exposure and optical projection type exposure can be selected.
According to the embodiment of the present invention, the developing and fixing selects different developing solutions and fixing solutions according to the selection of different kinds of the first photoresist 20.
(b) And depositing a metal layer 30 on the remaining first photoresist and the source region pattern and the drain region pattern. As shown in fig. 3.
In an embodiment of the invention, the material of the metal layer comprises a combination of one or more of the following: ti, al, ni, mo, pt, au, pd, W; in this step, the metal layer 30 is used for manufacturing a source electrode and a drain electrode (hereinafter referred to as a source-drain ohmic contact electrode 31), and may adopt a four-layer metal structure, which may be from bottom to top:
a barrier layer, the barrier layer being selected from metallic barrier layer compounds capable of forming a low resistance, low work function, thin and thermally stable metal with the mesa 11, metals such as Ti, ta, zr and Co;
a covering layer, the metal of which plays a catalytic role, and the common metal is Al;
a diffusion barrier layer, the metal of which is arranged between the cap layer and the covering layer to prevent the mutual diffusion of the elements, and the metals such as Pt/Pa, ni, cr, mo, ta, W and the like are commonly used;
and the cap layer keeps stable and low-resistance external contact and prevents the metal oxidation of the barrier layer and the covering layer, and the common metal is Au.
Alternatively, the material of the metal layer 30 may be a combination of Ti/Al/Ni/Au.
According to the embodiment of the invention, the metal layer 30 may be deposited by thermal evaporation, electron beam evaporation, or magnetron sputtering. Optionally, the electron beam evaporation method is one of vacuum evaporation coating, and a method of directly heating the evaporation material by using an electron beam under a vacuum condition to vaporize the evaporation material and transport the evaporation material to the substrate, and condensing the evaporation material on a base to form a thin film can accurately control the metal thickness and is beneficial to a subsequent stripping process.
(c) And removing the residual first photoresist, simultaneously stripping the metal layer 30 deposited outside the source region pattern and the drain region pattern area, and performing rapid thermal annealing to form a source electrode and a drain electrode (hereinafter referred to as a source-drain region ohmic contact electrode 31). As shown in fig. 4.
In the embodiment of the present invention, the metal layer 30 outside the source region pattern and the drain region pattern is stripped by a stripping process while the remaining first photoresist is removed by the stripper.
Rapid thermal annealing, according to an embodiment of the present invention, is a process in which a wafer is processed with a very fast ramp-up and a short dwell at a target temperature. A rapid thermal annealing process is used in order to form ohmic contacts between the source and drain electrodes and the mesa.
According to the embodiment of the invention, the source electrode and the drain electrode are prepared by adopting the photoetching technology, the electron beam metal evaporation technology and the rapid thermal annealing technology, the technology is mature, and the performance is reliable.
In operation S102, a resist is spin-coated on the substrate and the source and drain electrodes, and a mesa resist mask is formed by removing a portion of the resist using an exposure technique to expose a portion of the substrate.
In the embodiment of the present invention, a resist 40 is spin-coated on the substrate 10, the source and drain electrodes (source-drain region ohmic contact electrodes 31), and exposed on the resist 40 using an exposure technique, developed, and fixed to form the mesa resist mask 41. As shown in fig. 5, the resist 40 is not shown in fig. 5.
Resist 40 may be photoresist, e-beam resist, organic, or dielectric, according to embodiments of the present invention. Depending on the type of resist 40 selected, the subsequent exposure method, and the developing solution and the fixing solution may be different. The specific selection method can be referred to in S101 (a), and is not described herein again.
According to an embodiment of the present invention, the mesa resist mask 41 may serve as an etch mask for the mesas 11, as well as a sacrificial layer for subsequent top gate lift-off. Alternatively, the resist may be an electron beam negative resist.
In operation S103, a portion of the substrate of a predetermined depth is etched according to the mesa resist mask to form a mesa of the substrate.
In the embodiment of the present invention, the mesa 11 is formed by etching a portion of the substrate of a predetermined depth through the mesa resist mask 41 in the region outside the mesa resist mask 41. As shown in fig. 6.
According to the embodiment of the invention, the preset etching depth is 1 nm-10 μm, and the subsequent top gate stripping is influenced because the conductive channel cannot be etched due to over-shallow etching; too deep etching leads to difficulty in subsequent metal climbing, and device failure is caused. Optionally, the etching preset depth is 100nm.
According to the embodiment of the invention, the etching can be performed by Ion Beam Etching (IBE), reactive ion beam etching (RIE), inductively coupled plasma etching (ICP), and the like. Optionally, the etching manner may be inductively coupled plasma etching (ICP), and the etching manner may obtain a higher etching rate and a lower etching damage by controlling the energy and density of the plasma.
According to the embodiment of the invention, the electron beam exposure technology and the etching process are adopted to prepare the table board, the operation is simple, the efficiency is high, the exposure layout is modified randomly, the pattern feature size is small, and the exposure precision is high.
In operation S104, a gate image is made on the mesa resist mask and the substrate and a gate electrode is formed.
In an embodiment of the present invention, operation S104 further includes:
(a) A second photoresist 50 is spin-coated on the mesa resist mask 41 and the substrate 10, and a part of the second photoresist is removed by using a micro-nano processing technology to fabricate a gate pattern 51. As shown in fig. 7.
In the embodiment of the invention, the manufacturing of the grid graph by utilizing the micro-nano processing technology comprises the following steps: the gate pattern 51 is formed on the second photoresist 50 by exposure, development and fixation.
According to an embodiment of the present invention, the second photoresist 50 may be an electron beam photoresist or an ultraviolet photoresist, which is the same kind as the first photoresist 20 described above. According to the difference of the second photoresist type and the subsequent exposure manner, the step (a) in S101 may be referred to for specific selection, and details are not repeated herein.
Optionally, the second photoresist may be a double-layer electron beam positive photoresist, and since the size of the gate pattern 61 is small (less than or equal to 100 nm), the sensitivity of the upper layer photoresist is low, the sensitivity of the bottom layer photoresist is high, after exposure and development and fixation, the double-layer electron beam positive photoresist can form an inverted trapezoidal structure and is easy to strip; the exposure mode may be selected as electron beam exposure.
According to an embodiment of the present invention, the thickness of the second photoresist 50 is greater than the thickness of the evaporated gate metal layer 60.
(b) A gate metal layer 60 is deposited on the remaining second photoresist and on the gate pattern 51. As shown in fig. 8.
According to the embodiment of the invention, the method for depositing the gate metal layer 60 may be thermal evaporation, electron beam evaporation, magnetron sputtering, and optionally, the deposition manner may be an electron beam evaporation metal process.
According to an embodiment of the present invention, a gate metal layer 60 is used as the gate electrode 61. The material of the gate metal layer 60 includes one or a combination of: metals such as Ti, al, ni, mo, pt, au, pd, and W. The depth of the gate metal layer 60 is considered in combination with the etching depth of the mesa 11, optionally the material is a combination of Ni/Au with a thickness of Ni/Au =20/80nm, respectively.
(c) And removing the residual second photoresist and simultaneously stripping the gate metal layer deposited outside the gate pattern area to obtain the gate electrode. As shown in fig. 9.
In the embodiment of the invention, the residual second photoresist is removed by using the photoresist stripper, and the gate metal layer 60 outside the gate pattern region is stripped by using a stripping process.
In operation S105, the mesa resist mask 41 is removed while the top gate on the mesa resist mask is stripped, and the double gate electrodes 62, i.e., the side gate electrodes, are formed on both sides of the mesa. As shown in fig. 10.
The method of removing the mesa resist mask 41 may be wet etching or plasma etching according to an embodiment of the present invention.
According to the embodiment of the invention, the double-gate electrode is prepared by adopting an electron beam exposure technology, an electron beam metal evaporation process and a stripping process, the preparation is convenient, the alignment precision of the side gate electrode and the table top is high, and the problem of poor contact or over contact between the table top and the side gate can be avoided by top gate stripping.
In operation S106, antenna patterns are formed on the surfaces of the substrate, the source electrode, the drain electrode, and the dual-gate electrode, and an antenna and a lead are formed, so as to obtain the side-gate transistor terahertz detector.
In the embodiment of the invention, a third photoresist is deposited on the surfaces of the substrate 10, the source-drain region ohmic contact electrode 31 and the double gate electrode 62, and the third photoresist is exposed, developed and fixed by using a photolithography technique to form an antenna pattern. And then depositing an antenna metal layer, removing the residual third photoresist, and simultaneously stripping the antenna metal layer deposited outside the antenna pattern area by utilizing a stripping process to form a metal antenna and a lead wire 71. As shown in fig. 11.
According to the embodiment of the invention, the mesa is etched by utilizing the mesa resist mask, the grid is manufactured under the condition that the mesa resist mask is not removed, the resist is used as a top grid stripping sacrificial layer to strip the top grid, metal side grids are formed on two sides of the mesa, the high-precision self-alignment of the side grid transistor terahertz detector is realized, and the problems of low overlay precision and poor contact or over contact of the side grids and the mesa are solved, so that the high-precision alignment effect and the contact effect of the side grids and the mesa are realized, and the device performance is better improved; the preparation method has the advantages of self-alignment, high controllability, good repeatability and the like, and is simple and easy to implement.
It will be appreciated by a person skilled in the art that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present invention are possible, even if such combinations or combinations are not explicitly recited in the present invention. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present invention may be made without departing from the spirit or teaching of the invention. All such combinations and/or associations fall within the scope of the present invention.
The above embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A preparation method of a side-gate transistor terahertz detector comprises the following steps:
manufacturing a source electrode and a drain electrode on a substrate;
spin-coating a resist on the substrate, the source electrode and the drain electrode, and removing part of the resist by using an exposure technology to expose part of the substrate and form a mesa resist mask;
etching the part of the substrate with a preset depth according to the mesa resist mask to form a mesa of the substrate;
making a gate image on the mesa resist mask and the substrate and forming a gate electrode;
removing the mesa resist mask, and simultaneously stripping the top gate on the mesa resist mask to form double-gate electrodes on two sides of the mesa;
and manufacturing antenna patterns on the surfaces of the substrate, the source electrode, the drain electrode and the double-grid electrode, and forming the antenna and a lead to obtain the side-grid transistor terahertz detector.
2. The method of claim 1, wherein the fabricating a source electrode and a drain electrode on a substrate comprises:
spin-coating first photoresist on the substrate, and removing part of the first photoresist by using a micro-nano processing technology to form a source region graph and a drain region graph;
depositing a metal layer on the residual first photoresist and the source region graph and the drain region graph;
and removing the residual first photoresist, simultaneously stripping the metal layer deposited outside the source region pattern and the drain region pattern region, and performing rapid thermal annealing to form a source electrode and a drain electrode.
3. A method of manufacturing as claimed in claim 2, wherein the substrate material comprises one of: silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, indium phosphide; the first photoresist is electron beam photoresist or ultraviolet photoresist.
4. A producing method according to claim 1, wherein said exposure technique includes one of: electron beam exposure, ion beam exposure, X-ray exposure, holographic exposure, optical contact exposure, optical projection exposure.
5. The production method according to claim 1, wherein the predetermined depth is 1nm to 10 μm.
6. The method of claim 1, wherein the patterning a gate image and forming a gate electrode on the mesa resist mask and the substrate comprises:
spin-coating a second photoresist on the mesa resist mask and the substrate, removing part of the second photoresist by using a micro-nano processing technology, and manufacturing a grid pattern;
depositing a grid metal layer on the residual second photoresist and the grid pattern;
and removing the residual second photoresist and simultaneously stripping the gate metal layer deposited outside the gate pattern region to obtain a gate electrode.
7. The production method according to claim 2 or 6, wherein the manner of deposition includes: thermal evaporation, electron beam evaporation and magnetron sputtering; the material of the metal layer comprises one or more of the following combinations: ti, al, ni, mo, pt, au, pd, W.
8. The manufacturing method according to claim 1, wherein the etching method includes one of: inductively coupled plasma etching, reactive ion beam etching, and wet etching.
9. The production method according to claim 1, wherein the resist comprises one of: photoresist, electron beam resist, organic, dielectric.
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| CN102054891B (en) * | 2010-10-13 | 2012-10-10 | 中国科学院苏州纳米技术与纳米仿生研究所 | Room-temperature terahertz wave detector |
| US8623717B2 (en) * | 2012-06-12 | 2014-01-07 | International Business Machines Corporation | Side-gate defined tunable nanoconstriction in double-gated graphene multilayers |
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