CN112670304B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN112670304B CN112670304B CN202011564155.XA CN202011564155A CN112670304B CN 112670304 B CN112670304 B CN 112670304B CN 202011564155 A CN202011564155 A CN 202011564155A CN 112670304 B CN112670304 B CN 112670304B
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Abstract
The invention discloses an array substrate and a display panel. The array substrate includes: a substrate; the active layer is arranged on the substrate and comprises a plurality of rows of patterned pixel circuit regions, each row of pixel circuit regions comprises a plurality of rows of connected pixel circuit sub-regions, and the pixel circuit sub-regions are used for forming pixel circuits; the conducting layer is provided with a conducting wire, the conducting wire is connected with the end part of the active layer in at least part of the row pixel circuit areas, on the basis that the normal work of the pixel circuit is not influenced, the accumulated electrostatic charge quantity of the active layers corresponding to different row pixel circuit areas can be uniformly distributed, so that the problem of different threshold voltage bias degrees of the driving transistor formed by the active layers corresponding to different row pixel circuit areas can be solved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
During the manufacturing process and the using process of the display panel, the phenomena of static electricity accumulation and static electricity discharge exist. Due to the fact that the accumulated quantity of the electrostatic charges of the pixel units in different columns in the display panel is different, the display brightness of the pixel units in different columns of the display panel is different, and mura phenomenon occurs in the display panel.
Disclosure of Invention
The invention provides an array substrate and a display panel, which are used for improving the antistatic capability of the array substrate and improving the uniformity of the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
a substrate;
the active layer is arranged on the substrate and comprises a plurality of rows of patterned pixel circuit regions, each row of the pixel circuit regions comprises a plurality of rows of connected pixel circuit sub-regions, and the pixel circuit sub-regions are used for forming pixel circuits;
and the conductive layer is provided with a conductive wire which is connected with the end part of the active layer in at least partial column of the pixel circuit area. The end parts of the active layers corresponding to the different rows of pixel circuit regions can be connected through the conducting wires, on the basis that the normal work of the pixel circuit is not influenced, the accumulated electrostatic charge quantity of the active layers corresponding to the different rows of pixel circuit regions can be uniformly distributed, so that the problem that the threshold voltage bias degree of the driving transistor formed by the active layers corresponding to the different rows of pixel circuit regions is different can be solved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
Optionally, the substrate comprises a display region and a non-display region surrounding the display region;
the end part of the active layer in each row of the pixel circuit area is arranged in the non-display area, the conductive wire is arranged in the non-display area, and the conductive wire is connected with the end part of the active layer in each row of the pixel circuit area. The active layer extends to the non-display area, so that a pixel circuit can be formed in the non-display area, the pixel circuit of the non-display area is shielded on the light emitting side, the pixel circuit of the non-display area can be ensured not to be used for displaying of the display panel, and meanwhile, the pixel circuit can be ensured to be completely used for displaying in the display area. In addition, the end parts of the active layers in the pixel circuit regions of each row are connected, so that the electrostatic charge quantity accumulated by the active layers corresponding to the pixel circuit regions of different rows can be uniformly distributed, the problem of different threshold voltage offset degrees of the driving transistors formed by the active layers corresponding to the pixel circuit regions of different rows can be solved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
Optionally, the substrate comprises a display region, a light-transmitting region and a non-display region; the display area at least partially surrounds the light-transmitting area, and the non-display area at least partially surrounds the display area; an active layer in the pixel circuit region opposite to the light transmission region in a column direction has a first end portion and a second end portion in the light transmission region; the active layer in each column of the pixel circuit area is provided with a third end part and a fourth end part in the non-display area;
the conductive wire is arranged in the non-display area and/or the light-transmitting area and is connected with the end part of the active layer in each row of the pixel circuit area. The conductive wires are arranged in the non-display area and/or the light-transmitting area, so that the conductive wires are connected with the end parts of the active layers in each row of pixel circuit areas, the electrostatic charge quantity accumulated by the active layers in all the row of pixel circuit areas is uniformly distributed, the problem that the threshold voltage bias degree of the driving transistors formed by the active layers corresponding to the different row of pixel circuit areas is different can be solved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
Optionally, in the column direction, the first end portion is located on a side of the light-transmitting region close to the third end portion, and the second end portion is located on a side of the light-transmitting region close to the fourth end portion; the conductive lines comprise a first conductive line and a second conductive line; the first conductive line is arranged in the non-display area and is connected with the third end parts of the active layers in all the rows of the pixel circuit areas; the second conductive wire is arranged in the light-transmitting area and is connected with a second end part of the active layer in the pixel circuit area, which is opposite to the light-transmitting area; alternatively, the first and second electrodes may be,
the first conductive wire is connected with the fourth end parts of the active layers in the pixel circuit regions in all columns, and the second conductive wire is connected with the first end part of the active layer in the pixel circuit region opposite to the light transmission region. The end portions of the active layers in all the column pixel circuit regions can be ensured to be connected, and the connection reliability of the end portions of the active layers in different column pixel circuit regions is improved.
Optionally, the active layer further comprises a connection region, and the active layer in the connection region is reused as the conductive layer; the additional increase of the conductive layer can be avoided, and the manufacturing process flow of the display panel is reduced.
Preferably, the active layer doping within the connection region forms the conductive line. Therefore, no additional process is needed when the conductive wire is formed, the manufacturing process flow of the display panel is reduced, and the manufacturing cost of the display panel is reduced.
Optionally, the array substrate further includes:
the metal layer is arranged on one side, far away from the substrate, of the active layer, the metal layer is reused as the conducting layer, and the metal layer is connected with the end portion of the active layer in the pixel circuit area through the through hole.
Optionally, the metal layers include a first metal layer, a second metal layer, and a third metal layer;
the first metal layer is arranged on one side, far away from the substrate, of the active layer, the first metal layer is provided with a grid electrode of a transistor in the pixel circuit, the second metal layer is arranged on one side, far away from the substrate, of the first metal layer, the second metal layer is provided with a polar plate of a capacitor in the pixel circuit, the third metal layer is arranged on one side, far away from the substrate, of the second metal layer, and the third metal layer is provided with a source electrode and a drain electrode of the transistor in the pixel circuit; the additional arrangement of the conducting layer can be avoided, the manufacturing process flow of the display panel is reduced, and the manufacturing cost of the display panel is reduced.
Preferably, the third metal layer is multiplexed as the conductive layer.
Optionally, the array substrate further includes an insulating layer disposed between the adjacent metal layers, and the insulating layer is provided with a via hole; and a conductive substance is filled in the via hole and electrically connected with the conductive wire and the end part of the active layer in the pixel circuit region.
Optionally, the metal layer further comprises a signal line connected to the conductive line for providing a stable potential to the conductive line. The signal line and the conductive wire are arranged in the same layer, so that the connection process flow of the signal line and the conductive wire is simplified.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in the first aspect.
According to the technical scheme of the embodiment of the invention, the conductive layer is arranged in the array substrate and is patterned to form the conductive wire, the end parts of the active layers corresponding to the pixel circuit regions in different rows can be connected through the conductive wire, and the accumulated electrostatic charge quantity of the active layers corresponding to the pixel circuit regions in different rows can be uniformly distributed on the basis of not influencing the normal work of the pixel circuit, so that the problem of different threshold voltage bias degrees of the driving transistors formed by the active layers corresponding to the pixel circuit regions in different rows can be solved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
Drawings
Fig. 1 is a schematic partial structure diagram of an active layer of a display panel provided in the prior art;
fig. 2 is a schematic structural diagram of a display panel provided in the prior art;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic partial structural diagram of an active layer according to an embodiment of the present invention;
FIG. 5 is a partially enlarged view of a sub-area A of the pixel circuit of FIG. 3;
fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 7 is a schematic view of a partial structure of another active layer according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 10 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the invention;
fig. 11 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 12 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
In the manufacturing process and the using process of the display panel, static electricity generated by the environment can be accumulated and released in the display panel, and the display panel is damaged. The display panel comprises a plurality of rows and columns of pixel units, and the pixel units comprise active layers for forming channels, source regions and drain regions of transistors in the pixel units. Fig. 1 is a schematic partial structure diagram of an active layer of a display panel according to the prior art. As shown in fig. 1, the active layer 10 is patterned to form active layers 11 corresponding to pixel units in multiple rows and multiple columns, and as shown in fig. 1, the active layers 11 corresponding to pixel units in one column are connected with each other, and the active layers 11 corresponding to pixel units in different columns are disconnected. When the number of the pixel units in different columns in the display panel is different, the amount of the electrostatic charges accumulated between the pixel units in different columns is different, so that the threshold voltage bias degrees of the driving transistors in the pixel units in different columns are different, and when the display panel displays, the display brightness of the pixel units in different columns is different, so that the mura phenomenon of the display panel occurs. Fig. 2 is a schematic structural diagram of a display panel provided in the prior art. As shown in fig. 2, the display panel includes a display area 101 and a non-display area 102, an Electro-Static discharge (ESD) circuit 103 is disposed in the non-display area 102, and the ESD circuit 103 can improve the electrostatic protection capability of the display panel. But the mura phenomenon of the display panel caused by different amounts of accumulated electrostatic charges between different columns of pixel units cannot be solved.
In view of the above technical problems, an embodiment of the present invention provides an array substrate. Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of a portion of an active layer according to an embodiment of the present invention. As shown in fig. 3 and 4, the array substrate includes: a substrate 110, an active layer 120, and a conductive layer 130; specifically, the active layer 120 is disposed on the substrate 110, the active layer 120 includes a plurality of rows of patterned pixel circuit regions 111, each row of pixel circuit regions 111 includes a plurality of rows of connected pixel circuit sub-regions a, and the pixel circuit sub-regions a are used for forming pixel circuits; the conductive layer 130 is provided with a conductive line 131, and the conductive line 131 is connected to an end portion of the active layer 120 in at least a part of the column pixel circuit region 111.
The active layer 110 may be P-silicon, and channels, source regions and drain regions of transistors in pixel circuits in rows and columns may be formed through patterning and doping processes. Each column of pixel circuit regions 111 includes a plurality of rows of pixel circuit sub-regions a that may form an active layer of transistors in the pixel circuits and a portion of the connections of the transistors in the pixel circuits for subsequent formation of the plurality of rows of pixel circuits. Exemplarily, fig. 5 is a partially enlarged schematic diagram of one pixel circuit sub-area a of fig. 3. As shown in fig. 5, the pixel circuit sub-area a may form active layers of transistors corresponding to the pixel circuit of 7T1C, namely, a first transistor active layer P1, a second transistor active layer P2, a third transistor active layer P3, a fourth transistor active layer P4, a fifth transistor active layer P5, a sixth transistor active layer P6 and a seventh transistor active layer P7. The active layer of each transistor may form a corresponding transistor in the array substrate and form a pixel circuit according to a connection manner of the transistors. Since the active layers 120 of the plurality of rows of pixel circuit sub-areas a in each column of the pixel circuit area 111 are connected to each other, the active layer 120 corresponding to each column of the pixel circuit area 111 has an end portion 121. The conductive layer 130 is arranged in the array substrate, the conductive layer 130 is patterned to form the conductive line 131, the end portions 121 of the active layers 120 corresponding to the pixel circuit regions 111 in different rows can be connected through the conductive line 131, and on the basis that normal operation of the pixel circuits is not affected, electrostatic charge amounts accumulated in the active layers 120 corresponding to the pixel circuit regions 111 in different rows can be uniformly distributed, so that the problem that threshold voltage bias degrees of driving transistors formed by the active layers 120 corresponding to the pixel circuit regions 111 in different rows are different can be solved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
With continued reference to fig. 3 and 4, the substrate 110 includes a display region 112 and a non-display region 113 surrounding the display region 112; the end portion 121 of the active layer 120 in each row of the pixel circuit region 111 is disposed in the non-display region 121, the conductive line 131 is disposed in the non-display region 121, and the conductive line 131 is connected to the end portion 121 of the active layer 120 in each row of the pixel circuit region 111.
Specifically, the active layer 120 is disposed within the display region 112 of the substrate 110 for forming a pixel circuit. The non-display area 113 is disposed around the display area 112, the active layer 120 in the pixel circuit area 111 may extend to the non-display area 113 to form at least one row of pixel circuit sub-area a for forming pixel circuits (e.g., dummy pixel circuits) in the non-display area 113, where the pixel circuit sub-area a formed in the display area 112 by the active layer 120 in each column of the pixel circuit area 111 is used to form a normal light emitting pixel circuit, the pixel circuit sub-area a formed in the non-display area 113 is used to form dummy pixel circuits, and the pixel circuits in the non-display area 113 are shielded on the light emitting side of the display panel to ensure that the pixel circuits in the non-display area 113 are not used for displaying the display panel, and to ensure that the pixel circuits can make the display area 112 fully used for displaying. In general, the periphery of the non-display region 113 is in a step form, so that the number of pixel circuit sub-regions a in each column of the pixel circuit region 111 is different, resulting in different accumulation of the amount of electrostatic charge in the active layer 120 in different columns of the pixel circuit region 111. At this time, the end portion 121 of the active layer 120 corresponding to each column of the pixel circuit region 111 is disposed in the non-display region 113, and the end portions 121 of the active layers 120 of the pixel circuit regions 111 in different columns of the non-display region 113 are connected by the conductive wire 131 of the conductive layer 130, so that the amount of electrostatic charges accumulated in the active layers 120 corresponding to the pixel circuit regions 111 in different columns can be uniformly distributed without affecting normal display of the display panel, thereby improving the problem of different threshold voltage bias degrees of the driving transistors formed in the active layers 120 corresponding to the pixel circuit regions 111 in different columns, improving the electrostatic protection capability of the display panel, improving the mura phenomenon of the display panel, and improving the display uniformity of the display panel.
Exemplarily, as shown in fig. 4 and 5, when the end portion 121 of the active layer 120 in the pixel circuit region 111 of multiple columns is disposed in the non-display region 113, and the end portion 121 of the active layer 120 in the pixel circuit region 111 is one end of the seventh transistor active layer P7, the conductive lines 131 may be disposed to be respectively connected to the seventh transistor active layer P7 in the pixel circuit sub-region a of the first row in the pixel circuit region 111 of different columns, so as to achieve the connection of the end portion 121 of the active layer 120 in the pixel circuit region 111 of different columns.
It should be noted that fig. 4 merely exemplarily shows that the conductive line 131 is connected to the end portion 121 of the active layer 120 in the first row of pixel circuit sub-area a in the different column pixel circuit area 111. The first row of pixel circuit sub-regions a in the different column of pixel circuit regions 111 may be different row of pixel circuit sub-regions a. In other embodiments, the end portion 121 of the active layer 120 in the pixel circuit region 111 may also be an end of the fourth transistor active layer P4, and the end portion 121 of the active layer 120 in the different column pixel circuit regions 111 is connected by disposing the conductive line 131 to connect with the fourth transistor active layer P4 in the last row of pixel circuit sub-region a in the different column pixel circuit regions 111.
Fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 6, the substrate 110 includes a display region 112, a light-transmitting region 114, and a non-display region 113; the display area 112 at least partially surrounds the light-transmitting area 114, and the non-display area 113 at least partially surrounds the display area 112; the active layer 120 in the pixel circuit region 111 opposite to the light transmission region 114 in the column direction X has a first end 1211 and a second end 1212 in the light transmission region 114; the active layer 120 in each column of the pixel circuit region 111 has a third end portion 1213 and a fourth end portion 1214 in the non-display region 113; the conductive line 131 is disposed in the non-display region 113 and/or the light-transmitting region 114, and the conductive line 131 is connected to the end portion 121 of the active layer 120 in each column of the pixel circuit region 111.
Specifically, the substrate 110 may further include a light-transmitting region 114, the display region 112 may be disposed around the light-transmitting region 114, and the light transmittance of the light-transmitting region 114 is relatively high, which may be used to place a photosensitive element, such as a camera. The pixel circuit may not be disposed in the light-transmitting region 114 to ensure light transmittance of the light-transmitting region 114. The light-transmitting region 114 may be provided with a display device as a display region, or may be provided with only a photosensitive element as a non-display region. Since no pixel circuit is disposed in the light transmissive region 114, the active layer 120 of the pixel circuit region 111 in the same column has an end portion 121 at the edge of the light transmissive region 114, and the end portion 121 of the active layer 120 of the pixel circuit region 111 in the same column is increased. Optionally, the end 121 of the light-transmitting region 114 close to the first row of pixel circuit sub-regions a is a first end 1211, and the end 121 of the light-transmitting region 114 close to the last row of pixel circuit sub-regions a is a second end 1212. The active layer 120 of the pixel circuit region 111 in the same column may extend from the display region 112 to the transparent region 114 to form at least one row of pixel circuit sub-regions a for forming pixel circuits (e.g., dummy pixel circuits of the transparent region 114) in the transparent region 114, and shield the pixel circuits of the transparent region 114 on the light-emitting side of the display panel, so as to ensure that the pixel circuits of the transparent region 114 are not used for displaying the display panel, and ensure that the pixel circuits can make the display region 112 fully used for displaying. When the edge of the light transmissive region 114 is located in the pixel circuit region 111 of the display region 112, the active layer 120 in the pixel circuit region 111 is located in the pixel circuit sub-regions a of different rows at the first end 1211 and the second end 1212 of the light transmissive region 114. At this time, the power layers 120 in the pixel circuit regions 111 in the columns corresponding to the light transmitting regions 114 include four end portions, and the power layers 120 in the pixel circuit regions 111 in the other columns include two end portions. The conductive line 131 is arranged in the non-display area 113, so that the third end portion 1213 and/or the fourth end portion 1214 of the different pixel circuit areas 113 are connected, and/or the conductive line 131 is arranged in the light transmission area 114, so that the first end portion 1211 and/or the second end portion 1212 of the different pixel circuit areas 113 are connected, and the end portions 121 of the active layers 120 of the different pixel circuit areas 111 can be connected.
Exemplarily, fig. 7 is a schematic view of a partial structure of another active layer provided in an embodiment of the present invention. As shown in fig. 4, 6 and 7, when the light transmissive region 114 has a shape with a step at the edge, the first end 1211 and the second end 1212 of the active layer 120 of the pixel circuit region 111 in the column corresponding to the light transmissive region 114 are located in the pixel circuit sub-regions a in different rows. When the first end portion 1211 of the light-transmitting area 114 close to the pixel circuit sub-area a in the first row is one end of the fourth transistor active layer P4 in the pixel circuit sub-area a along the column direction X (specifically, as shown in fig. 6), the conductive wires 131 may be disposed to be respectively connected to the fourth transistor active layers P4 of the active layers 120 in different column pixel circuit areas 111 in the light-transmitting area 114, so as to achieve connection of the first end portions 1211 of the active layers 120 of the different column pixel circuit areas 111.
It should be noted that fig. 6 exemplarily shows that the conductive lines 131 are connected to the first end 1211, the second end 1212, and the third end 1213 of the active layer 120 in each column of the pixel circuit region 111. In other embodiments, the conductive line 131 may be connected to any end portion in the active layer 120 within a different column pixel circuit region 111. Furthermore, as shown in fig. 7, when the first end portion 1211 of the active layer 120 is one end of the fourth transistor active layer P4 in the pixel circuit sub-area a, the seventh transistor active layer P7 disposed in the same row as the fourth transistor active layer P4 can be simultaneously connected to the conductive line 131, so as to improve the connection reliability of the first end portion 1211 of the active layer 120 in the pixel circuit areas 111 of different columns. In addition, fig. 7 only exemplarily shows that the conductive line 131 is connected to the first end 1211 of the power layer 120 of the pixel circuit region 111 of the column corresponding to the light transmission region 114. In other embodiments, when the second end portion 1212 of the light transmissive region 114 near the pixel circuit sub-region a in the last row is the seventh transistor active layer P7, the conductive wires 131 may be disposed to be connected to the seventh transistor active layer P7 of the active layer 120 in different pixel circuit regions 111 in the light transmissive region 114, so as to connect the second end portions 1212 of the active layers 120 in different pixel circuit regions 111.
Fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the invention. As shown in fig. 8, along the column direction X, the first end 1211 is located on a side of the light-transmitting region 114 close to the third end 1213, and the second end 1212 is located on a side of the light-transmitting region 1213 close to the fourth end 1214; conductive line 131 includes a first conductive line 1311 and a second conductive line 1312; the first conductive line 1311 is disposed in the non-display region 113, and the first conductive line 1311 is connected to the third end portions 1213 of the active layers 120 in all the column pixel circuit regions 111; the second conductive line 1312 is disposed in the light transmissive region 114, and the second conductive line 1312 is connected to the second end portion 1212 of the active layer 120 in the pixel circuit region 111 opposite to the light transmissive region 114.
Specifically, fig. 8 exemplarily shows that the conductive line 131 is connected to the end portion 121 of the active layer 120 within a part of the pixel circuit region 111. The first end 1211 and the second end 1212 are symmetrically disposed. When the first conductive lines 1311 are disposed in the non-display region 113, the first conductive lines 1311 may be connected to the third ends 1213 of the active layers 120 in all the column pixel circuit regions 111, so that the active layers 120 in all the column pixel circuit regions 111 are connected. The first end 1211 and the second end 1212 are disconnected, and at this time, the second conductive line 1312 is disposed to be connected to the second end 1212 of the active layer 120 in the pixel circuit region 111 opposite to the light transmission region 114, so that all the pixel circuit sub-regions a in the same row in the pixel circuit region 111 corresponding to the first end 1211 and the second end 1212 are connected, and thus all the pixel circuit sub-regions a are connected, and on the basis of not affecting the normal operation of the pixel circuit, the uniformity of the electrostatic charge amount distribution of the active layer 120 is further improved, so that the problem of different threshold voltage bias degrees of the driving transistors formed in the active layers 120 corresponding to the pixel circuit regions 111 in different columns is further improved, the electrostatic protection capability of the display panel is improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved.
Fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the invention. As shown in fig. 9, the first conductive lines 1311 are connected to the fourth end portions 1214 of the active layers 120 in all the column pixel circuit regions 111, and the second conductive lines 1312 are connected to the first end portions 1211 of the active layers 120 in the pixel circuit regions 111 opposite to the light transmission regions 114.
Specifically, unlike fig. 8, when the first conductive lines 1311 are disposed in the non-display area 113, the first conductive lines may be connected to the fourth end portions 1214 of the active layers 120 in all the column pixel circuit areas 111, so as to connect the active layers 120 in all the column pixel circuit areas 111. The first end portion 1211 and the second end portion 1212 are disconnected, and at this time, the second conductive line 1312 is disposed to be connected to the first end portion 1211 of the active layer 120 in the pixel circuit region 111 opposite to the light transmission region 114, so that all the row pixel circuit sub-regions a in the same column pixel circuit region 111 corresponding to the first end portion 1211 and the second end portion 1212 are connected, and thus all the pixel circuit sub-regions a can be connected.
On the basis of the above technical solutions, the active layer 120 further includes a connection region, and the active layer 120 in the connection region is reused as the conductive layer 130.
Specifically, the conductive layer 130 may be disposed at the same layer as the active layer 120, and when patterning the active layer 120, the active layer 120 may be patterned according to the position of the conductive layer 130 while forming the active layer 120 in the pixel circuit region 111 and the active layer 120 in the connection region. And the conductive line 131 is formed through the active layer 120 in the connection region for connecting the end portions 121 of the pixel circuit regions 111 in different rows, so that the additional increase of the conductive layer 130 can be avoided, and the manufacturing process flow of the display panel is reduced.
Preferably, the active layer 120 in the connection region is doped to form a conductive line 131. The active layer in the pixel circuit region 111 may form an active layer of a transistor and a partial connection relationship of the transistor by doping, and the conductive line 131 may be formed simultaneously to the active layer 120 in the connection region by doping while the active layer of the transistor and the partial connection relationship of the transistor are formed by doping. Therefore, no additional process is required to be added when the conductive line 131 is formed, the manufacturing process flow of the display panel is reduced, and the manufacturing cost of the display panel is reduced.
On the basis of the above technical solutions, the array substrate further includes:
and the metal layer is arranged on one side of the active layer far away from the substrate and is reused as a conductive layer, and the metal layer is connected with the end part of the active layer in the pixel circuit area through the through hole.
In particular, the metal layer may be any metal layer that forms a transistor. Illustratively, the metal layer may be at least one of a gate metal layer, a capacitor plate metal layer, and a source drain metal layer of the transistor. In the process of forming the array substrate, transistors, capacitors and other devices required by pixel circuits can be formed by arranging the metal layers. The metal layer is a conductive layer, and before the metal layer is formed, an insulating layer is further arranged on the active layer to avoid short circuit between the metal layer and the active layer. The metal layer is reused as the conductive layer, the conductive line is formed, then the through hole is formed in the insulating layer, the metal layer can be connected with the end portion of the active layer through the through hole, and the end portion of the active layer corresponding to the pixel circuit regions in different columns can be connected through the conductive line.
Fig. 10 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 10, the metal layers include a first metal layer 140, a second metal layer 150, and a third metal layer 160; the first metal layer 140 is disposed on a side of the active layer 120 away from the substrate 110, the first metal layer 140 is disposed on a gate of a transistor in a pixel circuit, the second metal layer 150 is disposed on a side of the first metal layer 140 away from the substrate 110, the second metal layer 150 is disposed on a plate of a capacitor in the pixel circuit, the third metal layer 160 is disposed on a side of the second metal layer 150 away from the substrate 110, and the third metal layer 160 is disposed on a source and a drain of the transistor in the pixel circuit.
Specifically, the first metal layer 140 may be used to form a gate electrode of a transistor, and may also be used to form a scan signal line on the array substrate. The second metal layer 150 may be used to form a plate of a capacitor. The third metal layer 160 may be used to form a source and a drain of a transistor, and may also be used to form a data signal line and a power signal line on the array substrate. The metal layer has conductivity. Any film layer in the first metal layer 140, the second metal layer 150, and the third metal layer 160 can be reused as the conductive layer 130, so that additional arrangement of the conductive layer 130 can be avoided, the manufacturing process flow of the display panel is reduced, and the manufacturing cost of the display panel is reduced.
Preferably, the third metal layer 160 is multiplexed into the conductive layer 130.
Specifically, in fig. 9, the third metal layer 160 is reused as the conductive layer 130, that is, the third metal layer 160 is also used to form the conductive line 131, and the conductive line 131 is connected to the end portion 121 of the active layer 120, so that the conductive line 131 can connect the end portions 121 of the active layer 120 corresponding to different pixel circuit regions in columns.
With continued reference to fig. 10, the array substrate further includes an insulating layer 170 disposed between adjacent metal layers, and the insulating layer 170 has a via 171 disposed therein; the via hole 171 is filled with a conductive material electrically connecting the conductive line 131 and the end portion 121 of the active layer 120 in the pixel circuit region.
Specifically, the insulating layer 170 is disposed between different metal layers, and the insulating layer 170 is also disposed between the metal layers and the active layer 120. When the third metal layer 160 is multiplexed as the conductive layer 130, the conductive line 130 is located at the third metal layer 160. Due to the different patterning shapes of the different metal layers, when the third metal layer 160 is multiplexed such that the vertical projection of the portion of the conductive layer 130 on the substrate 110 does not overlap the vertical projection of the first metal layer 140 and the second metal layer 150 on the substrate 110, as shown in fig. 10, the conductive line 131 may be connected to the end portion of the active layer 120 in the pixel circuit region by providing a via 171 on the insulating layer 170, the vertical projection of both ends of the via 171 on the substrate 110 overlapping the conductive line 131 in the third metal layer 160 and the vertical projection of the end portion of the active layer 120 on the substrate 110, respectively, and filling the via 171 with a conductive material. Fig. 11 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention. As shown in fig. 11, when the third metal layer 160 is multiplexed into a state where the vertical projection of the portion of the conductive layer 130 on the substrate 110 overlaps with the vertical projection of the first metal layer 140 on the substrate 110, and does not overlap with the vertical projection of the second metal layer 150 on the substrate 110, the conductive line 131 in the third metal layer 160 may be connected to the first metal layer 140 by providing the via 171 on the insulating layer 170 between the third metal layer 160 and the first metal layer 140 and filling the via 171, and then the first metal layer 140 may be connected to the end portion of the active layer 120 by providing the via 171 on the insulating layer 170 between the first metal layer 140 and the end portion of the active layer 120, so that the connection of the conductive line 131 to the end portion of the active layer 120 in the pixel circuit region may be achieved. Fig. 12 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention. As shown in fig. 12, when the third metal layer 160 is multiplexed such that the vertical projection of the portion of the conductive layer 130 on the substrate 110 does not overlap with the vertical projection of the first metal layer 140 on the substrate 110 and overlaps with the vertical projection of the second metal layer 150 on the substrate 110, a via 171 may be provided on the insulating layer 170 between the third metal layer 160 and the second metal layer 150, and a conductive material may be filled in the via 171 to connect the conductive line 131 in the third metal layer 160 with the second metal layer 150, and then the second metal layer 150 may be connected with the end portion of the active layer 120 by providing the via 171 on the insulating layer 170 between the second metal layer 150 and the end portion of the active layer 120, so that the conductive line 131 may be connected with the end portion of the active layer 120 in the pixel circuit region.
It should be noted that fig. 10 to fig. 12 only exemplarily show that the third metal layer 160 is multiplexed as the conductive layer 130, in other embodiments, the first metal 140 or the second metal layer 150 may also be multiplexed as the conductive layer 130, and the conductive line 131 is formed, and the conductive line 131 may also be implemented to connect the end portions of the active layers 120 corresponding to the pixel circuit regions in different columns.
On the basis of the technical schemes, the metal layer further comprises a signal line, and the signal line is connected with the conductive line and used for providing stable potential for the conductive line.
Specifically, the metal layers may also provide signal lines, for example, the first metal layer may provide a scan signal line, the second metal layer may provide an initialization signal line, the third metal layer may provide a data signal line, a power signal line, and the like. The signal wire with the fixed potential through the metal layer is connected with the conducting wire, the fixed potential can be provided for the conducting wire through the signal wire, and therefore an electrostatic discharge path can be provided for the conducting wire, the electrostatic protection capability of the display panel is further improved, the mura phenomenon of the display panel is improved, and the display uniformity of the display panel is improved. Illustratively, when the third metal layer is multiplexed as a conductive layer, a fixed potential may be supplied to the conductive line by connecting the power signal line of the third metal layer with the conductive line of the third metal layer. Meanwhile, the power signal line and the conducting wire are arranged on the same layer, so that the connection process flow of the power signal line and the conducting wire is simplified.
The embodiment of the invention also provides a display panel. Fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 13, the display panel 200 includes an array substrate 201 according to any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (9)
1. An array substrate, comprising:
a substrate;
the active layer is arranged on the substrate and comprises a plurality of rows of patterned pixel circuit regions, each row of the pixel circuit regions comprises a plurality of rows of connected pixel circuit sub-regions, and the pixel circuit sub-regions are used for forming pixel circuits;
a conductive layer provided with a conductive line connected to an end portion of the active layer in at least a part of the columns of the pixel circuit region;
the substrate comprises a display area and a non-display area surrounding the display area;
the end part of the active layer in each row of the pixel circuit area is arranged in the non-display area, the conductive wire is arranged in the non-display area, and the conductive wire is connected with the end part of the active layer in each row of the pixel circuit area;
the substrate comprises a display area, a light-transmitting area and a non-display area; the display area at least partially surrounds the transmissive area, and the non-display area at least partially surrounds the display area.
2. The array substrate of claim 1, wherein the active layer in the pixel circuit region opposite to the light-transmitting region in a column direction has a first end and a second end in the light-transmitting region; the active layer in each column of the pixel circuit area is provided with a third end part and a fourth end part in the non-display area;
the conductive wire is arranged in the non-display area and/or the light-transmitting area and is connected with the end part of the active layer in each row of the pixel circuit area.
3. The array substrate of claim 2, wherein the first end portion is located on a side of the light-transmitting region close to the third end portion, and the second end portion is located on a side of the light-transmitting region close to the fourth end portion; the conductive line comprises a first conductive line and a second conductive line; the first conductive line is arranged in the non-display area and is connected with the third end parts of the active layers in all the rows of the pixel circuit areas; the second conductive wire is arranged in the light-transmitting area and is connected with a second end part of the active layer in the pixel circuit area, which is opposite to the light-transmitting area; alternatively, the first and second electrodes may be,
the first conducting wire is connected with the fourth end parts of the active layers in the pixel circuit regions in all columns, and the second conducting wire is connected with the first end part of the active layer in the pixel circuit region opposite to the light transmission region.
4. The array substrate of any of claims 1-3, wherein the active layer further comprises a connection region, and the active layer in the connection region is reused as the conductive layer;
active layer doping within the connection region forms the conductive line.
5. The array substrate of any one of claims 1-3, further comprising:
the metal layer is arranged on one side, far away from the substrate, of the active layer, the metal layer is reused as the conducting layer, and the metal layer is connected with the end portion of the active layer in the pixel circuit area through the through hole.
6. The array substrate of claim 5, wherein the metal layer comprises a first metal layer, a second metal layer, and a third metal layer;
the first metal layer is arranged on one side, far away from the substrate, of the active layer, the first metal layer is provided with a grid electrode of a transistor in the pixel circuit, the second metal layer is arranged on one side, far away from the substrate, of the first metal layer, the second metal layer is provided with a polar plate of a capacitor in the pixel circuit, the third metal layer is arranged on one side, far away from the substrate, of the second metal layer, and the third metal layer is provided with a source electrode and a drain electrode of the transistor in the pixel circuit;
the third metal layer is reused as the conductive layer.
7. The array substrate of claim 6, further comprising an insulating layer disposed between adjacent metal layers, wherein the insulating layer has a via disposed therein; and a conductive substance is filled in the via hole and electrically connected with the conductive wire and the end part of the active layer in the pixel circuit region.
8. The array substrate of claim 5, wherein the metal layer further comprises a signal line connected to the conductive line for providing a stable potential to the conductive line.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
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| CN113394236B (en) * | 2021-05-28 | 2024-04-09 | 武汉天马微电子有限公司 | Display panel and display device |
| CN114334915A (en) * | 2021-12-27 | 2022-04-12 | 昆山国显光电有限公司 | Display panel and display device |
| CN114613825A (en) * | 2022-03-11 | 2022-06-10 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108037626A (en) * | 2017-11-29 | 2018-05-15 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| CN111402716A (en) * | 2020-03-27 | 2020-07-10 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108037626A (en) * | 2017-11-29 | 2018-05-15 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| CN111402716A (en) * | 2020-03-27 | 2020-07-10 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
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