CN112670269A - Stepped word line structure and preparation method thereof - Google Patents
Stepped word line structure and preparation method thereof Download PDFInfo
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- CN112670269A CN112670269A CN201910981688.9A CN201910981688A CN112670269A CN 112670269 A CN112670269 A CN 112670269A CN 201910981688 A CN201910981688 A CN 201910981688A CN 112670269 A CN112670269 A CN 112670269A
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Abstract
The invention provides a step-type word line structure and a preparation method thereof. The ladder-type word line structure can reduce the resistance of the word line structure and simultaneously can avoid the GIDL effect.
Description
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a stepped word line structure and a preparation method thereof.
Background
A Dynamic Random Access Memory (DRAM) is a commonly used semiconductor Memory device, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor and a transistor. The grid electrode of the transistor is connected with a word line, the drain electrode or the source electrode of the transistor is connected with a bit line or a capacitor, a voltage information number on the word line can control the transistor to be turned on or turned off, and then data information in the capacitor is read through the bit line or written into the capacitor through the bit line for storage. In order to reduce the device size, criss-cross word lines and bit lines are usually disposed in the active area of the array.
For the word line structure, the surface thereof is usually covered with a thicker insulating layer to reduce the Leakage current and improve the GIDL (Gate-induced Drain Leakage) effect. However, the insulating layer also occupies a larger space of the word line, and the thickness of the word line is reduced, so that the resistance of the word line is increased, and the control capability of the gate to the channel is reduced, and the driving current capability of the transistor is reduced.
Therefore, how to reduce the resistance of the word line and improve the control capability of the gate to the channel while avoiding the GIDL effect is a technical problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a stepped word line structure and a preparation method thereof, which can reduce the resistance of the word line structure and simultaneously avoid the GIDL effect.
In order to solve the above problems, the present invention provides a step-type word line structure, which includes a conductive layer, wherein a top end of the conductive layer is in a step-type configuration with a high middle and two low sides.
Furthermore, the top ends of the conducting layers are arranged in an axisymmetric manner by taking the center line of the conducting layers as an axis.
Furthermore, the step-type word line structure further comprises a barrier layer arranged on the outer surface of the conducting layer, and the highest point of the top end of the conducting layer is higher than the upper end face of the barrier layer.
Further, the lowest point of the top end of the conducting layer is higher than the upper end face of the barrier layer.
Further, the step-type word line structure further comprises a gate insulating layer, and the gate insulating layer is arranged on the outer surface of the blocking layer.
Further, the upper end surface of the gate insulating layer is higher than the highest point of the top end of the conductive layer.
The invention also provides a preparation method of the stepped word line structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a plurality of grooves which are arranged at intervals; filling a conductive material in the groove to form a conductive layer, wherein the top end of the conductive layer is lower than the upper edge of the groove; and etching the conducting layer for multiple times to enable the top end of the conducting layer to be in a step-like configuration with a high middle and two low sides.
Further, the preparation method also comprises the following steps: forming a gate insulating layer and a barrier layer on the side wall of the trench before forming the conductive layer; and filling a conductive material in the grid barrier layer to form the conductive layer.
Further, the method for enabling the top end of the conducting layer to be in a step-shaped configuration with a high middle and two low sides comprises the following steps: and etching the conducting layer from the edge of the top end of the conducting layer to the center of the top end of the conducting layer for multiple times along the direction vertical to the top end of the conducting layer, so that the top end of the conducting layer is in a step-shaped configuration with a high middle and two low sides.
Further, the method for enabling the top end of the conducting layer to be in a step-shaped configuration with a high middle and two low sides comprises the following steps: forming a mask layer on the part, which is not filled with the conductive layer, of the groove, wherein the mask layer covers the top end of the conductive layer; and imaging the mask layer from the edge of the top end of the conductive layer for multiple times, and etching the conductive layer after imaging the mask layer every time to enable the top end of the conductive layer to be in a step-type configuration with a high middle and two low sides.
Further, the method for enabling the top end of the conducting layer to be in a step-shaped configuration with a high middle and two low sides comprises the following steps: forming a plurality of mask layers on the part, not filled by the conducting layer, of the groove along the side wall of the groove, wherein the plurality of mask layers are sequentially arranged along the direction from the edge of the top end of the conducting layer to the center; and removing the mask layers from the outermost mask layer in sequence, and etching the conducting layer after removing each mask layer, so that the top end of the conducting layer is in a step-type configuration with a high middle and two low sides.
Further, four mask layers are formed along the side wall of the groove at the part, not filled by the conducting layer, of the groove.
Further, the mask layer is made of nitride, carbon, boron-phosphorus-silicon glass and ethyl orthosilicate in sequence in the direction from the edge to the center of the top end of the conducting layer.
Compared with the prior word line structure with a flat top, the stepped word line structure has the advantages that the top of the stepped word line structure is higher than that of the prior word line structure, the area of the word line structure is increased, the resistance of the word line structure is reduced, the control capability of a grid electrode on a channel is improved, and the driving current capability of a transistor is improved. Although the highest point of the top end of the ladder-type word line structure is far from the drain electrode in the direction perpendicular to the top end of the word line structure (such as the Y direction in fig. 1), the distance between the highest point of the top end and the drain electrode in the direction parallel to the top end of the word line structure (such as the X direction in fig. 1) is not greatly reduced, so that the leakage current is not generated. That is to say, the ladder-type word line structure of the invention can reduce the resistance of the word line structure and simultaneously can avoid the GIDL effect.
Drawings
FIG. 1 is a schematic diagram of a ladder word line structure according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another embodiment of the stepped wordline structure of the present invention;
FIG. 3 is a schematic diagram of a ladder word line structure according to yet another embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating steps of a method for fabricating a ladder word line structure according to one embodiment of the present invention;
fig. 5A to 5O are process flow diagrams of an embodiment of a method for fabricating the staircase word line structure.
Detailed Description
The following describes in detail embodiments of the step word line structure and the method for fabricating the same according to the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a ladder word line structure according to an embodiment of the present invention. Referring to fig. 1, the step-shaped word line structure includes a conductive layer 10, and a top end of the conductive layer 10 is in a step-shaped configuration with a high middle and two low sides.
In the present embodiment, the top end of the conductive layer 10 has four steps in the direction from the edge to the center, and the heights of the steps in the direction from the edge to the center of the top end of the conductive layer 10 are sequentially increased, so that a stepped configuration having a high middle and two low sides is formed. In other embodiments of the present invention, the number of steps can be set according to actual conditions. For example, please refer to fig. 2, which is a schematic structural diagram illustrating another embodiment of the staircase word line structure according to the present invention, wherein the top end of the conductive layer 10 has no step configuration, that is, the top end of the conductive layer 10 is divided into a central region a1 and an edge region a2 surrounding the central region a1, and the height of the conductive layer in the central region a1 is greater than that of the conductive layer in the edge region a 2. Referring to fig. 3, which is a schematic structural diagram of a further embodiment of the staircase word line structure according to the present invention, in the embodiment, the top end of the conductive layer 10 has three steps from the edge to the center, that is, the top end of the conductive layer 10 is divided into a central region a1, a middle region a2 and an edge region A3 which sequentially surround the central region a1, and the height of the conductive layer 10 decreases sequentially from the central region a1 to the edge region A3.
Referring to fig. 1, a dotted line B is shown schematically in fig. 1 to show a position of a top end of a flat-type word line structure in the prior art, and compared with the top end of the conventional word line structure in a flat configuration, the top end of the step-type word line structure of the present invention is higher than the top end of the conventional word line structure. Although the highest point of the top end of the ladder-type word line structure is far from the drain electrode in the direction perpendicular to the top end of the word line structure (such as the Y direction in fig. 1), the distance between the highest point of the top end and the drain electrode in the direction parallel to the top end of the word line structure (such as the X direction in fig. 1) is not greatly reduced, so that the leakage current is not generated. That is to say, the ladder-type word line structure of the invention can reduce the resistance of the word line structure and simultaneously can avoid the GIDL effect.
Preferably, in the present embodiment, the top ends of the conductive layer 10 are disposed to be axisymmetrical with respect to a center line of the conductive layer 10. The conductive layer 10 material includes, but is not limited to, a metal or metal alloy, such as tungsten, aluminum, copper, and alloys thereof.
Further, the step-type word line structure further includes a barrier layer 11 disposed on an outer surface of the conductive layer 10. The barrier layer 11 includes, but is not limited to, a titanium nitride layer or a tantalum nitride layer. In this embodiment, the lowest point of the top end of the conductive layer 10 is higher than the upper end surface of the barrier layer 11, and in another embodiment of the present invention, the highest point of the top end of the conductive layer 10 is higher than the upper end surface of the barrier layer 11, and the lowest point of the top end of the conductive layer 10 is lower than the upper end surface of the barrier layer 11.
Further, the step word line structure further includes a gate insulating layer 12, and the gate insulating layer 12 is disposed on an outer surface of the barrier layer 11. The gate insulating layer 12 includes, but is not limited to, a silicon oxide insulating layer. Further, the upper end surface of the gate insulating layer 12 is higher than the highest point of the top end of the conductive layer 10. In this particular manner, the gate insulating layer 12 may cover the sidewalls of the trench 20 forming the stepped word line structure.
The invention also provides a preparation method of the ladder-shaped word line structure. FIG. 4 is a schematic step diagram of a method for fabricating a ladder word line structure according to an embodiment of the present invention. Referring to fig. 4, the method for manufacturing the ladder type word line structure includes the following steps: step S40, providing a substrate, wherein the substrate is provided with a plurality of grooves which are arranged at intervals; step S41, filling a conductive material in the groove to form a conductive layer, wherein the top end of the conductive layer is lower than the upper edge of the groove; and step S42, etching the conducting layer for multiple times to enable the top end of the conducting layer to be in a step-like configuration with a high middle and two low sides.
Fig. 5A to 5O are process flow diagrams of an embodiment of a method for fabricating the staircase word line structure. In the present embodiment, the formation of the four-stage step will be described as an example.
Referring to step S40 and fig. 5A, a substrate 200 is provided, in which the substrate 200 has a plurality of trenches 210 arranged at intervals.
The substrate 200 includes, but is not limited to, a Silicon crystal or germanium crystal, a Silicon On Insulator (SOI) structure or an epitaxial layer on Silicon structure, a compound semiconductor (e.g., Silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof). In this step, a mask may be formed on the substrate 200, and the trench 210 may be formed on the substrate 200 using a photolithography and etching process.
Further, when the trench 210 is formed, an oxide isolation layer 250 is also formed on the surface of the substrate 200, and the oxide isolation layer 250 does not cover the inner surface of the trench 210, but only covers the upper surface of the substrate 200. The oxide isolation layer 250 may protect the upper surface of the substrate 200 from being etched in a subsequent process.
Referring to step S41 and fig. 5B to 5E, the trench 210 is filled with a conductive material to form a conductive layer 220, and a top end of the conductive layer 220 is lower than an upper edge of the trench 210.
Further, before forming the conductive layer 220, a step of forming a gate insulating layer 230 and a blocking layer 240 is further included, and a conductive material is filled in the gate blocking layer to form the conductive layer. One embodiment of a method of forming the conductive layer 220 is described below.
Referring to fig. 5B, a gate insulating layer 230 is formed in the trench 210. The gate insulating layer 230 may be an oxide layer for insulation between the gate and the substrate. The gate insulating layer 230 may be formed using a thermal oxidation method. The gate insulating layer 230 at least covers the inner sidewall of the trench 210, and the gate insulating layer 230 has the same shape as the trench 210, for example, if the trench 210 is U-shaped, the gate insulating layer 230 also has a U-shape. Further, in the present embodiment, the gate insulating layer 230 further extends to cover the upper surface of the oxide isolation layer 250.
Referring to fig. 5C, a barrier layer 240 is formed on the gate insulating layer 230, wherein the barrier layer 240 at least covers the inner sidewall of the gate insulating layer 230. The shape of the blocking layer 240 is the same as that of the gate insulating layer 230, for example, if the gate insulating layer 230 has a U-shape, the blocking layer 240 also has a U-shape. The material of the barrier layer 240 includes, but is not limited to, a metal nitride, such as titanium nitride or tantalum nitride. In this embodiment, the barrier layer 240 covers the upper surface of the gate insulating layer 230 in addition to the inner sidewall of the gate insulating layer 230.
Referring to fig. 5D, a conductive layer 220 is formed on the barrier layer 240, wherein the conductive layer 220 at least fills the trench 210. The material of the conductive layer 220 includes, but is not limited to, a metal or a metal alloy, such as tungsten, aluminum, copper, and alloys thereof. After this step is performed, the conductive layer 220 is formed on the barrier layer 240, and the conductive layer 220 at least fills the trench 210, i.e., the conductive layer 220 fills the gap formed by the inner sidewall of the barrier layer 240. In this embodiment, the conductive layer 220 not only fills the void formed by the inner sidewall of the barrier layer 240, but also covers the upper surface of the barrier layer 240.
Referring to fig. 5E, a portion of the conductive layer 220 and the barrier layer 240 is removed by etching, and only a portion of the conductive layer 220 and the barrier layer 240 in the trench 210 remains. After this step is performed, the top of the conductive layer 220 is lower than the upper edge of the trench 210. In this embodiment, the top of the barrier layer 240 is lower than the top of the conductive layer 220. In other embodiments, the top of the barrier layer 240 may be flush with the top of the conductive layer 220, or the top of the barrier layer 240 may be higher than the top of the conductive layer 220.
Referring to step S42 and fig. 5F to 5N, the conductive layer is etched for multiple times, so that the top end of the conductive layer is in a step-like configuration with a high middle and two low sides. Specifically, the conductive layer 220 is etched in a direction perpendicular to the top end of the conductive layer several times, so that the top end of the conductive layer 220 has a stepped configuration with a high middle and two low sides.
One method for making the top end of the conductive layer in a step-like configuration with a high middle and two low sides is to etch the conductive layer multiple times along the edge of the top end of the conductive layer toward the center of the top end of the conductive layer, so that the top end of the conductive layer is in a step-like configuration with a high middle and two low sides.
One embodiment of a method for forming the top end of the conductive layer in a stepped configuration with a high center and two low sides will be described below.
A mask layer 260 is formed in the portion of the trench 210 not filled with the conductive layer 220, and the mask layer 260 covers the top end of the conductive layer 220. In this embodiment, the mask layer 260 also covers the top of the barrier layer 240 and the sidewalls of the gate oxide layer 230.
Referring to fig. 5F, a mask layer 260 is formed in the portion of the trench 210 not filled by the conductive layer 220. In this step, the mask layer 260 not only fills the portion of the trench 210 not filled by the conductive layer 220, but also covers the upper surface of the gate insulating layer 230. Further, the mask layer 260 may have a one-layer structure or a multi-layer structure. In this embodiment, the mask layer 260 has a multi-layer structure, which includes four layers, namely a first mask layer 260A, a second mask layer 260B, a third mask layer 260C and a fourth mask layer 260D. The first mask layer 260A, the second mask layer 260B, the third mask layer 260C, and the fourth mask layer 260D may be made of a material with a large etching selectivity, so as to facilitate the subsequent etching process. For example, the first mask layer 260A may be made of nitride, the second mask layer 260B may be made of carbon, the third mask layer 260C may be made of borophosphosilicate glass, and the fourth mask layer 260D may be made of tetraethoxysilane.
Referring to fig. 5G, the mask layer 260 covering the upper surface of the gate insulating layer 230 is removed, and only the mask layer 260 in the trench 210 region and above the trench is remained. After this step is performed, the plurality of mask layers are sequentially arranged along a direction from the edge of the top end of the conductive layer 220 to the center.
The mask layer 260 is patterned for multiple times from the edge of the top end of the conductive layer 220, and the conductive layer 220 is etched after the mask layer 260 is patterned each time, so that the top end of the conductive layer is in a stepped configuration with a high middle and two low sides. The specific process is described as follows:
referring to fig. 5H, the first mask layer 260A is removed along a direction perpendicular to the top end of the conductive layer 220 to expose the top end edge of the conductive layer 220. In this step, a part of the first mask layer 260A on the top of the barrier layer 240 is not removed, and the top end surface of the remaining first mask layer 260A is flush with the exposed end surface of the conductive layer 220. The remaining first mask layer 260A can protect the barrier layer 240 from being etched in a subsequent process.
Referring to fig. 5I, the conductive layer 220 is etched along a direction perpendicular to the top end of the conductive layer 220 by using the mask layer 260 as a mask, so that the height of the edge of the conductive layer 220 is lower than the height of the center of the conductive layer 220.
Referring to fig. 5J, the second mask layer 260B is removed along a direction perpendicular to the top end of the conductive layer 220, and a partial region of the top end of the conductive layer 220 is exposed. The exposed area is located at the edge of the un-etched area on the top of the conductive layer 220.
Referring to fig. 5K, the conductive layer 220 is etched along a direction perpendicular to the top of the conductive layer 220 using the mask layer 260 as a mask to form a second step. After this step is performed, the height of the exposed area of the conductive layer 220 is lower than the height of the area of the center of the conductive layer 220 covered by the mask layer 260.
Referring to fig. 5L, the third mask layer 260C is removed along a direction perpendicular to the top end of the conductive layer 220, and a partial region of the top end of the conductive layer 220 is exposed. The exposed area is located at the edge of the un-etched area on the top of the conductive layer 220.
Referring to fig. 5M, the conductive layer 220 is etched along a direction perpendicular to the top of the conductive layer 220 by using the mask layer 260 as a mask, so as to form a three-step structure. After this step is performed, the height of the exposed area of the conductive layer 220 is lower than the height of the area of the center of the conductive layer 220 covered by the mask layer 260.
Referring to fig. 5N, the fourth mask layer 260D and the remaining first mask layer 260A on the upper end surface of the barrier layer 240 are removed, and the upper end surface of the conductive layer 220 and the upper end surface of the barrier layer 240 are exposed. After this step is performed, a step word line structure is formed in the trench 210.
In the present embodiment, a plurality of mask layers are formed and sequentially patterned to etch the conductive layer to form a step-shaped word line structure, which can control the width and the etching depth of each step to avoid over-etching, thereby increasing the area of the word line and avoiding the generation of leakage current.
The method for forming the staircase word line structure is not limited to the above method, and other methods can be used to form the staircase word line structure in other embodiments of the present invention.
Further, referring to fig. 5O, after the step-type word line structure is formed, a dielectric layer 300 covers over the conductive layer 220, and the dielectric layer 300 fills the trench 210 and covers the upper surface of the gate insulating layer 230. The material of the dielectric layer 300 may be silicon nitride.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. The ladder-type word line structure is characterized by comprising a conductive layer, wherein the top end of the conductive layer is of a ladder-type configuration with a high middle and two low sides.
2. A staircase word line structure as defined in claim 1, wherein the top ends of said conductive layers are arranged axisymmetrically with respect to the center line of said conductive layers.
3. A staircase word line structure as defined in claim 1, wherein the staircase word line structure further comprises a barrier layer disposed on an outer surface of the conductive layer, the top end of the conductive layer having a higher peak than an upper end surface of the barrier layer.
4. The ladder wordline structure of claim 3, wherein a lowest point of a top of the conductive layer is higher than an upper end surface of the barrier layer.
5. The staircase word line structure of claim 3 further comprising a gate insulation layer disposed on an outer surface of the barrier layer.
6. The ladder type word line structure of claim 5 wherein an upper end surface of the gate insulating layer is higher than a highest point of a top end of the conductive layer.
7. A method for preparing a ladder-type word line structure is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a plurality of grooves which are arranged at intervals;
filling a conductive material in the groove to form a conductive layer, wherein the top end of the conductive layer is lower than the upper edge of the groove;
and etching the conducting layer for multiple times to enable the top end of the conducting layer to be in a step-like configuration with a high middle and two low sides.
8. The method of claim 7, further comprising the steps of:
forming a gate insulating layer and a barrier layer on the side wall of the trench before forming the conductive layer;
and filling a conductive material in the grid barrier layer to form the conductive layer.
9. The method for preparing a conductive layer according to claim 7, wherein the method for making the top end of the conductive layer in a stepped configuration with a high middle and two low sides comprises the steps of: and etching the conducting layer from the edge of the top end of the conducting layer to the center of the top end of the conducting layer for multiple times along the direction vertical to the top end of the conducting layer, so that the top end of the conducting layer is in a step-shaped configuration with a high middle and two low sides.
10. The method for preparing a conductive layer according to claim 9, wherein the method for making the top end of the conductive layer in a stepped configuration with a high middle and two low sides comprises the steps of:
forming a mask layer on the part, which is not filled with the conductive layer, of the groove, wherein the mask layer covers the top end of the conductive layer;
and imaging the mask layer from the edge of the top end of the conductive layer for multiple times, and etching the conductive layer after imaging the mask layer every time to enable the top end of the conductive layer to be in a step-type configuration with a high middle and two low sides.
11. The method for preparing a conductive layer according to claim 9, wherein the method for making the top end of the conductive layer in a stepped configuration with a high middle and two low sides comprises the steps of:
forming a plurality of mask layers on the part, not filled by the conducting layer, of the groove along the side wall of the groove, wherein the plurality of mask layers are sequentially arranged along the direction from the edge of the top end of the conducting layer to the center;
and removing the mask layers from the outermost mask layer in sequence, and etching the conducting layer after removing each mask layer, so that the top end of the conducting layer is in a step-type configuration with a high middle and two low sides.
12. The method of claim 11, wherein four mask layers are formed along sidewalls of the trench at portions of the trench not filled with the conductive layer.
13. The method according to claim 12, wherein the mask layer is made of nitride, carbon, borophosphosilicate glass, and tetraethoxysilane in sequence from the edge of the top end of the conductive layer to the center thereof.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021180A1 (en) * | 2022-07-28 | 2024-02-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| WO2024031818A1 (en) * | 2022-08-09 | 2024-02-15 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021180A1 (en) * | 2022-07-28 | 2024-02-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| WO2024031818A1 (en) * | 2022-08-09 | 2024-02-15 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and memory |
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