CN112670242A - Memory device, semiconductor device and method of manufacturing the same - Google Patents
Memory device, semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- CN112670242A CN112670242A CN201910979554.3A CN201910979554A CN112670242A CN 112670242 A CN112670242 A CN 112670242A CN 201910979554 A CN201910979554 A CN 201910979554A CN 112670242 A CN112670242 A CN 112670242A
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- insulating material
- forming
- trenches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000011810 insulating material Substances 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 21
- 150000002500 ions Chemical class 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 29
- 238000002360 preparation method Methods 0.000 abstract description 5
- 238000003860 storage Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 204
- 238000005530 etching Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The disclosure provides a storage device, a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method of the semiconductor device comprises the following steps: providing a substrate; forming a plurality of first grooves arranged at intervals to form a plurality of strip-shaped parts; forming a first insulating material layer filled in each first groove; forming a plurality of second trenches to divide the bar-shaped portions to form a plurality of active regions arranged in an array; forming a second insulating material layer at least covering the surface of each second groove; forming a plurality of gate trenches through the plurality of second trenches, any gate trench including a plurality of third trenches formed of the second insulating material layer and a plurality of fourth trenches spaced apart by the third trenches; forming a gate insulating layer at least covering the surface of the fourth trench in the active region, wherein the equivalent oxide thickness of the gate insulating layer is smaller than that of the second insulating material layer; and forming a gate layer in the gate trench. The preparation method of the semiconductor device can reduce the leakage current of the parasitic transistor.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory device, a semiconductor device, and a method for manufacturing the same.
Background
On-chip leakage current control is becoming increasingly important as feature sizes of integrated circuit devices are further reduced and the number of transistors per unit area is increased. Not only is the control transistor leakage current of the memory cell sufficiently small, but parasitic transistor leakage currents are also minimized.
In the prior art, the leakage current in the off state can be reduced by increasing the threshold voltage of the transistor. However, the control transistor threshold voltage of the memory cell has an optimal window, and too high or too low can affect circuit performance. Therefore, there is a need to find a method for reducing the leakage current of the parasitic transistor without increasing the threshold voltage of the control transistor.
The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a storage device, a semiconductor device and a preparation method thereof, which can reduce the leakage current of a parasitic transistor.
In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:
according to a first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a plurality of first grooves which extend along a first direction and are arranged at intervals on the surface of the substrate to form a plurality of strip-shaped parts;
forming a first insulating material layer filled in each first groove;
forming a plurality of second trenches dividing the bar portions to form a plurality of active regions arranged in an array;
forming a second insulating material layer at least covering the surface of each second groove;
forming a plurality of gate trenches extending in a second direction, the gate trenches passing through a plurality of the second trenches, any of the gate trenches including a plurality of third trenches formed of the second insulating material layer and a plurality of fourth trenches spaced apart by the third trenches;
forming a gate insulating layer at least covering the surface of the fourth trench in the active region, wherein the equivalent oxide thickness of the gate insulating layer is smaller than that of the second insulating material layer;
and forming a gate layer positioned in the gate trench.
In one exemplary embodiment of the present disclosure, a dielectric constant of a material of the second insulating material layer is less than a dielectric constant of a material of the gate insulating layer.
In one exemplary embodiment of the present disclosure, a thickness of the second insulating material layer is greater than a thickness of the gate insulating layer.
In one exemplary embodiment of the present disclosure, the third insulating layer covering the third trench surface is simultaneously formed when the gate insulating layer covering at least the fourth trench surface is formed.
In an exemplary embodiment of the present disclosure, before forming the second insulating material layer covering at least the surface of each of the second trenches, the method for manufacturing a semiconductor device further includes:
and implanting ions into the surface of each second groove, wherein the type of the implanted ions is the same as that of the doped ions of the substrate.
In an exemplary embodiment of the present disclosure, after forming a second insulating material layer covering at least a surface of each of the second trenches, the method further includes: and forming a fourth insulating material layer on the surface of the second insulating material layer to completely fill the second groove, wherein the material of the fourth insulating material layer is the same as that of the first insulating material layer.
According to a second aspect of the present disclosure, there is provided a semiconductor device comprising:
the semiconductor device comprises a substrate, a plurality of first grooves and a plurality of second grooves are arranged on the surface of the substrate, wherein the first grooves extend along a first direction and are arranged at intervals, and any one second groove is connected with two adjacent first grooves, so that active regions distributed in an array are isolated from the surface of the substrate; the surface of the substrate is also provided with a plurality of grid grooves extending along a second direction, and any grid groove penetrates through the first groove, the active region and the second groove;
the grid layer is arranged in the grid groove;
the grid insulating layer is arranged between the surface of the part of the grid groove positioned in the active area and the grid layer;
the insulating layer is arranged between the surface of the second groove and the grid layer;
wherein the equivalent oxide thickness of the gate insulating layer is less than the equivalent oxide thickness of the insulating layer.
In an exemplary embodiment of the present disclosure, a dielectric constant of the insulating layer is less than a dielectric constant of a material of the gate insulating layer.
In an exemplary embodiment of the present disclosure, a thickness of the insulating layer is greater than a thickness of the gate insulating layer.
In an exemplary embodiment of the present disclosure, a doping concentration of a portion of the substrate for forming the second trench is greater than a doping concentration of a portion of the substrate for forming the gate trench located in the active region.
According to a third aspect of the present disclosure, there is provided a memory device including the semiconductor device described above.
According to the storage device, the semiconductor device and the preparation method thereof, before the grid electrode groove is formed, a second insulating material layer is formed on the surface of the second groove; after the gate trench is formed, a gate insulating layer is formed on the surface of the fourth trench. Because the equivalent oxide layer thickness of the gate insulating layer is smaller than that of the second insulating material layer, the threshold voltage of a parasitic transistor formed between the second trench and the gate layer of the substrate can be larger than that of a control transistor formed between the active region and the gate layer of the substrate, so that the leakage current of the parasitic transistor in a turn-off state can be reduced, and the performance of the semiconductor device can be improved. Furthermore, the gate insulating layer of the parasitic transistor and the gate insulating layer of the control transistor are formed respectively, so that the threshold voltage of the parasitic transistor and the threshold voltage of the control transistor are prevented from being simultaneously increased, the threshold voltage of the parasitic transistor can be selectively increased on the premise that the threshold voltage of the control transistor is in an optimal window, the leakage current of the parasitic transistor in a turn-off state is selectively reduced, and the performance of a semiconductor device is improved.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 2 is a schematic top view of a first trench according to an embodiment of the disclosure.
Fig. 3 is a schematic top view of a first insulating material layer according to an embodiment of the disclosure.
Fig. 4 is a schematic top view of a second trench formed according to an embodiment of the disclosure.
Fig. 5 is a schematic top view of a second insulating material layer according to an embodiment of the disclosure.
Fig. 6 is a schematic cross-sectional structural view of forming a second insulating material layer according to an embodiment of the disclosure, the cross-sectional position being at CD of fig. 5.
Fig. 7 is a schematic top view of a fourth insulating material layer according to an embodiment of the disclosure.
Fig. 8 is a schematic top view of a gate trench formed according to an embodiment of the present disclosure.
Fig. 9 is a schematic top view of a gate insulating layer according to an embodiment of the disclosure.
Fig. 10 is a schematic diagram of a top view structure of forming a gate layer according to an embodiment of the disclosure.
Fig. 11 is a schematic cross-sectional structure diagram of forming a gate layer according to an embodiment of the disclosure, where the cross-sectional position is at CD of fig. 10.
Fig. 12 is a schematic top view of a gate trench formed according to an embodiment of the present disclosure.
The reference numerals of the main elements in the figures are explained as follows:
100. a substrate; 111. a first trench; 112. a second trench; 120. a bar-shaped portion; 121. an active region; 201. a first layer of insulating material; 202. a second layer of insulating material; 300. a gate trench; 301. a third trench; 302. a fourth trench; 401. a gate insulating layer; 402. a third insulating layer; 500. a gate layer; 600. a fourth layer of insulating material; 601. a fourth insulating layer; A. a first direction; B. a second direction.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.
In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.
In the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, as shown in fig. 1 to 12, the method including:
step S110, as shown in fig. 6, providing a substrate 100;
step S120, as shown in fig. 2, forming a plurality of first trenches 111 extending along the first direction a and arranged at intervals on the surface of the substrate 100 to form a plurality of bar-shaped portions 120;
step S130, as shown in fig. 3, forming a first insulating material layer 201 filling each first trench 111;
step S140, as shown in fig. 4, forming a plurality of second trenches 112, the second trenches 112 dividing the stripe portions 120 to form a plurality of active regions 121 arranged in an array;
step S150, as shown in fig. 5 and 6, forming a second insulating material layer 202 at least covering the surface of each second trench 112;
step S160, as shown in fig. 12 and 8, forming a plurality of gate trenches 300 extending along the second direction B, the gate trenches 300 passing through the plurality of second trenches 112, any gate trench 300 including a plurality of third trenches 301 formed by the second insulating material layer 202 and a plurality of fourth trenches 302 spaced apart by the third trenches 301;
step S170, as shown in fig. 9, forming a gate insulating layer 401 at least covering the fourth trench 302 on the surface of the active region 121, wherein an equivalent oxide thickness of the gate insulating layer 401 is smaller than an equivalent oxide thickness of the second insulating material layer 202;
in step S180, as shown in fig. 10 and 11, a gate layer 500 is formed in the gate trench 300.
In the method for manufacturing a semiconductor device provided by the present disclosure, before forming the gate trench 300, a second insulating material layer 202 is formed on the surface of the second trench 112; after the gate trench 300 is formed, a gate insulating layer 401 is formed on the surface of the fourth trench 302. Since the equivalent oxide thickness of the gate insulating layer 401 is smaller than the equivalent oxide thickness of the second insulating material layer 202, the threshold voltage of the parasitic transistor formed between the substrate 100 at the second trench 112 and the gate layer 500 may be larger than the threshold voltage of the control transistor formed between the substrate 100 at the active region 121 and the gate layer 500, which may reduce the leakage current of the parasitic transistor in the off state and improve the performance of the semiconductor device.
Furthermore, the gate insulating layer of the parasitic transistor and the gate insulating layer of the control transistor are formed respectively, so that the threshold voltage of the parasitic transistor and the threshold voltage of the control transistor are prevented from being simultaneously increased, the threshold voltage of the parasitic transistor can be selectively increased on the premise that the threshold voltage of the control transistor is in an optimal window, the leakage current of the parasitic transistor in a turn-off state is selectively reduced, and the performance of a semiconductor device is improved.
The steps of the method for manufacturing a semiconductor device according to the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings:
in step S110, the substrate 100 may be a silicon-based semiconductor substrate 100, such as a silicon-based intrinsic semiconductor substrate 100, a P-type doped silicon-based semiconductor substrate 100, or an N-type doped silicon-based semiconductor substrate 100. The substrate 100 may have a single-layer semiconductor structure, or may have a plurality of the same or different semiconductor layers stacked in sequence. For example, the substrate 100 may include a first doped semiconductor layer and a second doped semiconductor layer stacked on the first doped semiconductor layer, and the doping types of the first doped semiconductor layer and the second doped semiconductor layer may be different.
In step S120, as shown in fig. 2, a plurality of first grooves 111 extending in the first direction a and disposed at intervals may be formed on one surface of the substrate 100 through a photolithography process such that the surface of the substrate 100 is divided into a plurality of bar-shaped portions 120 by the first grooves 111. It is understood that the respective bar portions 120 extend in the first direction a and are spaced apart by the first grooves 111.
In the present disclosure, the photolithography process may include the steps of gumming, exposing, developing, etching, and removing the photoresist. For example, in step S120, the photolithography process may include the following steps: forming a photoresist layer on the surface of the substrate 100; exposing the photoresist; developing to make the residual photoresist expose partial surface of the substrate 100 and cover partial surface of the substrate 100; etching to form a first trench 111 in the portion of the substrate 100 not covered by the photoresist; and removing the residual photoresist layer.
In step S130, the first insulating material layer 201 may be formed by a deposition method, for example, the first insulating material layer 201 may be formed by a CVD (chemical vapor deposition) method. Thus, as shown in fig. 3, two adjacent strip portions 120 are separated by the first insulating material layer 201.
In one embodiment of the present disclosure, the material of the first insulating material layer 201 may be silicon oxide to ensure mutual isolation between the subsequently formed active regions 121. In another embodiment of the present disclosure, the first insulating material layer 201 may fill the first trench 111 so as to control the depth of the gate trench 300 in the first trench 111 and the active region 121 when forming the gate trench 300.
Of course, the first insulating material layer 201 may also be formed by other methods. The surface portion of the substrate 100 exposed by the first trench 111 may also be oxidized, for example, by an oxidation method, to form a first insulating material layer 201 composed of an oxide in the first trench 111. This is not detailed in this disclosure.
In step S140, the second trench 112 may be formed through a photolithography process. Any one of the second grooves 112 may connect two adjacent first grooves 111 to divide the strip portion 120 between the two adjacent first grooves 111. The plurality of second trenches 112 divide the plurality of stripe portions 120 so that the surface of the substrate 100 forms a plurality of active regions 121 distributed in an array divided by the first trenches 111 and the second trenches 112. As can be seen from fig. 4, the active regions 121 are formed by dividing the stripe portions 120 by the second trenches 112, and thus the active regions 121 have a long axis direction along the first direction a.
In one embodiment of the present disclosure, before step S150, ions may be further implanted into the surface of each second trench 112, and the type of the implanted ions is the same as the type of the doping ions of the substrate 100. In this way, the doping concentration of the portion of the substrate 100 for forming the second trench 112 is increased, so that the threshold voltage of the parasitic transistor is increased, the threshold voltage of the parasitic transistor is selectively increased, and the leakage current of the parasitic transistor in the off state is selectively reduced.
In step S150, as shown in fig. 5 and 6, a second insulating material layer 202 is formed to cover at least the surface of each second trench 112. Alternatively, the second insulating material layer 202 may be formed by a deposition method, for example, a CVD method may be used to deposit a layer of second insulating material on the surface of the second trench 112 to form the second insulating material layer 202.
Alternatively, in order to increase the equivalent oxide thickness of the second insulating material layer 202, the material of the second insulating material layer 202 may have a smaller dielectric constant. For example, the dielectric constant of the material of the second insulating material layer 202 may be smaller than the dielectric constant of the material of the gate insulating layer 401. Further alternatively, the material of the second insulating material layer 202 may be SiOC (silicon oxycarbide) or α -C: f (fluorinated amorphous carbon).
Alternatively, the second insulating material layer 202 may have a thicker thickness in order to increase the equivalent oxide thickness of the second insulating material layer 202. For example, the thickness of the second insulating material layer 202 may be greater than the thickness of the gate insulating layer 401.
Through step S150, as shown in fig. 6, the surface of the second trench 112 is covered with a second insulating material layer 202; in this way, a third trench 301 is formed on a side of the second insulating material layer 202 away from the substrate 100. It will be appreciated that the third trench 301 passes through the second trench 112.
In step S160, as shown in fig. 12, a plurality of gate trenches 300 extending in the second direction B are formed. Wherein, as shown in fig. 12, the gate trenches 300 pass through the plurality of second trenches 112, and any one of the gate trenches 300 includes a plurality of third trenches 301 formed by the second insulating material layer 202 and a plurality of fourth trenches 302 spaced apart by the third trenches 301. As shown in fig. 12, the fourth trench 302 may extend in the second direction B and pass through the first trench 111 and the active region 121, and communicate with the third trench 301 disposed along the same line.
Alternatively, when the gate trench 300 is formed, each of the fourth trenches 302 may be selectively formed such that the fourth trenches 302 and the third trenches 301 located on the same line communicate with each other to form the gate trench 300. For example, in one embodiment of the present disclosure, in step S160, an etching method capable of selectively etching the first insulating material layer 201 and the active region 121 may be adopted, so that the first insulating material layer 201 and the active region 121 may be etched to form the fourth trench 302, and the etching process does not etch or etches the second insulating material layer 202 by a very small amount. For another example, in another embodiment of the present disclosure, in step S160, when the gate trench 300 is formed, a protection layer may be formed on the surface of the third trench 301, and then the fourth trench 302 is formed by etching, so as to avoid etching the second insulating material layer 202 during the etching process.
Optionally, as shown in fig. 7, in order to avoid a larger leakage current of the parasitic transistor when the parasitic transistor is turned off due to the larger depth of the gate trench 300 at the third trench 301, and also to effectively protect the second insulating material layer 202 when the gate trench 300 is formed, the method for manufacturing a semiconductor device of the present disclosure may further include:
after step S150 and before step S160, i.e. after forming the second insulating material layer 202 and before forming the gate trench 300, a fourth insulating material layer 600 is formed on the surface of the second insulating material layer 202 to completely fill the second trench 112, wherein the material of the fourth insulating material layer 600 is the same as that of the first insulating material layer 201. In this way, as shown in fig. 8, when the gate trench 300 is formed by etching in step S160, the fourth insulating material layer 600 may be completely or partially etched, so that the time for exposing the second insulating material layer 202 to the etching environment may be shortened, and the thickness of the second insulating material layer 202 that may be lost when forming the gate trench 300 may be reduced. Furthermore, when the fourth insulating material layer 600 is partially etched, that is, when the fourth insulating material layer 600 remains in the third trench 301 after the gate trench 300 is formed, the depth of the gate trench 300 in the second trench 112 can be reduced, so that the buried depth of the gate layer 500 in the second trench 112 is reduced, and the leakage current of the parasitic transistor in the off state is further reduced. Wherein the remaining fourth insulating material layer 600 may serve as a fourth insulating layer 601 of the prepared semiconductor device.
In step S170, as shown in fig. 9, a gate insulating layer 401 covering the surface of the active area 121 of the fourth trench 302 may be formed by deposition, for example, a gate insulating layer 401 may be formed on the surface of the active area 121 of the fourth trench 302 by CVD.
Alternatively, as shown in fig. 9 and 11, when the gate insulating layer 401 is formed by a deposition method, a third insulating layer 402 may also be simultaneously formed on the surface of the third trench 301; in other words, in step S170, a gate insulating material layer may be deposited on the surface of the substrate, where the gate insulating material layer is located in the fourth trench 302 and is located in the portion of the active region 121 to serve as the gate insulating layer 401 of the present disclosure, and the gate insulating material layer is located in the portion of the third trench 301 to serve as the third insulating layer 402 of the present disclosure. As such, the third insulating layer 402 may have the same material and the same thickness as the gate insulating layer 401. In the semiconductor device formed according to the method, the gate insulating layer of the parasitic transistor comprises the second insulating material layer 202 and the third insulating layer 402 which are arranged in a stacked mode, the equivalent oxide thickness of the gate insulating layer is larger, the threshold voltage is larger, and the leakage current in the off state is smaller.
Furthermore, as shown in fig. 9 and 11, a portion of the gate insulating material layer located in the fourth trench 302 and located in the first trench 111 may be remained, and since the third insulating layer 402 does not need to be removed, a patterning process on the deposited gate insulating material layer may not be required, and a manufacturing process of the semiconductor device and a mask may be saved.
Alternatively, the material of the gate insulating layer 401 may be silicon oxide.
Of course, the gate insulating layer 401 may be formed by other methods. For example, the surface of the active region 121 exposed by the fourth trench 302 may be oxidized to an oxide, such as silicon oxide, by an oxidation method.
In step S180, as shown in fig. 10 and 11, a gate layer 500 positioned within the gate trench 300 may be formed. That is, the gate layer 500 is located in the gate trench 300 and on a side of the gate insulating layer 401 and the second insulating material layer 202 away from the substrate 100.
Thus, as shown in fig. 11, in the prepared semiconductor device, the surface of the substrate 100 is provided with a plurality of first trenches 111 and a plurality of second trenches 112, wherein the first trenches 111 extend along the first direction a and are arranged at intervals, and any one of the second trenches 112 connects two adjacent first trenches 111, so that the surface of the substrate 100 is isolated from the active regions 121 distributed in an array; the surface of the substrate 100 is further provided with a plurality of gate trenches 300 extending along the second direction B, and any one of the gate trenches 300 passes through the first trench 111, the active region 121, and the second trench 112. A gate layer 500 is disposed in the gate trench 300, and a gate insulating layer 401 and an insulating layer are disposed between the gate layer 500 and the substrate 100. The gate insulating layer 401 is disposed between the gate trench 300 and the gate layer 500; the insulating layer is disposed between the surface of the second trench 112 and the gate layer 500. Wherein the equivalent oxide thickness of the gate insulating layer 401 is smaller than the equivalent oxide thickness of the insulating layer. The insulating layer may include a second layer of insulating material 202 disposed on the surface of the second trench 112. In some embodiments, the insulating layer may further include a residual fourth insulating material layer 600 disposed on a side of the second insulating material layer 202 away from the substrate 100. In some embodiments, the insulating layer may further include a third insulating layer 402 disposed on a side of the second insulating material layer 202 away from the substrate 100.
Optionally, the method for manufacturing a semiconductor device of the present disclosure may further include forming an interlayer dielectric layer covering the gate layer 500.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.
The present disclosure also provides a semiconductor device, as shown in fig. 10 and 11, including a substrate 100, a gate electrode layer 500, a gate insulating layer 401, and an insulating layer, wherein,
a plurality of first trenches 111 and a plurality of second trenches 112 are arranged on the surface of the substrate 100, wherein the first trenches 111 extend along the first direction a and are arranged at intervals, and any one second trench 112 connects two adjacent first trenches 111, so that the surface of the substrate 100 is isolated from active regions 121 distributed in an array; the surface of the substrate 100 is further provided with a plurality of gate trenches 300 extending along the second direction B, and any gate trench 300 passes through the first trench 111, the active region 121 and the second trench 112; the gate layer 500 is disposed in the gate trench 300; the gate insulating layer 401 is disposed between the gate trench 300 and the gate layer 500; the insulating layer is arranged between the surface of the second trench 112 and the gate layer 500; wherein the equivalent oxide thickness of the gate insulating layer 401 is smaller than the equivalent oxide thickness of the insulating layer.
In the semiconductor device provided by the present disclosure, a control transistor may be formed between the gate layer 500, the gate insulating layer 401, and the active region 121, and a parasitic transistor may be formed between the gate layer 500, the insulating layer, and the active region 121. Since the equivalent oxide layer thickness of the gate insulating layer 401 is smaller than that of the insulating layer, the threshold voltage of the parasitic transistor of the semiconductor device of the present disclosure is larger than that of the control transistor, so that the threshold voltage of the parasitic transistor can be increased on the premise that the threshold voltage of the control transistor is within the optimal window, and the leakage current of the parasitic transistor in the off state can be further reduced.
In one embodiment of the present disclosure, the insulating layer may include a second insulating material layer 202 disposed on the surface of the second trench 112.
In another embodiment of the present disclosure, as shown in fig. 11, the insulating layer may include a second insulating material layer 202 disposed on the surface of the second trench 112, and a fourth insulating layer 601 disposed on a side of the second insulating material layer 202 away from the substrate 100.
In another embodiment of the present disclosure, as shown in fig. 11, the insulating layer may include a second insulating material layer 202 disposed on the surface of the second trench 112, and a third insulating layer 402 disposed on a side of the second insulating material layer 202 away from the substrate 100. Alternatively, the third insulating layer 402 and the gate insulating layer 401 have the same material and thickness.
Optionally, the dielectric constant of the insulating layer is smaller than the dielectric constant of the material of the gate insulating layer 401. For example, the dielectric constant of the material of the second insulating material layer 202 may be smaller than the dielectric constant of the material of the gate insulating layer 401. Alternatively, the material of the second insulating material layer 202 may be SiOC (silicon oxycarbide) or α -C: f (fluorinated amorphous carbon).
Optionally, the thickness of the insulating layer is greater than the thickness of the gate insulating layer 401. For example, the thickness of the second insulating material layer 202 may be greater than that of the gate insulating layer 401 to ensure that the insulating layer has a larger equivalent oxide thickness.
Optionally, the doping concentration of the portion of the substrate 100 used to form the second trench 112 is greater than the doping concentration of the portion of the substrate 100 used to form the gate trench 300 located in the active region 121. In other words, the doping concentration of the portion of the substrate 100 near the insulating layer is greater than the doping concentration of the portion of the substrate 100 near the gate insulating layer 401. Thus, the threshold voltage of the parasitic transistor can be further improved, the leakage current of the parasitic transistor in an off state can be reduced, and the performance of the semiconductor device can be improved.
Embodiments of the present disclosure also provide a memory device including any one of the semiconductor devices described in the above semiconductor device embodiments. The memory device may be a DRAM, SRAM, or other type of memory device. Since the memory device has any one of the semiconductor devices described in the above semiconductor device embodiments, the same advantageous effects are obtained, and the details of the present disclosure are not repeated herein.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a plurality of first grooves which extend along a first direction and are arranged at intervals on the surface of the substrate to form a plurality of strip-shaped parts;
forming a first insulating material layer filled in each first groove;
forming a plurality of second trenches dividing the bar portions to form a plurality of active regions arranged in an array;
forming a second insulating material layer at least covering the surface of each second groove;
forming a plurality of gate trenches extending in a second direction, the gate trenches passing through a plurality of the second trenches, any of the gate trenches including a plurality of third trenches formed of the second insulating material layer and a plurality of fourth trenches spaced apart by the third trenches;
forming a gate insulating layer at least covering the surface of the fourth trench in the active region, wherein the equivalent oxide thickness of the gate insulating layer is smaller than that of the second insulating material layer;
and forming a gate layer positioned in the gate trench.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a dielectric constant of a material of the second insulating material layer is smaller than a dielectric constant of a material of the gate insulating layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the second insulating material layer is larger than a thickness of the gate insulating layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein a third insulating layer covering the surface of the third trench is formed at the same time as forming the gate insulating layer covering at least the surface of the fourth trench.
5. The method for manufacturing a semiconductor device according to claim 1, wherein before forming the second insulating material layer covering at least the surface of each of the second trenches, the method further comprises:
and implanting ions into the surface of each second groove, wherein the type of the implanted ions is the same as that of the doped ions of the substrate.
6. The method for manufacturing a semiconductor device according to claim 1, further comprising, after forming a second insulating material layer covering at least a surface of each of the second trenches: and forming a fourth insulating material layer on the surface of the second insulating material layer to completely fill the second groove, wherein the material of the fourth insulating material layer is the same as that of the first insulating material layer.
7. A semiconductor device, comprising:
the semiconductor device comprises a substrate, a plurality of first grooves and a plurality of second grooves are arranged on the surface of the substrate, wherein the first grooves extend along a first direction and are arranged at intervals, and any one second groove is connected with two adjacent first grooves, so that active regions distributed in an array are isolated from the surface of the substrate; the surface of the substrate is also provided with a plurality of grid grooves extending along a second direction, and any grid groove penetrates through the first groove, the active region and the second groove;
the grid layer is arranged in the grid groove;
the grid insulating layer is arranged between the surface of the part of the grid groove positioned in the active area and the grid layer;
the insulating layer is arranged between the surface of the second groove and the grid layer;
wherein the equivalent oxide thickness of the gate insulating layer is less than the equivalent oxide thickness of the insulating layer.
8. The semiconductor device according to claim 7, wherein a dielectric constant of the insulating layer is smaller than a dielectric constant of a material of the gate insulating layer.
9. The semiconductor device according to claim 7, wherein a thickness of the insulating layer is larger than a thickness of the gate insulating layer.
10. The semiconductor device of claim 7, wherein a doping concentration of a portion of the substrate for forming the second trench is greater than a doping concentration of a portion of the substrate for forming a gate trench in the active region.
11. A memory device comprising the semiconductor device according to any one of claims 7 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910979554.3A CN112670242A (en) | 2019-10-15 | 2019-10-15 | Memory device, semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910979554.3A CN112670242A (en) | 2019-10-15 | 2019-10-15 | Memory device, semiconductor device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112670242A true CN112670242A (en) | 2021-04-16 |
Family
ID=75399990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910979554.3A Pending CN112670242A (en) | 2019-10-15 | 2019-10-15 | Memory device, semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112670242A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174648A (en) * | 2006-09-08 | 2008-05-07 | 奇梦达股份公司 | Transistor and memory cell array |
| US20100258858A1 (en) * | 2009-04-10 | 2010-10-14 | Hynix Semiconductor Inc. | Method of fabricating semiconductor device |
| CN103377905A (en) * | 2012-04-30 | 2013-10-30 | 三星电子株式会社 | Methods of fabricating semiconductor devices having buried channel array |
| US20140117459A1 (en) * | 2012-10-26 | 2014-05-01 | Samsung Electronics Co., Ltd. | Memory device |
| CN210805732U (en) * | 2019-10-15 | 2020-06-19 | 长鑫存储技术有限公司 | Memory device and semiconductor device |
-
2019
- 2019-10-15 CN CN201910979554.3A patent/CN112670242A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174648A (en) * | 2006-09-08 | 2008-05-07 | 奇梦达股份公司 | Transistor and memory cell array |
| US20100258858A1 (en) * | 2009-04-10 | 2010-10-14 | Hynix Semiconductor Inc. | Method of fabricating semiconductor device |
| CN103377905A (en) * | 2012-04-30 | 2013-10-30 | 三星电子株式会社 | Methods of fabricating semiconductor devices having buried channel array |
| US20140117459A1 (en) * | 2012-10-26 | 2014-05-01 | Samsung Electronics Co., Ltd. | Memory device |
| CN210805732U (en) * | 2019-10-15 | 2020-06-19 | 长鑫存储技术有限公司 | Memory device and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101472626B1 (en) | Semiconductor device and method of forming the same | |
| KR100881825B1 (en) | Semiconductor device and method for fabricating the same | |
| US9087856B2 (en) | Semiconductor device with buried bit line and method for fabricating the same | |
| US20070045697A1 (en) | Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures | |
| US8927966B2 (en) | Dynamic random access memory unit and method for fabricating the same | |
| TW200939402A (en) | Semiconductor device and method for manufacturing the same | |
| KR100593739B1 (en) | Morse field effect transistor with body-source connection and its manufacturing method | |
| JP2006278674A (en) | Field effect transistor and its manufacturing method, and semiconductor device | |
| US20060049445A1 (en) | Dram having at least three layered impurity regions between channel holes and method of fabricating same | |
| US20170256556A1 (en) | Nonvolatile memory device and method for fabricating the same | |
| CN210805732U (en) | Memory device and semiconductor device | |
| CN113629057B (en) | Semiconductor structure and manufacturing method thereof | |
| CN115083900A (en) | Semiconductor structure, forming method thereof and memory | |
| CN112670242A (en) | Memory device, semiconductor device and method of manufacturing the same | |
| JP2010278394A (en) | Method for manufacturing semiconductor device | |
| TW201501307A (en) | Semiconductor device | |
| KR100453864B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR20120121723A (en) | Semiconductor device and method for forming the same | |
| US6362037B1 (en) | Semiconductor device and method of fabricating same | |
| KR101952510B1 (en) | Thyristor-based Memory and Method of fabricating the same | |
| KR100713904B1 (en) | Method for fabricating semiconductor device | |
| KR100265370B1 (en) | A method for fabricating dram device | |
| US8349719B2 (en) | Semiconductor device and method for fabricating the same | |
| KR20010058136A (en) | Method of fabricating semiconductor device | |
| US20110309424A1 (en) | Structure of memory device and process for fabricting the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |