CN112669756A - Array substrate, driving chip and display device - Google Patents
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Abstract
The invention discloses an array substrate, a driving chip and a display device, and relates to the technical field of display. The array substrate comprises a display area and a non-display area surrounding the display area, the non-display area comprises a binding area, the array substrate further comprises a first edge and a second edge, the first edge and the second edge are oppositely arranged, a plurality of bonding pads are located in the binding area, the plurality of bonding pads comprise at least one output bonding pad group, the output bonding pad group comprises a plurality of output bonding pads, the center point of the binding area points to the direction of the first edge and/or the second edge, and the orthographic projection area of at least part of the output bonding pads located in the same output bonding pad group on the plane where the light-emitting surface of the array substrate is located is gradually increased. Compared with the prior art, through the area that changes the output pad, change the resistance of output pad, improve because the fan-out district lead wire length difference that is connected with the output pad electricity causes the signal line load different, and then leads to showing bad problem to promote display quality, improve production efficiency, reduction in production cost.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a driving chip and a display device.
Background
With the continuous development of science and technology, intelligent mobile terminal equipment gradually becomes an indispensable part of daily life of consumers. Among them, the preparation of display devices, especially display panels and array substrates, has received much attention.
In a display device, a pad and a lead are disposed around a display area, so that a signal of a driving chip is transmitted to the display area to control pixels of the display area, thereby displaying a display image. However, in prior designs, the length of the leads connected to the pads on both sides is typically greater than the length of the leads connected to the pads in the middle region. Because the loads of different leads are different, signals transmitted to the display area are different, so that the problem of poor display is caused, and the display effect of the display device is seriously influenced.
Disclosure of Invention
In view of the above, the invention provides an array substrate, a driving chip and a display device.
In a first aspect, the present invention provides an array substrate, including a display area and a non-display area surrounding the display area, wherein the non-display area includes a binding area;
the array substrate further comprises a first edge and a second edge, and the first edge and the second edge are oppositely arranged;
a plurality of bonding pads located within the bonding region; the plurality of pads comprise at least one output pad group, the output pad group comprises a plurality of output pads, the output pads in the same output pad group are arranged in parallel along a first direction, and the first direction is intersected with the first edge;
and along the direction of the central point of the binding region pointing to the first edge and/or the second edge, the orthographic projection area of the output bonding pads at least partially positioned in the same output bonding pad group on the plane where the light-emitting surface of the array substrate is positioned is gradually increased.
In a second aspect, the present invention provides a driver chip disposed in match with the array substrate of the first aspect, including a plurality of pads, where the plurality of pads includes at least one output pad group, the output pad group includes a plurality of output pads, and the output pads in the same output pad group are arranged in a row;
the driving chip comprises a third edge and a fourth edge, and the third edge and the fourth edge are oppositely arranged;
and along the direction of the central point of the driving chip pointing to the third edge and/or the fourth edge, the orthographic projection area of the output pads at least partially positioned in the same output pad group on the plane where the driving chip is positioned is gradually increased.
In a third aspect, the present invention provides a display device, including the array substrate and the driving chip provided in the present invention.
Compared with the prior art, the array substrate, the driving chip and the display device provided by the invention at least realize the following beneficial effects:
in the array substrate, the driving chip and the display device provided by the invention, along the direction that the central point of the binding region points to the first edge and/or the second edge, the orthographic projection area of the output bonding pads at least partially positioned in the same output bonding pad group on the plane where the light-emitting surface of the array substrate is positioned is gradually increased. Compared with the prior art, through the area that changes the output pad, change the resistance of output pad, improve because the fan-out district lead wire length difference that is connected with the output pad electricity causes the signal line load different, and then leads to showing bad problem to promote display quality, improve production efficiency, reduction in production cost.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic top view of an array substrate in a conventional design;
FIG. 2 is a partially enlarged view of a KK' region of the array substrate shown in FIG. 1;
fig. 3 is a schematic top view of an array substrate according to the present invention;
fig. 4 is a partially enlarged schematic view of a KK region in the array substrate shown in fig. 3;
FIG. 5(a) is a schematic diagram of a top view structure of an output pad;
FIG. 5(b) is a schematic diagram of a top view structure of another output pad;
FIG. 5(c) is a schematic diagram of a top view structure of another output pad;
fig. 6 is a schematic top view of an output pad set according to the present invention;
fig. 7 is another partially enlarged view of a KK region in the array substrate shown in fig. 3;
fig. 8 is another partially enlarged view of a KK region in the array substrate shown in fig. 3;
fig. 9 is another partially enlarged view of a KK region in the array substrate shown in fig. 3;
fig. 10 is a schematic top view of a driving chip according to the present invention;
fig. 11 is a schematic top view of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1 and 2, fig. 1 is a schematic top view of an array substrate in a conventional design, and fig. 2 is a partially enlarged schematic view of the array substrate shown in fig. 1. In general, the array substrate 100 includes a display area AA ' and a non-display area NA ' surrounding the display area AA ', the non-display area NA ' includes a stepped area TJ ', the stepped area TJ ' includes a bonding area 1 ' and a fan-out area 2 ', and the bonding area 1 ' includes an output pad group 12 ' and an input pad group 13 '. The output pad group 12 ' includes a plurality of output pads 121 ', and the signal lines 5 ' in the display area AA ' are electrically connected to the output pads 121 ' through the leads 7 ', so that the electrical signals of the driving chip (not shown) are transmitted to the signal lines 5 ' in the display area AA ' through the output pads 121 ' and the leads 7 ', and the display area AA ' displays corresponding images. However, since the width of the output pad group 12 ' in the first direction D1 is generally smaller than the width of the display area AA ', the lengths of the leads 7 ' corresponding to the output pads 121 ' in the same output pad group 12 ' are not uniform. Specifically, a first lead 71 'and a second lead 72' are included in a direction pointing to the first edge 3 'along the center point 8' of the bonding region 1 ', wherein the first lead 71' is located between the second lead 72 'and the first edge 3'. It can be seen that the length of the first lead 71 'is greater than the length of the second lead 72'. As is well known to those skilled in the art, the electrical resistance of the electrical conductor is proportional to the length of the electrical conductor, and thus the electrical resistance of the first lead 71 'is greater than the electrical resistance of the second lead 72'. Similarly, the problem also exists along the direction of the central point 8 ' of the binding region 1 ' towards the second edge 4 '. The load of the signal line 5 ' varies due to the difference in resistance of the lead 7 ', and thus the load of the electric signal transmitted to the signal line 5 ' varies, resulting in a problem of display failure due to the unevenness of the display screen.
In order to solve the above problems, the present invention provides an array substrate, a driving chip and a display device. Embodiments of an array substrate, a driving chip and a display device provided by the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Referring to fig. 3, fig. 4 and fig. 5, in which fig. 3 is a schematic top view structure diagram of an array substrate provided by the present invention, fig. 4 is a partially enlarged schematic top view of the array substrate shown in fig. 3, fig. 5(a) is a schematic top view structure diagram of an output pad, fig. 5(b) is a schematic top view structure diagram of another output pad, and fig. 5(c) is a schematic top view structure diagram of another output pad. The invention provides an array substrate 200, which comprises a display area AA and a non-display area NA surrounding the display area AA, wherein the non-display area NA comprises a binding area 1;
the array substrate 200 further includes a first edge 3 and a second edge 4, and the first edge 3 and the second edge 4 are oppositely disposed;
a plurality of pads 11 located within the bonding region 1; the plurality of pads 11 include at least one output pad group 12, the output pad group 12 includes a plurality of output pads 121, the output pads 121 in the same output pad group 12 are arranged in parallel along a first direction D1, and the first direction D1 intersects the first edge 3;
along the direction that the central point 8 of the binding region 1 points to the first edge 3 and/or the second edge 4, the orthographic projection area of the output pads 121 at least partially located in the same output pad group 12 on the plane where the light emitting surface of the array substrate 200 is located gradually increases.
It should be noted that fig. 3 only illustrates the rectangular array substrate 200, and the shape of the array substrate may be changed according to actual requirements, which is not limited in the present invention. The number of the pads 11 and the signal lines 5 and the size of the pads 11 in fig. 3 and 4 are only schematic, and do not indicate the actual number of the pads 11 and the signal lines 5 and the size of the pads 11, and the specific number and size may be set according to the actual situation.
It is understood that the present invention defines a direction pointing to the first edge 3 and/or the second edge 4 along the central point 8 of the bonding region 1, and the area of the orthographic projection of the output pads 121 at least partially located on the same output pad group 12 on the plane where the light-emitting surface of the array substrate 200 is located is gradually increased, that is, the area of the orthographic projection of the output pads 121 at least partially located on the first edge 3 and/or the second edge 4 in the same output pad group 12 is gradually increased
Larger than the orthographic area of the output pad 121 near the center point 8 of the bonding region 1. As can be seen from the resistance theorem, the resistance R is ρ L/S, where ρ is the resistivity of the conductor, L is the length of the conductor, and S is the cross-sectional area of the conductor. From this, it is understood that the resistance R of the conductor is inversely proportional to the cross-sectional area S of the conductor, i.e., the resistance R decreases as the cross-sectional area S of the conductor increases. Therefore, by adjusting the area of the output pad 121, the resistance of the output pad 121 can be changed such that the resistance of at least some of the output pads 121 in the same output pad group 12 gradually decreases in a direction pointing to the first edge 3 and/or the second edge 4 along the center point 8 of the bonding region 1. As mentioned before, the resistance of the leads 7 increases gradually in a direction pointing along the center point 8 of the bonding region 1 towards the first edge 3 and/or the second edge 4. Therefore, in the array substrate provided by the present invention, by increasing the area of the output pads 121 located on the same output pad group 12 near the first edge 3 and/or the second edge 4, the resistance of the output pads 121 is reduced, and then the resistance of the lead 7 is matched, so that the problem that the difference of the electrical signals transmitted to the signal lines 5 due to the different resistances of the lead 7 can be weakened, and the display effect is improved, and the problem of display unevenness is avoided.
Specifically, referring to fig. 5(a), 5(b) and 5(c), the rectangular output pad 121 is taken as an example in fig. 5(a), 5(b) and 5(c), and the actual shape of the output pad 121 is not shown. When the width of the first output pad 1211 in the first direction D1 is a and the length in the second direction D2 is b (the first direction D1 is perpendicular to the second direction D2), the area of the first output pad 1211 is S1Ab. At this time, the resistance R of the first output pad 12111＝ρL/S1ρ L/ab. The second output pad 1212 has a constant width in the first direction D1 and a length in the second direction D2 increased by 10% compared to the first output pad 1211, that is, when the length of the second output pad 1212 in the second direction D2 is (b +0.1b) ═ 1.1b, the area of the second output pad 1212 is S21.1 ab. Δ S ═ S compared with the first output pad 12112/S11.1ab/ab 1.1. The resistance R of the second output pad 1212 at this time2＝ρL/S2ρ L/1.1 ab. By calculation, Δ R ═ R2/R1The value of (ρ L/1.1ab)/(ρ L/ab) is 1/1.1 and 90.9%. That is, when the length of the output pad 121 in the second direction D2 increases by 10%, the area of the output pad 121 increases by 10%, and the resistance of the output pad 121 at this time increases by 10%The reduction was 9.1%. Similarly, the width of the output pad 121 in the first direction D1 is increased by itself, and the effect is the same. When the lengths of the output pads 121 in both the first direction D1 and the second direction D2 are increased, the resistance of the output pads 121 is further decreased. Specifically, when the width of the third output pad 1213 in the first direction D1 is 1.1a and the length of the third output pad 1213 in the second direction D2 is 1.1b, the area S3 of the third output pad 1213 is 1.1a × 1.1b — 1.21ab, and Δ S is S3/S1 — 1.21. At this time, the resistance R3 ═ ρ L/S3 ═ ρ L/1.21ab, and Δ R ═ R3/R1 ═ ρ L/1.21ab)/(ρ L/ab ═ 1/1.21 ═ 82.6%, it can be found that when the length of the output pad 121 in the first direction D1 and the second direction D2 is increased by 10% at the same time, the resistance of the output pad 121 is decreased by 17.4%. Therefore, the resistance of the output pad 121 can be effectively reduced by increasing the area of the output pad 121, and then the resistance is matched with the differentiated resistance of the lead 7 at different positions, so that the problem that the electric signal load of the signal line 5 is different due to different resistances of the lead 7, and then the display is uneven is solved, and the display effect is improved.
In an alternative embodiment of the present invention, please continue to refer to fig. 3 and 4. Along the direction that the central point 8 of the binding region 1 points to the first edge 3 and/or the second edge 4, the orthographic projection areas of the output pads 121 located in the same output pad group 12 on the plane where the light-emitting surface of the array substrate 200 is located are sequentially increased.
It will be appreciated that due to the inclusion of a plurality of leads 7 in the fan-out area 2, the longer the length of the leads 7 closer to the first edge 3 and/or the second edge 4, and therefore the greater the resistance. Therefore, when the area of the output pad 121 closer to the first edge 3 and/or the second edge 4 is larger, that is, the resistance is smaller, the output pad 121 and the resistance of the lead 7 are complementary, so that the problem that the signal strength of the signal line 5 is uneven and the display is uneven due to the difference in the lengths of the lead 7, which is caused by the difference in the resistances of the lead 7, can be alleviated, and the display quality is improved.
In an alternative embodiment of the present invention, please refer to fig. 3 and fig. 6, and fig. 6 is a schematic top view of an output pad set according to the present invention. In the same output pad group 12, the center point of the output pad 121 goes to the phaseThe distance d between the center points of the adjacent output pads 1211；
A direction pointing along the binding area 1 centre point 8 towards the first edge 3 and/or the second edge 4, d1And gradually increases.
It should be noted that the number of the output pads 121 in fig. 6 is only schematic, and does not indicate the actual number of the output pads 121 in one output pad group 12, and the specific number may be set according to the actual situation, and this is not specifically required in the present invention, and is not described in detail below.
It will be appreciated that in a direction pointing along the centre point 8 of the binding area 1 towards the first edge 3 and/or the second edge 4, d1The gradual increase may be achieved by changing the spacing between the output pads 121, by changing the width of the output pads 121 in the first direction D1, or by both.
It is understood that, by changing the area of the output pad 121, the width of the output pad 121 in the first direction D1 may be changed, the length of the output pad 121 in the second direction D2 may be changed, or both of them may be changed. In either case, d is the direction pointing along the central point 8 of the binding 1 towards the first edge 3 and/or the second edge 41When gradually increasing, compare with current design, can avoid the increase of the width of output pad group 12 on first direction D1 as far as possible to avoid carrying out adjustment by a wide margin to current technology, can reduce the technology degree of difficulty, improve production efficiency to a certain extent.
In an alternative embodiment of the invention, please refer to fig. 3, fig. 6 and fig. 10, wherein fig. 10 is a schematic top view of a driving chip according to the invention. The output pads 121 and the output pads 121 adjacent thereto have a distance D in the first direction D12，
Wherein d is2≥20μm。
It can be understood that a certain gap needs to be left between the output pads 121, so as to ensure that the output pads 121 in the same output pad group 12 are insulated from each other and do not interfere with each other. In addition, the output pads 121 on the array substrate 200 need to be connected with the output pads on the driving chip IC0121 are electrically connected to form a bonding structure (not shown), so as to transmit the electrical signal on the driver IC to the array substrate 200. However, in the bonding process, due to process variation, there is often a certain variation between the output pads 121 on the array substrate 200 and the output pads 0121 on the driver IC during the bonding process, and therefore, when the output pads 121 have a distance D in the first direction D12Less than 20 μm, the same output pad 121 may be electrically connected to two output pads 0121 at the same time during the bonding process, which may cause the electric signal transmitted to the signal line 5 to be disordered and finally to be displayed badly. Therefore, the present invention will d2The arrangement of 20 μm or more is advantageous to ensure that the adjacent output pads 121 are insulated from each other without mutual interference, and also can ensure the yield to a certain extent, thereby improving the production efficiency and reducing the production cost.
In an alternative embodiment of the present invention, please continue to refer to fig. 3. The orthographic projection area of the output bonding pad 121 on the plane of the light-emitting surface of the array substrate 200 is more than or equal to 1.5 multiplied by 10-5cm2。
As described above, the output pads 121 on the array substrate 200 need to be electrically connected to the output pads 0121 on the driver IC in a one-to-one correspondence to form a bonding structure (not shown), so as to transmit the electrical signals on the driver IC to the array substrate 200. Therefore, when the area of the output pad 121 is less than 1.5 × 10-5cm2In the meantime, after the output pad 121 and the output liner 0121 form a binding structure (not shown in the figure), since the binding area of the output pad 121 and the output liner 0121 is small, the electrical connection effect of the output pad and the output liner is poor, the electrical signal on the driver IC cannot be transmitted to the array substrate 200, and at this time, the display product cannot be normally displayed. In addition, because there is a process deviation in the bonding process, the actual bonding area is often smaller than the area of the output pad 121, and therefore, when the area of the output pad 121 is smaller than 1.5 × 10-5cm2In practice, the effective bonding area is smaller, the stable electrical connection effect between the output pad 121 and the output pad 0121 is difficult to achieve, and the signal line 5 on the array substrate 200 cannot receive the electrical signal transmitted from the driver IC, so the display area is smallerAA cannot normally display images. Meanwhile, when the area of the output pad 121 is less than 1.5 × 10-5cm2In the process, the requirement on the precision of process preparation is high, unqualified products are easy to generate, the production effect is reduced, and the production cost is improved. Therefore, the present invention sets the area of the output pad 121 to be 1.5 × 10 or more-5cm2The reliability of the electrical connection between the output pad 121 and the output pad 0121 can be ensured, the process difficulty can be reduced to a certain extent, the production efficiency can be improved, and the production cost can be reduced.
In an alternative embodiment of the invention, please refer to fig. 3 and 7, and fig. 7 is another partially enlarged schematic view of the array substrate shown in fig. 3. The array substrate 200 includes a plurality of output pad groups 12, and a plurality of output pads 121 between the plurality of output pad groups 12 are alternately arranged along the first direction D1.
It should be noted that fig. 7 only illustrates two output pad sets 12, and in other embodiments of the present invention, the array substrate 200 may further include three, four, or more output pad sets 12, which is not limited in the present invention.
It can be understood that the array substrate 200 may further include a plurality of output pad groups 12, specifically, a first output pad group 14 and a second output pad group 15, where the plurality of output pads 121 in the first output pad group 14 are arranged in parallel along the first direction D1, the plurality of output pads 121 in the second output pad group 15 are arranged in parallel along the first direction D1, and the output pads 121 located between different output pad groups 12 are alternately arranged in a staggered manner along the first direction D1. That is, in the first direction D1, the output pad 121 located in the second output pad group 15 is located at the gap between two adjacent output pads 121 in the first output pad group 14, and the lead 21 may be electrically connected to the output pad 121 located in the second output pad group 15 through the gap between two adjacent output pads 121 in the first output pad group 14, thereby reducing the difficulty of wiring.
In addition, the output pad 121 located in the second output pad group 15 may also be electrically connected to the lead 7, i.e., the third lead 73, through a side of the output pad 121 remote from the fan-out region 2. It can be seen that the length of the third wire 73 is longer than that of the remaining wires 7, so that the resistance is larger, and therefore, the area of the orthographic projection of the output pad 121 electrically connected with the third wire 73 on the plane of the light emitting surface of the array substrate 200 is larger.
In an alternative embodiment of the invention, please refer to fig. 3 and 8, and fig. 8 is another partially enlarged schematic view of the array substrate shown in fig. 3. The non-display area NA comprises a step area TJ, and a boundary line 6 is formed at the adjacent position of the step area TJ and the display area NA;
the vertical distance from the output pad 121, which is at least partially located in the same output pad group 12, to the boundary line 6 gradually increases along the direction from the center point 8 of the bonding region 1 to the first edge 3 and/or the second edge 4.
The output pad group 12 includes a fourth output pad 1214 and a fifth output pad 1215, wherein the fourth output pad 1214 is closer to the first edge 3 or the second edge 4. The vertical distance d from the end of the fourth output pad 1214 close to the boundary line 63The vertical distance d from the end of the fifth output pad 1215 close to the boundary line 6 is4，d3＞d4. It will be appreciated that the length of the leads 7 increases gradually in a direction from the centre point 8 of the bonding region 1 towards the first edge 3 and/or the second edge 4. Wherein the lead 7 comprises a fan-out trace 21, the fan-out trace 21 being located at the fan-out area 2. In the embodiment, the vertical distance from the fourth output pad 1214 to the boundary line 6 is greater than the vertical distance from the fifth output pad 1215 to the boundary line 6, so that at least a part of the fan-out trace 21 is displaced to the bonding area 1, the area for arranging the lead 7 is increased, a part of the fan-out area 2 overlaps with the bonding area 1, the height of the fan-out area 2 in the second direction D2 is reduced, and the effect of a narrow frame is achieved. At this time, however, the wire 7 electrically connected to the fourth output pad 1214 is longer than the wire 7 electrically connected to the fifth output pad 1215. By adjusting the area of the fourth output pad 1214 to make the area of the fourth output pad 1214 larger than that of the fifth output pad 1215, the problem of different resistances due to different lengths of the leads 7 can be balanced, thereby improving the display effect.
In an alternative embodiment of the invention, please refer to fig. 3 and 9, and fig. 9 is another partially enlarged schematic view of the array substrate shown in fig. 3. The non-display area NA comprises a step area TJ, and a boundary line 6 is formed at the adjacent position of the step area TJ and the display area AA;
the vertical distance of the output pads 121 at least partially located in the same output pad group 12 to the interface line 6 decreases gradually in a direction from the center point 8 of the bonding area 1 to the first edge 3 and/or the second edge 4.
It will be appreciated that the length of the lead 7 closer to the first edge 3 or the second edge 4 is longer in a direction along the center point 8 of the bonding region 1 towards the first edge 3 and/or the second edge 4. This embodiment is achieved by limiting d3＜d4That is, the fourth output pad 1214 is closer to the display area AA than the fifth output pad 1215, thereby shortening the length of the wire 7 connected to the fourth output pad 1214, and making the length of the wire 7 electrically connected to the fourth output pad 1214 closer to the length of the wire 7 electrically connected to the fifth output pad 1215, thereby reducing the resistance difference between different wires 7, and further alleviating the problem of poor display due to the resistance difference between different output pads 121 and wires 7.
Please continue to refer to fig. 3, fig. 4, fig. 7, fig. 8, fig. 9, and fig. 10. The array substrate 200 further includes at least one input pad group 13, and the input pad group 13 is located on one side of the output pad group 12 far away from the fan-out region 2. The input pad group 13 includes a plurality of input pads 131, and the input pads 131 in the same input pad group 13 are arranged in parallel along the first direction D1. The driver chip IC is correspondingly provided with an input pad 0131, and the input pad 131 and the input pad 0131 form a binding structure (not shown in the figure). The driver chip IC is supplied with power and the like through the binding structure of the input pad 131 and the input pad 0131.
Based on the unified inventive concept, the present invention further provides a driving chip IC used in cooperation with the array substrate 200 provided by the present invention, please refer to fig. 3 and fig. 10 continuously. The driving chip IC includes a plurality of pads 011, the plurality of pads 011 includes at least one output pad group 012, the output pad group 012 includes a plurality of output pads 0121, the output pads 0121 in the same output pad group 012 are arranged in a row;
the driving chip IC further includes a third edge 03 and a fourth edge 04, and the third edge 03 and the fourth edge 04 are disposed opposite to each other;
along the direction that the center point 08 of the driver IC points to the third edge 03 and/or the fourth edge 04, the area of the output pads 0121 at least partially located in the same output pad group 012 gradually increases in the orthographic projection of the plane where the driver IC is located.
It can be understood that the output pads 0121 on the driving chip IC and the output pads 121 on the array substrate 200 form a binding structure (not shown in the figure), and thus, the electrical signals on the driving chip IC can be transmitted to the array substrate 200 through the binding structure of the output pads 0121 and the output pads 121, thereby controlling the display image of the display area AA. Therefore, the present invention defines a direction pointing to the third edge 03 and/or the fourth edge 04 along the center point 08 of the driver IC, and the area of the orthographic projection of the output pads 0121 at least partially located in the same output pad group 012 on the plane where the driver IC is located is gradually increased, which is beneficial to balance the electrical signals finally transmitted to each signal line 5, and alleviates the problem of poor display caused by different loads of the signal lines 5 due to different lengths of the lead wires 7.
Further, at least one input pad group 013 is provided on the driver chip IC, and the same input pad group 013 includes a plurality of input pads 0131. The input pads 0131 on the driver chip IC are disposed corresponding to the input pads 131 on the array substrate 200, and power is provided to the driver chip IC through a binding structure between the input pads 131 and the input pads 0131.
Based on the same inventive concept, the present invention further provides a display device, please refer to fig. 11, and fig. 11 is a schematic top view of the display device according to the present invention. The display device 300 provided by the invention comprises the array substrate 200 and the driving chip IC, wherein the output pads on the array substrate 200 are arranged corresponding to the output pads on the driving chip IC. The display device 300 provided by the present application may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital camera, a navigator and the like.
According to the embodiment, the array substrate, the driving chip and the display device provided by the invention at least realize the following beneficial effects:
in the array substrate, the driving chip and the display device provided by the invention, along the direction that the central point of the binding region points to the first edge and/or the second edge, the orthographic projection area of the output bonding pads at least partially positioned in the same output bonding pad group on the plane where the light-emitting surface of the array substrate is positioned is gradually increased. Compared with the prior art, through the area that changes the output pad, change the resistance of output pad, improve because the fan-out district lead wire length difference that is connected with the output pad electricity causes the signal line load different, and then leads to showing bad problem to promote display quality, improve production efficiency, reduction in production cost.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. The array substrate is characterized by comprising a display area and a non-display area surrounding the display area, wherein the non-display area comprises a binding area;
the array substrate further comprises a first edge and a second edge, and the first edge and the second edge are oppositely arranged;
a plurality of bonding pads located within the bonding region; the plurality of pads comprise at least one output pad group, the output pad group comprises a plurality of output pads, the output pads in the same output pad group are arranged in parallel along a first direction, and the first direction is intersected with the first edge;
and along the direction of the central point of the binding region pointing to the first edge and/or the second edge, the orthographic projection area of the output bonding pads at least partially positioned in the same output bonding pad group on the plane where the light-emitting surface of the array substrate is positioned is gradually increased.
2. The array substrate of claim 1, wherein along a direction from the center point of the bonding region to the first edge and/or the second edge, the orthographic projection areas of the output pads in the same output pad group on the plane where the light-emitting surface of the array substrate is located are sequentially increased.
3. The array substrate of claim 1, wherein in the same output pad group, the distance from the center point of the output pad to the center point of the adjacent output pad is d1(ii) a A direction pointing along the binding area center point towards the first edge and/or the second edge, d1And gradually increases.
4. The array substrate of claim 1, wherein the output pads and the output pads adjacent thereto have a pitch d in the first direction2Wherein d is2≥20μm。
5. The array substrate of claim 1, wherein an orthographic projection area of the output pad on a plane where a light emitting surface of the array substrate is located is greater than or equal to 1.5 x 10-5cm2。
6. The array substrate of claim 1, comprising a plurality of the output pad groups, wherein the plurality of output pads of the plurality of the output pad groups are alternately arranged along the first direction.
7. The array substrate of claim 1, wherein the non-display region comprises a step region, and the step region and the display region are adjacent to form a boundary line; and along the direction from the center point of the binding region to the first edge and/or the second edge, the vertical distance from the output pad at least partially positioned in the same output pad group to the boundary line is gradually increased.
8. The array substrate of claim 1, wherein the non-display region comprises a step region, and the step region and the display region are adjacent to form a boundary line;
and along the direction of the central point of the binding region pointing to the first edge and/or the second edge, the vertical distance from the output pad at least partially positioned in the same output pad group to the boundary line is gradually reduced.
9. A driver chip disposed to match with the array substrate of claim 1, comprising a plurality of pads, wherein the plurality of pads comprises at least one output pad group, the output pad group comprises a plurality of output pads, and the output pads in the same output pad group are arranged in a row;
the driving chip comprises a third edge and a fourth edge, and the third edge and the fourth edge are oppositely arranged;
and along the direction of the central point of the driving chip pointing to the third edge and/or the fourth edge, the orthographic projection area of the output pads at least partially positioned in the same output pad group on the plane where the driving chip is positioned is gradually increased.
10. A display device comprising the array substrate of any one of claims 1 to 8 and the driving chip of claim 9, wherein the output pads on the array substrate are disposed corresponding to the output pads on the driving chip.
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| CN202011608029.XA CN112669756A (en) | 2020-12-29 | 2020-12-29 | Array substrate, driving chip and display device |
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Cited By (1)
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| CN114882833A (en) * | 2022-05-23 | 2022-08-09 | 上海中航光电子有限公司 | Display panel |
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