CN112669750A

CN112669750A - Array substrate, driving chip and display device

Info

Publication number: CN112669750A
Application number: CN202011593354.3A
Authority: CN
Inventors: 纪文套; 庄知龙; 黄建才
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-12-29
Filing date: 2020-12-29
Publication date: 2021-04-16
Anticipated expiration: 2040-12-29
Also published as: CN112669750B

Abstract

The invention provides an array substrate, a driving chip and a display device, wherein the array substrate comprises a display area and a step area, a boundary line is formed at the adjacent position of the display area and the step area, and the step area comprises a binding area; a plurality of pads; the plurality of pads includes at least one output pad set, the output pad set including a plurality of output pads; the plurality of output pads comprise a first pad and a second pad, the first pad and the second pad are positioned in the same output pad group, the vertical distance between the first pad and the central axis is smaller than that between the second pad and the central axis, and the vertical distance between the first pad and the boundary line is larger than that between the second pad and the boundary line; wherein, the axis passes through the center of the boundary line, and the first direction is crossed with the axis. According to the embodiment of the invention, the length of the data connecting line connected with the first pad is as close as possible to the length of the data connecting line connected with the second pad, so that the length difference among the data connecting lines is reduced, and the display quality is improved.

Description

Array substrate, driving chip and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a driving chip and a display device.

Background

In a conventional display device, a plurality of leads are required to connect signal lines of a display area with a display driver chip, for example, in order to connect the display area and an integrated circuit in a peripheral circuit area on an array substrate.

In the existing array substrate, the leads are all made of the same material, thickness and line width when being arranged, and the resistance of each lead is in direct proportion to the length thereof according to the resistance law. For a plurality of leads connected to the same chip, because the size of the chip is usually smaller than that of the display area, it is difficult to ensure that the lengths of all the leads are kept consistent when the leads are arranged, and the lengths of the leads connected with pins in the areas at two ends of the chip are usually larger than that of the leads connected with pins in the central area of the chip, so that the resistance of the leads connected with the pins in the areas at two ends of the chip is larger than that of the leads connected with the pins in the central area of the chip. When the resistance difference between different leads is large, the probability of poor display of the display device is increased, display problems such as uneven brightness and darkness under gray-scale pictures, horizontal and vertical stripes and the like are easily caused, and the reliability of the display device is reduced.

Disclosure of Invention

The invention provides an array substrate, a driving chip and a display device, which are used for reducing the length of a data connecting line connected with a second gasket, so that the length of the data connecting line connected with a first gasket is as close as possible to the length of the data connecting line connected with the second gasket, the length difference among the data connecting lines is reduced, and the display quality is improved.

The embodiment of the invention provides an array substrate, which comprises a display area and a step area, wherein a boundary line is formed at the adjacent position of the display area and the step area, the boundary line extends along a first direction, and the step area comprises a binding area;

the array substrate includes:

a plurality of pads located within the bonded region; the plurality of pads comprises at least one output pad group, the output pad group comprises a plurality of output pads, and the output pads in the same output pad group are arranged in parallel along a first direction;

the output pads comprise a first pad and a second pad, the first pad and the second pad are located in the same output pad group, the vertical distance between the first pad and the central axis is smaller than that between the second pad and the central axis, and the vertical distance between the first pad and the boundary line is larger than that between the second pad and the boundary line;

wherein the central axis passes through a center of the boundary line, and the first direction intersects the central axis.

In a second aspect, an embodiment of the present invention provides a driver chip used in cooperation with the array substrate of the first aspect, including a plurality of pins, where the plurality of pins includes at least one output pin group, the output pin group includes a plurality of output pins, and the output pins in the same output pin group are arranged in a row;

the plurality of output pins comprise a first pin and a second pin, the first pin and the second pin are positioned in the same output pin group, the vertical distance between the first pin and a central line is smaller than that between the second pin and the central line, and the vertical distance between the first pin and a first edge is larger than that between the second pin and the first edge;

the first edge is an edge of the driving chip, and the center line passes through the center of the first edge and intersects with the first edge.

In a third aspect, an embodiment of the present invention provides a display device, including the array substrate of the first aspect and the driving chip of the second aspect.

Embodiments of the present invention provide an array substrate, in which the inclination degree of a data connection line at a position closer to a central axis is smaller, and the inclination degree of a data connection line at a position farther from the central axis is larger. The length of the data link line at a position farther from the central axis is greater among the plurality of data link lines having the same projected length in the second direction. In an embodiment of the present invention, a vertical distance between the second pad and the boundary line is smaller than a vertical distance between the first pad and the boundary line. The first pad is farther from the display area and the second pad is closer to the display area. Therefore, the length of the data connecting line connected with the second pad is reduced, the length of the data connecting line connected with the first pad is as close as possible to the length of the data connecting line connected with the second pad, the length difference among the data connecting lines is reduced, and the display quality is improved.

Drawings

Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;

FIG. 2 is a schematic top view of a step region of the array substrate shown in FIG. 1;

FIG. 3 is a schematic diagram of a top view of the output pad set of the step area shown in FIG. 2;

FIG. 4 is a schematic top view of another stepped region according to an embodiment of the present invention;

FIG. 5 is a schematic top view of another stepped region according to an embodiment of the present invention;

FIG. 6 is a schematic top view of another stepped region according to an embodiment of the present invention;

FIG. 7 is a schematic top view of another stepped region according to an embodiment of the present invention;

FIG. 8 is a schematic top view of another stepped region according to an embodiment of the present invention;

FIG. 9 is a schematic top view of another stepped region according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a top view of a driving chip according to an embodiment of the present invention;

fig. 11 is a schematic top view of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic top view structure diagram of an array substrate according to an embodiment of the present invention, fig. 2 is a schematic top view structure diagram of a step region of the array substrate shown in fig. 1, fig. 3 is a schematic top view structure diagram of an output pad set of the step region shown in fig. 2, referring to fig. 1-3, the array substrate includes a display region a1 and a step region a2, a boundary line M1 is formed at a position where the display region a1 and the step region a2 are adjacent, and the boundary line M1 extends along a first direction. The step area a2 includes a binding area a 21. The array substrate includes a plurality of pads 40, and the plurality of pads 40 are located in the bonding area a 21. The plurality of pads 40 includes at least one output pad group G1, the output pad group G1 includes a plurality of output pads 41, and the output pads 41 in the same output pad group G1 are arranged in parallel in the first direction. The plurality of output pads 41 includes a first pad 411 and a second pad 412, the first pad 411 and the second pad 412 are located in the same output pad group G1, the first pad 411 is at a vertical distance X1 from the central axis M2, the second pad 412 is at a vertical distance X2 from the central axis M2, and X1 is smaller than X2. The first gasket 411 is closer to the central axis M2 and the second gasket 412 is farther from the central axis M2. The vertical distance between the first pad 411 and the boundary line M1 is Y1, the vertical distance between the second pad 412 and the boundary line M1 is Y2, and Y1 is greater than Y2. The central axis M2 passes through the center of the boundary line M1, and the first direction intersects the central axis M2. The central axis M2 extends in a second direction, the first direction intersecting the second direction. In one embodiment, the first direction is perpendicular to the second direction, and in another embodiment, the first direction may not be perpendicular to the second direction and may form an included angle greater than 0 ° and less than 90 °.

In the array substrate according to the embodiments of the present invention, the inclination degree of the data link line at a position closer to the central axis M2 is smaller, and the inclination degree of the data link line at a position farther from the central axis M2 is larger. Among the plurality of data link lines having the same projected length in the second direction, the length of the data link line at a position farther from the central axis M2 is greater. In the embodiment of the present invention, the vertical distance between the second pad 412 and the boundary line M1 is smaller than the vertical distance between the first pad 411 and the boundary line M1. The first pad 411 is located farther from the display area a1, and the second pad 412 is located closer to the display area a 1. Accordingly, the length of the data link line connected to the second pad 412 is reduced, so that the length of the data link line connected to the first pad 411 is as close as possible to the length of the data link line connected to the second pad 412, thereby reducing the length difference between the data link lines and improving the display quality.

Exemplarily, referring to fig. 1 to 3, the array substrate further includes a substrate 10, a plurality of gate lines 21 and a plurality of data lines 22, and the plurality of gate lines 21 and the plurality of data lines 22 are located on the same side of the substrate 10. The plurality of gate lines 21 extend in a first direction and are arranged in a second direction, and the plurality of data lines 22 extend in the second direction and are arranged in the first direction. The gate lines 21 and the data lines 22 are located in the display area a1 and intersect to define a plurality of pixel units 110. The step area a2 further includes a sector a22, and the sector a22 is located between the binding area a21 and the display area a 1. The array substrate further includes a plurality of data link lines 23 located in the sector a22, one end of the data link line 23 is electrically connected to the data line 22, and the other end of the data link line 23 is electrically connected to the pad 40.

Fig. 4 is a schematic top view of another step region according to an embodiment of the present invention, and referring to fig. 1 to 4, the bonding region a21 includes a central region a213, a first edge region a211, and a second edge region a 212. In the first direction, the central region a213 is located between the first edge region a211 and the second edge region a 212. The central region a213 connects the first edge region a211 and the second edge region a 212. In the same output pad group G1, the output pads 41 located in the first edge region a211 and the second edge region a212 have smaller vertical distances from the boundary line M1 as the distance from the central axis M2 is longer. Since the length of the data link line 23 connected to the output pads 41 in the first edge region a211 and the second edge region a212 is greater the length of the data link line 23 at a position farther from the central axis M2 among the plurality of data link lines 23 having the same projected length in the second direction, in the embodiment of the present invention, the output pads 41 located in the first edge region a211 and the second edge region a212 each satisfy: in the same output pad group G1, the vertical distance to the boundary line M1 is smaller as the vertical distance to the central axis M2 is farther, and the vertical distance to the boundary line M1 is larger as the vertical distance to the central axis M2 is closer, so as to gradually reduce the length difference between the data connection lines 23 connected to the output pads 41 in the first edge area a211 and the second edge area a212, thereby improving the display quality.

Alternatively, referring to fig. 1 to 4, in the same output pad group G1, the output pads 41 located in the first edge region a211 are arranged along a first straight direction L1, the output pads 41 located in the second edge region a212 are arranged along a second straight direction L2, and both the first straight direction L1 and the second straight direction L2 intersect with the central axis M2. In the embodiment of the present invention, the output pads 41 in the first edge area a211 and the second edge area a212 are arranged along a straight line, so that the difficulty in arranging the output pads 41 in the first edge area a211 and the second edge area a212 is reduced on the basis of reducing the length difference between the data connection lines 23 connected to the output pads 41 in the first edge area a211 and the second edge area a 212.

Fig. 5 is a schematic top view structure diagram of another step area according to an embodiment of the present invention, and referring to fig. 1 to 5, the data connection line 23 includes a first conductive segment 231, a second conductive segment 232, and a third conductive segment 233, and the second conductive segment 232 connects the first conductive segment 231 and the third conductive segment 233. A first end of the second wire segment 232 is connected to a second end of the first wire segment 231, and a second end of the second wire segment 232 is connected to a first end of the third wire segment 233. A first end of the first wire segment 231 is electrically connected to the output pad 41. A second end of the third wire segment 233 is connected to the data line 22. The second wire segment 232 includes an edge wire segment 2321, and a perpendicular distance between a center of the edge wire segment 2321 and the central axis M2 is greater than a perpendicular distance between a center of the second wire segment 232 except for the edge wire segment 2321 and the central axis M2. The edge wire segment 2321 is the second wire segment 232 whose center is the farthest from the perpendicular distance of the central axis M2. The included angle between the edge wire segment 2321 and the first direction is α, one end of the plurality of second wire segments 232 adjacent to the first wire segment 231 is arranged along a third linear direction L3, the included angle between the third linear direction L3 and the first direction is β, and the included angle between the first linear direction L1 and the first direction is γ, which satisfies the following conditions: gamma/alpha is more than or equal to 0.8 and less than or equal to 1.2, and gamma/beta is more than or equal to 0.8 and less than or equal to 1.2. In the embodiment of the invention, gamma/alpha is more than or equal to 0.8 and less than or equal to 1.2, and gamma/beta is more than or equal to 0.8 and less than or equal to 1.2, so that the angles of gamma and alpha are more consistent, and the angles of gamma and beta are more consistent, thereby being convenient for reducing the wiring difficulty of the data connecting line 23.

Further, α and β may also satisfy: alpha/beta is more than or equal to 0.8 and less than or equal to 1.2 so as to further reduce the wiring difficulty of the data connecting line 23.

Alternatively, referring to fig. 1 to 5, one end of the second wire segments 232 adjacent to the third wire segment 233 is arranged along a fourth linear direction L4, the fourth linear direction L4 is perpendicular to the central axis M2, and a perpendicular distance between one end of the edge wire segment 2321 adjacent to the first wire segment 231 and a straight line of the fourth linear direction L4 is H, where H is greater than or equal to 0.1mm and less than or equal to 0.3 mm. In the embodiment of the present invention, on the basis of the above-mentioned embodiment, the projection length of each second wire segment 232 in the second direction is further defined by defining the outermost edge wire segment 2321, that is, defining H being greater than or equal to 0.1mm and less than or equal to 0.3mm, so as to cooperate with γ/α being greater than or equal to 0.8 and less than or equal to 1.2 and γ/β being greater than or equal to 0.8 and less than or equal to 1.2, so as to further reduce the wiring difficulty of the data connection line 23.

Alternatively, and with reference to FIGS. 1-5, the first linear direction L1 includes an angle γ from the first direction of 10 ≦ γ ≦ 70. If γ < 10 °, the inclination angle of the first straight line direction L1 is too small, the distance that the output pad 41 moves toward the display area a1 in the first edge area a211 is too small, and the ability to reduce the difference in length between the data link lines 23 connected to the output pad 41 in the first edge area a211 is weak. If γ > 70 °, the inclination angle of the first straight line direction L1 is too large, the space occupied by the output pad 41 in the second direction is too large, the width of the binding area a21 is increased, the frame is increased, and the distance from the output pad 41 in the first edge area a211 to the display area a1 is too large, which also easily causes the length difference between the data link lines 23 connected to the output pad 41 in the first edge area a211 to increase. In the embodiment of the invention, gamma is set to be more than or equal to 10 degrees and less than or equal to 70 degrees, so that the length difference between the data connecting lines 23 connected with the output gasket 41 in the first edge area A211 is reduced, too much space of a binding area is not occupied, and the frame is reduced.

Illustratively, referring to fig. 5, the second rectilinear direction L2 includes an angle greater than or equal to 10 ° and less than or equal to 70 ° with respect to the first direction. The angle between the second linear direction L2 and the first direction may be equal to the angle between the first linear direction L1 and the first direction, or the angle between the second linear direction L2 and the first direction may not be equal to the angle between the first linear direction L1 and the first direction.

Fig. 6 is a schematic top view of another stepped region according to an embodiment of the present invention, and referring to fig. 6, the output pads 41 in the first edge region a211 are arranged along an arc, and the output pads 41 in the second edge region a212 are arranged along an arc. In the embodiment of the present invention, the output pads 41 in the first edge area a211 and the second edge area a212 are arranged along an arc, so that the difficulty in disposing the output pads 41 in the first edge area a211 and the second edge area a212 is reduced on the basis of reducing the length difference between the data connection lines 23 connected to the output pads 41 in the first edge area a211 and the second edge area a 212.

Alternatively, referring to fig. 1 to 6, in the same output pad group G1, all the output pads 41 located in the central region a213 are at the same vertical distance from the boundary line M1. In the embodiment of the present invention, the vertical distances between any two output pads 41 in the central area a213 and the boundary line M1 are the same, and the output pads 41 in the central area a213 may be arranged in a row along the first direction, thereby reducing the difficulty in disposing the output pads 41 in the central area a 213.

Fig. 7 is a schematic top view of another stepped region according to an embodiment of the present invention, and referring to fig. 7, in the same output pad group G1, the vertical distance between the output pad 41 and the boundary line M1 is smaller as the vertical distance from the central axis M2 is farther. In the embodiment of the present invention, for all output pads 41 in the same output pad group G1, the vertical distance between the output pad 41 and the boundary line M1 is smaller as the vertical distance from the central axis M2 is farther, and the vertical distance between the output pad 41 and the boundary line M1 is larger as the vertical distance from the central axis M2 is closer, so as to gradually reduce the length difference between the data connection lines 23 connected to the output pad 41 in the binding region a21, and improve the display quality.

Illustratively, referring to fig. 7, the binding region a21 includes a central region a213, a first edge region a211, and a second edge region a 212. In the first direction, the central region a213 is located between the first edge region a211 and the second edge region a 212. In the same output pad group G1, the output pads 41 located in the first edge area a211 are arranged along the first straight direction L1, the output pads 41 located in the second edge area a212 are arranged along the second straight direction L2, and both the first straight direction L1 and the second straight direction L2 intersect with the central axis M2. The output pads 41 positioned in the central area a213 are arranged in a V shape, and the output pads 41 positioned in the central area a213 adjacent to the first edge area a211 are arranged along the first straight direction L1, and the output pads 41 positioned in the central area a213 adjacent to the second edge area a212 are arranged along the second straight direction L2.

Fig. 8 is a schematic top view of another stepped region according to an embodiment of the present invention, and referring to fig. 8, in the same output pad group G1, the vertical distance between the output pad 41 and the boundary line M1 is smaller as the vertical distance from the central axis M2 is farther. All the output pads 41 in the same output pad group G1 are arranged along an arc to gradually reduce the length difference between the data link lines 23 connected to the output pads 41 in the bonding region a21, thereby improving the display quality. The arc may include, for example, a circular arc, an elliptical arc, a parabola, and the like.

Alternatively, referring to fig. 1-8, the output pad group G1 is symmetrical about the central axis M2. The output pad groups G1 located on both sides of the central axis M2 have the same number and the same arrangement position, thereby reducing the difficulty of arranging the output pad groups G1 and the arrangement positions of the matching data lines 22 and the data link lines 23.

For example, referring to fig. 1-8, display area a1, binding area a21, and sector area a22 are all symmetric about a central axis M2. The gate line 21, the data line 22 and the data link line 23 are all symmetrical about the central axis M2. The central region a213 is symmetrical about the central axis M2, and the first and second edge regions a211 and a212 are symmetrical about the central axis M2. The first and second linear directions L2 are symmetrical about the central axis M2.

Fig. 9 is a schematic top view showing a structure of another step region according to an embodiment of the present invention, and referring to fig. 9, at least one output pad group G1 includes a first output pad group G11 and a second output pad group G12, and the first output pad group G11 is located between the second output pad group G12 and the display region a 1. The output pads 41 in the first output pad group G11 are arranged in parallel in the first direction, and the output pads 41 in the second output pad group G12 are arranged in parallel in the first direction. In the first direction, the output pads 41 in the second output pad group G12 are arranged to be staggered with the output pads 41 in the first output pad group G11. In the first direction, the output pads 41 of the second output pad group G12 are located in the gaps of the adjacent two output pads 41 of the first output pad group G11, and the data link line 23 is connected to the output pads 41 of the second output pad group G12 through the gaps of the adjacent two output pads 41 of the first output pad group G11. It should be noted that, in other embodiments, at least three output pad groups G1 may be further disposed in the bonding area a21 of the array substrate, which is not limited in this embodiment of the present invention.

Alternatively, referring to fig. 9, the first output pad group G11 coincides with the extending direction of the second output pad group G12. In the embodiment of the present invention, the first output pad group G11 and the second output pad group G12 extend in the same direction, so that on one hand, the distance between the output pad 41 in the first output pad group G11 and the output pad 41 in the second output pad group G12 adjacent to the output pad group is reduced, and the length difference of the data connection line 23 connected to the two output pads 41 is reduced; on the other hand, the difficulty in arranging the first output pad group G11 and the second output pad group G12 is reduced. In other embodiments, the first output pad group G11 and the second output pad group G12 may have different arrangements.

Alternatively, referring to fig. 1-9, the plurality of pads 40 further includes at least one input pad group G2, the input pad group G2 being located on a side of the output pad group G1 away from the display area a 1. The input pad group G2 includes a plurality of input pads 42, and the input pads 42 in the same input pad group G2 are arranged in a row in the first direction. In the embodiment of the invention, the array substrate is provided with at least one output pad group G1 and at least one input pad group G2 in the bonding area a21, and the input pad group G2 is located on the side of the output pad group G1 far away from the display area a 1. The input pad group G2 may receive an external signal and transmit the external signal to the driver chip bound to the binding region a21, and the output pad group G1 may receive a data signal output by the driver chip and transmit the data signal to the data line 22 through the data connection line 23 to control the light emitting brightness of each pixel unit 110.

Referring to fig. 10, the driving chip IC includes a plurality of pins 50, the plurality of pins 50 includes at least one output pin group F1, the output pin group F1 includes a plurality of output pins 51, and the output pins 51 in the same output pin group F1 are arranged in a row. The plurality of output pins 51 include a first pin 511 and a second pin 512, the first pin 511 and the second pin 512 are located in the same output pin group F1, a vertical distance between the first pin 511 and the center line M3 is smaller than a vertical distance between the second pin 512 and the center line M3, and a vertical distance between the first pin 511 and the first edge M41 is larger than a vertical distance between the second pin 512 and the first edge M41. The first edge M41 is an edge of the driver IC, the center line M3 passes through the center of the first edge M41, and the center line M3 intersects with the first edge M41. The driving chip provided by the embodiment of the invention is matched with the array substrate in the embodiment, so that the driving chip has the beneficial effect of the array substrate in the embodiment.

Exemplarily, referring to fig. 10, the driving chip IC includes a first edge M41, a second edge M42, a third edge M43, and a fourth edge M44, the first edge M41 is opposite to the second edge M42, the third edge M43 is opposite to the fourth edge M44, the first edge M41 is adjacent to both the third edge M43 and the fourth edge M44, and the second edge M42 is adjacent to both the third edge M43 and the fourth edge M44. The third edge M43 and the fourth edge M44 are symmetrical about the center line M3. The first edge M41 and the second edge M42 may extend in a first direction, and the third edge M43 and the fourth edge M44 may extend in a second direction.

Illustratively, referring to fig. 10, the plurality of pins 50 further includes at least one input pin group F2, the input pin group F2 being located on a side of the output pin group F1 away from the first edge M41. The input pin group F2 includes a plurality of input pins 52, and the input pins 52 in the same input pin group F2 are arranged in a row in the first direction. Since the driving chips are used with the array substrate in the above embodiment, the input lead group F2 and the input pad group G2 have the same number and the same extending direction, and the output lead group F1 and the output pad group G1 have the same number and the same extending direction.

Fig. 11 is a schematic top view of a display device according to an embodiment of the present invention, and referring to fig. 1 to 11, the display device includes the array substrate and the driving chip IC in the above embodiments. The display device provided by the embodiment of the invention comprises the array substrate in the embodiment, so that the display device has the beneficial effects of the array substrate in the embodiment.

Illustratively, referring to fig. 1 to 11, the driver chip IC is bound within a binding region a21 of the array substrate. After the driver IC is bound in the binding area a21 of the array substrate, the output pads 41 of the array substrate are electrically connected with the output pins 51 of the driver IC in a one-to-one correspondence manner, and the input pads 42 of the array substrate are electrically connected with the input pins 52 of the driver IC in a one-to-one correspondence manner.

It should be noted that the display device provided in the embodiment of the present invention may further include other circuits and devices for supporting normal operation of the display device. The display device can be one of a mobile phone, a tablet personal computer, electronic paper and an electronic photo frame.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. The array substrate is characterized by comprising a display area and a step area, wherein an interface line is formed at the position where the display area is adjacent to the step area, the interface line extends along a first direction, and the step area comprises a binding area;

the array substrate includes:

2. The array substrate of claim 1, wherein the bonding region comprises a central region, a first edge region and a second edge region, and the central region is located between the first edge region and the second edge region along the first direction;

in the same output pad group, the output pads located in the first edge region and the second edge region have smaller vertical distances from the boundary line as the vertical distance from the central axis is farther.

3. The array substrate of claim 2, wherein in the same output pad group, the output pads located in the first edge region are arranged along a first straight line direction, and the output pads located in the second edge region are arranged along a second straight line direction, and both the first straight line direction and the second straight line direction intersect with the central axis.

4. The array substrate of claim 3, wherein the step area further comprises a sector area, the sector area being located between the bonding area and the display area;

the array substrate further comprises a plurality of data connecting lines positioned in the fan-shaped area, wherein each data connecting line comprises a first conducting wire segment, a second conducting wire segment and a third conducting wire segment, the second conducting wire segment is connected with the first conducting wire segment and the third conducting wire segment, and the first conducting wire segment is electrically connected with the output gasket;

the second wire section comprises an edge wire section, the vertical distance between the center of the edge wire section and the central axis is greater than the vertical distance between the center of the second wire section and the central axis except the edge wire section, the included angle between the edge wire section and the first direction is alpha, a plurality of second wire sections are arranged at the ends close to the first wire section along a third linear direction, the included angle between the third linear direction and the first direction is beta, and the included angle between the first linear direction and the first direction is gamma, so that the requirements are met:

0.8≤γ/α≤1.2；0.8≤γ/β≤1.2。

5. the array substrate of claim 4, wherein ends of the second conductive segments adjacent to the third conductive segments are arranged along a fourth linear direction, the fourth linear direction is perpendicular to the central axis, and a perpendicular distance between an end of the edge conductive segment adjacent to the first conductive segment and a straight line in the fourth linear direction is H, wherein H is greater than or equal to 0.1mm and less than or equal to 0.3 mm.

6. The array substrate of claim 3, wherein the first linear direction is at an angle γ of 10 ° γ 70 °.

7. The array substrate of claim 2, wherein all the output pads in the central region have the same vertical distance from the boundary line in the same output pad group.

8. The array substrate of claim 1, wherein the output pads are spaced a smaller vertical distance from the interface line as the vertical distance from the central axis is greater in the same output pad group.

9. The array substrate of claim 1, wherein the set of output pads are symmetric about the central axis.

10. The array substrate of claim 1, wherein the at least one output pad group comprises a first output pad group and a second output pad group, the first output pad group being located between the second output pad group and the display area;

along the first direction, output pads in the second output pad group are arranged in a staggered mode with output pads in the first output pad group.

11. The array substrate of claim 10, wherein the first output pad set and the second output pad set extend in the same direction.

12. The array substrate of claim 1, wherein the plurality of pads further comprises at least one input pad set located on a side of the output pad set remote from the display area;

the input pad group includes a plurality of input pads, and input pads in the same input pad group are arranged in a row in the first direction.

13. A driver chip for use with the array substrate of any one of claims 1-12, comprising a plurality of pins, wherein the plurality of pins comprises at least one output pin group, wherein the output pin group comprises a plurality of output pins, and the output pins in the same output pin group are arranged in a row;

14. A display device comprising the array substrate according to any one of claims 1 to 12 and the driving chip according to claim 13.