CN112667640A

CN112667640A - Routing address storage method and device

Info

Publication number: CN112667640A
Application number: CN202011639068.6A
Authority: CN
Inventors: 赵茂聪; 洪润; 何志川
Original assignee: Centec Networks Suzhou Co Ltd
Current assignee: Centec Networks Suzhou Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-04-16
Anticipated expiration: 2040-12-31
Also published as: CN112667640B

Abstract

The invention provides a method and a device for storing a routing address, wherein the method comprises the following steps: storing a plurality of routing addresses and common prefixes of the routing addresses through a multi-stage Static Random Access Memory (SRAM), wherein the last-stage SRAM in the multi-stage SRAM is used for storing the routing addresses, and the other stages of SRAMs except the last-stage SRAM in the multi-stage SRAM are used for storing the common prefixes of the routing addresses; the common prefix of the first-stage common prefix in the multi-stage SRAM is stored in a ternary content addressable memory TCAM, so that the problem of overlarge resource consumption of TCAM resources by an ALPM routing tree algorithm in the related technology can be solved, a routing address is stored through a multi-stage SRAM structure, namely the common prefix of the routing address is stored by using one-stage or multi-stage SRAMs to form cascade connection, the top-stage prefix is stored in the TCAM, and the resource consumption of the TCAM is less due to multi-stage prefix convergence.

Description

Routing address storage method and device

Technical Field

The invention relates to the field of information processing, in particular to a method and a device for storing a routing address.

Background

In the current network environment, the number of Internet Protocol (IP) addresses is huge, the number of IPv4 routing IP addresses can reach 2^32, and the number of IPv6 addresses which are put into use at present reaches 2^128 surprisingly, which puts great requirements on the storage of equipment for storing routing entries.

In the related art, routes are stored in a Static Random-Access Memory (SRAM) of a Longest mask Match (ALPM), a common Prefix of the routes stored in the same SRAM is stored, and the common Prefix is placed in a Ternary Content Addressable Memory (TCAM). Each route has a next hop, the TCAM prefix route has a next hop, and if the route of the SRAM is matched, the maximum mask route in the SRAM is preferentially used. When the prefix change of the route is large, the common prefix of the route is more, and the consumption of resources of the TCAM is overlarge, especially under the condition of IPv6 route, the prefix of IPv6 route occupies a lot of TCAM resources, and under the routing algorithm of the ALPM, if more route resources are supported, the TCAM resources can only be increased. However, in an Application Specific Integrated Circuit (ASIC) chip design for a Specific Application, TCAM in the chip is not particularly large due to its high power consumption and cost.

Aiming at the problem that the resource consumption of TCAM resources is overlarge by an ALPM routing tree algorithm in the related technology, no solution is provided.

Disclosure of Invention

The embodiment of the invention provides a method and a device for storing a routing address, which are used for at least solving the problem of overlarge resource consumption of a TCAM (traffic collision avoidance model) resource by an ALPM (alternating current packet) routing tree algorithm in the related technology.

According to an embodiment of the present invention, there is provided a routing address storage method, including:

storing a plurality of routing addresses and common prefixes of the routing addresses through a multi-stage Static Random Access Memory (SRAM), wherein the last stage of SRAM in the multi-stage SRAM is used for storing the routing addresses, and the stages of SRAM except the last stage of SRAM in the multi-stage SRAM are used for storing the common prefixes of the routing addresses; storing a common prefix of a first-level common prefix in the multi-level SRAM in a Ternary Content Addressable Memory (TCAM).

In an exemplary embodiment, the method further comprises: receiving a target message, wherein the target message carries a first target routing address; querying a TCAM Key with the highest matching degree from the TCAM; acquiring a target item with the highest matching degree from an N-level SRAM according to the TCAM Key, wherein N is an integer larger than 0; and forwarding the target message according to the target item.

In an exemplary embodiment, obtaining the target entry with the highest matching degree from the N-level SRAM according to the TCAM Key includes: when i is 1, acquiring a jth pointer and a jth behavior which point to the ith-level SRAM and correspond to the TCAM Key; acquiring an mth item with the highest matching degree with the first target routing address from the ith-level SRAM according to the jth pointer; if i is greater than 1, repeatedly executing the following steps on the N-level SRAM until the target entry with the highest matching degree is obtained from the plurality of entries corresponding to the Nth-level SRAM: acquiring a jth pointer and a jth behavior which point to the (i + 1) th-level SRAM and correspond to the ith target entry; acquiring an mth item with the highest matching degree with the first target routing address from the (i + 1) th-level SRAM according to the jth pointer; i is i +1, i is less than or equal to N, j, and m is a natural number.

In an exemplary embodiment, obtaining the mth entry with the highest matching degree with the first target routing address from the ith-level SRAM according to the jth pointer includes: if the jth pointer is valid, obtaining a plurality of corresponding entries from the ith-level SRAM according to the jth pointer; and matching the first target routing address with a plurality of entries corresponding to the ith-level SRAM one by one to obtain the mth entry with the highest matching degree with the first target routing address.

In an exemplary embodiment, forwarding the target packet according to the target entry includes: and forwarding the target message according to the outlet information and the editing information corresponding to the target item.

In an exemplary embodiment, after storing a plurality of routing addresses and a common prefix of the plurality of routing addresses by a multi-level static random access memory SRAM, the method further comprises: constructing a plurality of SRAM trees for the multi-level SRAM, wherein one SRAM tree is constructed for the one-level SRAM, each SRAM tree comprises a transition node and a load node, the effective load of each SRAM tree is the root node of the next SRAM tree, and the effective load of the last SRAM tree is the routing address; and constructing a TCAM tree for the TCAM, wherein the effective load of the TCAM tree is the root node of the first SRAM tree.

In an exemplary embodiment, after constructing a TCAM tree for the TCAM, the method further includes: receiving an update instruction, wherein the update instruction carries a second target routing address; acquiring a target node with the highest matching degree of the second target routing address according to the TCAM tree and the SRAM trees; and updating the TCAM and the storage position indicated by the target node in the multi-level SRAM.

According to still another embodiment of the present invention, there is also provided a router address storage apparatus including: a first storage module, configured to store a plurality of routing addresses and common prefixes of the routing addresses through a multi-level Static Random Access Memory (SRAM), wherein a last-level SRAM in the multi-level SRAM is used to store the routing addresses, and other-level SRAMs except the last-level SRAM in the multi-level SRAM are used to store the common prefixes of the routing addresses; and the second storage module is used for storing the common prefix of the first-stage common prefix in the multistage SRAM in a Ternary Content Addressable Memory (TCAM).

In an optional embodiment, the apparatus further includes:

the system comprises a receiving module, a sending module and a receiving module, wherein the receiving module is used for receiving a target message, and the target message carries a first target routing address;

the query module is used for querying the TCAM Key with the highest matching degree from the TCAM;

the acquisition module is used for acquiring a target item with the highest matching degree from an N-level SRAM according to the TCAM Key, wherein N is an integer larger than 0;

and the forwarding module is used for forwarding the target message according to the target entry.

In an alternative embodiment, the obtaining module 86 is further configured to: when i is 1, acquiring a jth pointer and a jth behavior which point to the ith-level SRAM and correspond to the TCAM Key; acquiring an mth item with the highest matching degree with the first target routing address from the ith-level SRAM according to the jth pointer; if i is greater than 1, repeatedly executing the following steps on the N-level SRAM until the target entry with the highest matching degree is obtained from the plurality of entries corresponding to the Nth-level SRAM: acquiring a jth pointer and a jth behavior which point to the (i + 1) th-level SRAM and correspond to the mth entry; acquiring an mth item with the highest matching degree with the first target routing address from the (i + 1) th-level SRAM according to the jth pointer; i is i +1, i is less than or equal to N, j, and m is a natural number.

In an optional embodiment, the obtaining module is further configured to: if the jth pointer is valid, obtaining a plurality of corresponding entries from the ith-level SRAM according to the jth pointer; and matching the first target routing address with a plurality of entries corresponding to the ith-level SRAM one by one to obtain the mth entry with the highest matching degree with the first target routing address.

In an optional embodiment, the forwarding module is further configured to forward the target packet according to the exit information and the editing information corresponding to the target entry.

In an optional embodiment, the apparatus further includes:

the first building module is used for building a plurality of SRAM trees for the multilevel SRAM, wherein one SRAM tree is built for the first level SRAM, each SRAM tree comprises a transition node and a load node, the effective load of each SRAM tree is the root node of the next SRAM tree, and the effective load of the last SRAM tree is the routing address;

and the second construction module is used for constructing a TCAM tree for the TCAM, wherein the effective load of the TCAM tree is the root node of the first SRAM tree.

In an optional embodiment, the apparatus further includes:

the updating receiving module is used for receiving an updating instruction, wherein the updating instruction carries a second target routing address;

the matching module is used for acquiring the target node with the highest matching degree of the second target routing address according to the TCAM tree and the SRAM trees;

and the updating processing module is used for updating the TCAM and the storage position indicated by the target node in the multi-level SRAM.

According to a further embodiment of the present invention, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above-described method embodiments when executed.

According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

According to the invention, a plurality of routing addresses and common prefixes of the routing addresses are stored through a multi-stage Static Random Access Memory (SRAM), wherein the last-stage SRAM in the multi-stage SRAM is used for storing the routing addresses, and the other stages of SRAMs except the last-stage SRAM in the multi-stage SRAM are used for storing the common prefixes of the routing addresses; the common prefix of the first-stage common prefix in the multi-stage SRAM is stored in a ternary content addressable memory TCAM, so that the problem of overlarge resource consumption of TCAM resources by an ALPM routing tree algorithm in the related technology can be solved, the routing address is stored through a multi-stage SRAM structure, namely the common prefix of the routing address is stored by using one-stage or multi-stage SRAMs to form cascade connection, the top-stage prefix is stored in the TCAM, and the resource consumption of the TCAM is less due to multi-stage prefix convergence.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

fig. 1 is a block diagram of a hardware configuration of a mobile terminal of a routing address storage method according to an embodiment of the present invention;

FIG. 2 is a flow diagram of a method of routing address storage according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a routing memory structure according to an alternative embodiment of the present invention;

FIG. 4 is a schematic diagram of a routing memory structure according to an alternative embodiment of the present invention;

FIG. 5 is a schematic diagram of a route storage structure according to an alternative embodiment of the present invention;

FIG. 6 is a schematic diagram of a chip lookup process according to an alternative embodiment of the invention;

FIG. 7 is a block diagram of a routing address storage apparatus according to an embodiment of the present invention;

FIG. 8 is a block diagram of a routing address storage apparatus according to an alternative embodiment of the present invention;

FIG. 9 is a block diagram of a routing address storage apparatus according to an alternative embodiment of the present invention;

fig. 10 is a schematic structural diagram (three) of a routing address storage device according to an alternative embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Example 1

The method provided by the first embodiment of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking a mobile terminal as an example, fig. 1 is a hardware structure block diagram of a mobile terminal of a routing address storage method according to an embodiment of the present invention, and as shown in fig. 1, the mobile terminal may include one or more processors 102 (only one is shown in fig. 1) (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and a memory 104 for storing data, and optionally, the mobile terminal may further include a transmission device 106 for a communication function and an input/output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to the routing address storage method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the mobile terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.

In this embodiment, a routing address storage method operating in the mobile terminal or the network architecture is provided, and fig. 2 is a flowchart of the routing address storage method according to the embodiment of the present invention, as shown in fig. 2, the flowchart includes the following steps:

step S202, storing a plurality of routing addresses and common prefixes of the routing addresses through a multi-level Static Random Access Memory (SRAM), wherein the last-level SRAM in the multi-level SRAM is used for storing the routing addresses, and the other-level SRAMs except the last-level SRAM in the multi-level SRAM are used for storing the common prefixes of the routing addresses;

step S204, storing the common prefix of the first-level common prefix in the multi-level SRAM in a Ternary Content Addressable Memory (TCAM).

Through the above steps S202 to S204, storing a plurality of routing addresses and common prefixes of the routing addresses by a multi-level static random access memory SRAM, wherein a last-level SRAM in the multi-level SRAM is used for storing the routing addresses, and other-level SRAMs except the last-level SRAM in the multi-level SRAM are used for storing the common prefixes of the routing addresses; the common prefix of the first-stage common prefix in the multi-stage SRAM is stored in a ternary content addressable memory TCAM, so that the problem of overlarge resource consumption of TCAM resources by an ALPM routing tree algorithm in the related technology can be solved, the routing address is stored through a multi-stage SRAM structure, namely the common prefix of the routing address is stored by using one-stage or multi-stage SRAMs to form cascade connection, the top-stage prefix is stored in the TCAM, and the resource consumption of the TCAM is less due to multi-stage prefix convergence.

In an optional embodiment, the method further comprises: receiving a target message, wherein the target message carries a first target routing address; querying a TCAM Key with the highest matching degree from the TCAM; acquiring a target item with the highest matching degree from an N-level SRAM according to the TCAM Key, wherein N is an integer larger than 0; and forwarding the target message according to the target item.

In an optional embodiment, acquiring the target entry with the highest matching degree from the N-level SRAM according to the TCAM Key includes: when i is 1, acquiring a jth pointer and a jth behavior which point to the ith-level SRAM and correspond to the TCAM Key; acquiring an mth item with the highest matching degree with the first target routing address from the ith-level SRAM according to the jth pointer; if i is greater than 1, repeatedly executing the following steps on the N-level SRAM until the target entry with the highest matching degree is obtained from the plurality of entries corresponding to the Nth-level SRAM: acquiring a jth pointer and a jth behavior which point to the (i + 1) th-level SRAM and correspond to the mth entry; acquiring an mth item with the highest matching degree with the first target routing address from the (i + 1) th-level SRAM according to the jth pointer; i is i +1, i is less than or equal to N, j, and m is a natural number.

In an optional embodiment, obtaining the mth entry with the highest matching degree with the first target routing address from the ith-level SRAM according to the jth pointer includes: if the jth pointer is valid, obtaining a plurality of corresponding entries from the ith-level SRAM according to the jth pointer; and matching the first target routing address with a plurality of entries corresponding to the ith-level SRAM one by one to obtain the mth entry with the highest matching degree with the first target routing address.

In an optional embodiment, forwarding the target packet according to the target entry includes: and forwarding the target message according to the outlet information and the editing information corresponding to the target item.

In an optional embodiment, after storing, by the multi-level static random access memory SRAM, a plurality of routing addresses and a common prefix of the plurality of routing addresses, the method further comprises: constructing a plurality of SRAM trees for the multi-level SRAM, wherein one SRAM tree is constructed for the one-level SRAM, each SRAM tree comprises a transition node and a load node, the effective load of each SRAM tree is the root node of the next SRAM tree, and the effective load of the last SRAM tree is the routing address; and constructing a TCAM tree for the TCAM, wherein the effective load of the TCAM tree is the root node of the first SRAM tree.

In an optional embodiment, after constructing a TCAM tree for the TCAM, the method further includes: receiving an update instruction, wherein the update instruction carries a second target routing address; acquiring a target node with the highest matching degree of the second target routing address according to the TCAM tree and the SRAM trees; and updating the TCAM and the storage position indicated by the target node in the multi-level SRAM.

Fig. 3 is a schematic diagram (one) of a route storage structure according to an alternative embodiment of the present invention, as shown in fig. 3, including: the system comprises a one-stage TCAM and a two-stage SRAM, wherein the storage of a whole route consists of 3 parts, the SRAM2 stores complete route information, the SRAM1 stores a prefix part of the route, and the TCAM stores a prefix of the prefix.

Fig. 4 is a schematic diagram (two) of a route storage structure according to an alternative embodiment of the present invention, as shown in fig. 4, including: the three-level ternary memory comprises a first-level TCAM and two-level SRAMs, wherein the TCAM, the SRAMs 1 and the SRAMs 2 respectively form three tries, each level of the trie is divided into an internal node (internal) and a payload (payload), and the payload is a root node of a next level trie. The payload of the last trie is the real route.

Fig. 5 is a schematic diagram (three) of a route storage structure according to an alternative embodiment of the present invention, as shown in fig. 5, including: one-level TCAM and two-level SRAM, wherein 8 ipv6 routes are issued: 1::0:0/112

1::1:0/112、1::2:0/112、1::3:0/112、2::0:0/112、2::1:0/112、2::2:0/112、2::3:0/112。

Wherein, four routes of 1: 0:0/112, 1:0/112, 1: 2:0/112 and 1: 3:0/112 occupy the same SRAM, and under the management of one tier, the common prefix of the SRAM is 1: 0: 0/110. The routes are stored in ALPM SRAM2 and the prefixes are stored in ALPM SRAM 1.

Wherein, the four routes of 2: 0:0/112, 2: 1:0/112, 2:0/112 and 2: 3:0/112 occupy the same SRAM, and under the management of one tier, the common prefix of the router is 2: 0: 0/110. The routes are stored in ALPM SRAM2 and the prefixes are stored in ALPM SRAM 1.

Two prefixes 1: 0:0/110,2: 0:0/110 are stored in ALPM SRAM1, and under one tier management, its common prefix is 0: 0/14, and the prefixes are stored in TCAM.

It can be seen that 8 routes use only one TCAM prefix, and two TCAMs are required for storage according to the only one-level ALPM SRAM algorithm.

Fig. 6 is a schematic diagram of a chip search flow according to an alternative embodiment of the present invention, as shown in fig. 6, including the following steps:

step S1, obtaining IPDA;

step S2, searching the first-stage TCAM item by item according to IPDA;

step S3, whether the matching is successful is judged, if yes, the steps S4 and S5 are executed, otherwise, the step S2 is returned to;

step S4, searching the most matched prefix in the SRAM1 according to the longest matching atom according to IPDA, and then executing S6;

step S5, export and edit;

step S6, whether the matching is successful is judged, if yes, the steps S7 and S9 are executed, otherwise, the step S4 is returned to;

s7, export and edit;

s8, judging whether a selection result is obtained according to the longest matching principle, and executing S12 if the judgment result is yes;

s9, searching the most matched route in the SRAM2 according to the longest matching principle according to IPDA;

s10, judging whether the matching is successful, if so, executing the step S11, otherwise, returning to the step S9;

s11, export and edit, followed by S8;

and S12, obtaining the result.

Searching in TCAM according to the target IP address of the incoming message, and finding the TCAM keyword key which is longest matched with the IPDA message; obtaining an entry corresponding to the pointer and the key of the pointer to the SRAM1 according to the TCAM; a behavior is generated, nexthop (exit information and editing information) is forwarded according to the behavior, and if the pointer is valid, an entry corresponding to the SRAM1 is obtained according to the pointer index; matching the corresponding table entry of the SRAM1 with the IPDA of the incoming message one by one to obtain an entry which is longest matched with the IPDA of the message; thereby to enter a pointer and nexthop; if the pointer is valid, obtaining an entry corresponding to the SRAM2 according to the pointer index; matching the corresponding table entry of the SRAM2 with the IPDA of the incoming message one by one to obtain a route which is longest matched with the IPDA of the message; thereby routing a nexthop; according to the longest match selection principle, the priority of SRAM2Nexthop is greater than that of SRAM1 Nexthop, and the priority of SRAM1 Nexthop is greater than that of TCAM Nexthop.

Example 2

According to another embodiment of the present invention, there is also provided a routing address storage apparatus, and fig. 7 is a block diagram of a routing address storage apparatus according to an embodiment of the present invention, as shown in fig. 7, including:

a first storage module 72, configured to store a plurality of routing addresses and common prefixes of the routing addresses through a multi-level static random access memory SRAM, wherein a last-level SRAM in the multi-level SRAM is used to store the routing addresses, and other levels of SRAMs except the last-level SRAM in the multi-level SRAM are used to store the common prefixes of the routing addresses;

a second storing module 74, configured to store the common prefix of the first-level common prefix in the multi-level SRAM in a ternary content addressable memory TCAM.

By the device, the problem that resource consumption of TCAM resources is overlarge by an ALPM routing tree algorithm in the related technology can be solved, the routing address is stored through the multi-stage SRAM structure, namely, the public prefix of the routing address is stored by using one-stage or multi-stage SRAM to form cascade connection, the top-stage prefix is stored in the TCAM, and the resource consumption of the TCAM is less due to multi-stage prefix convergence.

Fig. 8 is a schematic structural diagram (one) of a routing address storage apparatus according to an alternative embodiment of the present invention, and as shown in fig. 8, the apparatus further includes:

a receiving module 82, configured to receive a target packet, where the target packet carries a first target routing address;

the query module 84 is configured to query a TCAM Key with the highest matching degree from the TCAM;

an obtaining module 86, configured to obtain a target entry with the highest matching degree from an N-level SRAM according to the TCAM Key, where N is an integer greater than 0;

and a forwarding module 88, configured to forward the target packet according to the target entry.

In an alternative embodiment, the obtaining module 86 is further configured to: if the jth pointer is valid, obtaining a plurality of corresponding entries from the ith-level SRAM according to the jth pointer; and matching the first target routing address with a plurality of entries corresponding to the ith-level SRAM one by one to obtain the mth entry with the highest matching degree with the first target routing address.

In an optional embodiment, the forwarding module 88 is further configured to forward the target packet according to the egress information and the editing information corresponding to the target entry.

Fig. 9 is a schematic structural diagram (ii) of a routing address storage apparatus according to an alternative embodiment of the present invention, and as shown in fig. 9, the apparatus further includes:

a first constructing module 92, configured to construct a plurality of SRAM trees for the multi-level SRAM, where a single SRAM tree is constructed for a first-level SRAM, each SRAM tree includes a transition node and a load node, a payload of each SRAM tree is a root node of a next SRAM tree, and a payload of a last SRAM tree is the routing address;

a second constructing module 94, configured to construct a TCAM tree for the TCAM, where a payload of the TCAM tree is a root node of the first SRAM tree.

Fig. 10 is a schematic structural diagram (three) of a routing address storage apparatus according to an alternative embodiment of the present invention, and as shown in fig. 10, the apparatus further includes:

an update receiving module 102, configured to receive an update instruction, where the update instruction carries a second destination routing address;

a matching module 104, configured to obtain, according to the TCAM tree and the plurality of SRAM trees, a target node with a highest matching degree of the second target routing address;

an update processing module 106, configured to perform update processing on the TCAM and a storage location indicated by the target node in the multilevel SRAM.

Example 3

Embodiments of the present invention also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above method embodiments when executed.

Alternatively, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:

s1, storing a plurality of routing addresses and common prefixes of the routing addresses through a multi-stage Static Random Access Memory (SRAM), wherein the last-stage SRAM in the multi-stage SRAM is used for storing the routing addresses, and the other stages of SRAMs except the last-stage SRAM in the multi-stage SRAM are used for storing the common prefixes of the routing addresses;

s2, storing the common prefix of the first-level common prefix in the multi-level SRAM in a Ternary Content Addressable Memory (TCAM).

Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Example 4

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for storing routing addresses, comprising:

storing a plurality of routing addresses and common prefixes of the routing addresses through a multi-stage Static Random Access Memory (SRAM), wherein the last stage of SRAM in the multi-stage SRAM is used for storing the routing addresses, and the stages of SRAM except the last stage of SRAM in the multi-stage SRAM are used for storing the common prefixes of the routing addresses;

storing a common prefix of a first-level common prefix in the multi-level SRAM in a Ternary Content Addressable Memory (TCAM).

2. The method of claim 1, further comprising:

receiving a target message, wherein the target message carries a first target routing address;

querying a TCAM Key with the highest matching degree from the TCAM;

acquiring a target item with the highest matching degree from an N-level SRAM according to the TCAM Key, wherein N is an integer larger than 0;

and forwarding the target message according to the target item.

3. The method of claim 2, wherein obtaining the target entry with the highest matching degree from the N-level SRAM according to the TCAM Key comprises:

when i is 1, acquiring a jth pointer and a jth behavior which point to the ith-level SRAM and correspond to the TCAM Key;

acquiring an mth item with the highest matching degree with the first target routing address from the ith-level SRAM according to the jth pointer;

if i is greater than 1, repeatedly executing the following steps on the N-level SRAM until the target entry with the highest matching degree is obtained from the plurality of entries corresponding to the Nth-level SRAM:

acquiring the jth pointer and the jth behavior which point to the (i + 1) th-level SRAM and correspond to the mth entry;

acquiring an mth item with the highest matching degree with the first target routing address from the (i + 1) th-level SRAM according to the jth pointer;

i is i +1, i is less than or equal to N, j, and m is a natural number.

4. The method of claim 3, wherein obtaining the mth entry from the ith-level SRAM according to the jth pointer, the mth entry having the highest matching degree with the first target routing address comprises:

if the jth pointer is valid, obtaining a plurality of corresponding entries from the ith-level SRAM according to the jth pointer;

and matching the first target routing address with a plurality of entries corresponding to the ith-level SRAM one by one to obtain the mth entry with the highest matching degree with the first target routing address.

5. The method of claim 2, wherein forwarding the target packet according to the target entry comprises:

and forwarding the target message according to the outlet information and the editing information corresponding to the target item.

6. The method of any of claims 1 to 5, wherein after storing, by a multi-level Static Random Access Memory (SRAM), a plurality of routing addresses and a common prefix of the plurality of routing addresses, the method further comprises:

constructing a plurality of SRAM trees for the multi-level SRAM, wherein one SRAM tree is constructed for the one-level SRAM, each SRAM tree comprises a transition node and a load node, the effective load of each SRAM tree is the root node of the next SRAM tree, and the effective load of the last SRAM tree is the routing address;

and constructing a TCAM tree for the TCAM, wherein the effective load of the TCAM tree is the root node of the first SRAM tree.

7. The method of claim 6, wherein after constructing a TCAM tree for the TCAM, the method further comprises:

receiving an update instruction, wherein the update instruction carries a second target routing address;

acquiring a target node with the highest matching degree of the second target routing address according to the TCAM tree and the SRAM trees;

and updating the TCAM and the storage position indicated by the target node in the multi-level SRAM.

8. A router address storage apparatus, comprising:

a first storage module, configured to store a plurality of routing addresses and common prefixes of the routing addresses through a multi-level Static Random Access Memory (SRAM), wherein a last-level SRAM in the multi-level SRAM is used to store the routing addresses, and other-level SRAMs except the last-level SRAM in the multi-level SRAM are used to store the common prefixes of the routing addresses;

and the second storage module is used for storing the common prefix of the first-stage common prefix in the multistage SRAM in a Ternary Content Addressable Memory (TCAM).

9. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to carry out the method of any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 7.