CN116319553A - Table item searching method and network equipment - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/54—Organization of routing tables
Abstract
The specification provides a table entry searching method and network equipment, and relates to the technical field of communication. A method of table entry lookup, comprising: the processor issues a first forwarding table item to a first forwarding table of the logic chip, and issues a second forwarding table item to a second forwarding table of the logic chip; the logic chip searches a first target table item matched with the mask part in a first forwarding table according to the destination IP address of the received data message, and obtains a matching mark in the first target table item; the logic chip searches a second target table item matched with the non-mask part and the matching mark in the first target table item in a second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item; and the logic chip encapsulates and forwards the data message according to the forwarding information in the second target table entry. By the method, the table entry scale of the logic chip in the network equipment can be improved.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a table entry searching method and a network device.
Background
With the continuous development of the internet, users accessing the internet have exploded, and IPv4 (fourth version of internet protocol, internet Protocol Version) addresses are nearly exhausted, so that the whole internet starts to convert to IPv6 (sixth version of internet protocol, internet Protocol Version 6), and compared with IPv4 addresses, IPv6 addresses have longer lengths, so that more users can be identified.
However, since the length of the IPv6 address is several times longer than that of the IPv4 address, more memory space is required when storing entries containing the IPv6 address. How to record various types of entries more effectively so that the storage space in the network device can be used more reasonably is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In order to overcome the problems in the related art, the present specification provides a table entry searching method and a network device.
With reference to the first aspect of the embodiments of the present disclosure, the present application provides a table entry searching method, which is applied to a network device, where the network device includes a processor and a logic chip;
the method comprises the following steps:
the processor issues a first forwarding table item to a first forwarding table of the logic chip, and issues a second forwarding table item to a second forwarding table of the logic chip, wherein the first forwarding table item comprises a mask part of an Internet Protocol (IP) address and a matching mark, and the second forwarding table item at least comprises a non-mask part of the IP address, the matching mark and forwarding information which are the same as those in the first forwarding table item;
the logic chip searches a first target table item matched with the mask part in a first forwarding table according to the destination IP address of the received data message, and obtains a matching mark in the first target table item;
the logic chip searches a second target table item matched with the non-mask part and the matching mark in the first target table item in a second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item;
and the logic chip encapsulates and forwards the data message according to the forwarding information in the second target table entry.
Optionally, the first forwarding table is a routing table, the first forwarding table item is a routing table item, the second forwarding table is an access control list ACL, and the second forwarding table item is an ACL table item;
the processor issues a first forwarding table entry into a first forwarding table of the logic chip, and issues a second forwarding table entry into a second forwarding table of the logic chip, including:
the processor generates a software forwarding list item according to the received data message;
the processor acquires a mask part and a non-mask part of a destination IP address in a software forwarding table item according to a preset mask length;
the processor issues a routing table entry containing a mask portion and a match flag into a routing table of the logic chip, and issues an ACL table entry containing a non-mask portion, a match flag, and forwarding information into an ACL of the logic chip.
Further, the matching mark is the next hop or stream type;
the destination IP address is either an IPv6 address or an IPv4 address.
Optionally, the first forwarding table is a longest prefix matching LPM table, the first forwarding table entry is an LPM table entry, the second forwarding table is a neighbor discovery ND result table, the second forwarding table entry is a ND result table entry, and the IP address is an IPv6 address;
the processor issues a first forwarding table entry into a first forwarding table of the logic chip, and issues a second forwarding table entry into a second forwarding table of the logic chip, including:
the processor issues LPM list items comprising a mask part, a matching mark and a target interface to an LPM list of the logic chip according to a preset network segment and mask length;
when the data message is matched with the LPM table item and is not matched with the ND result table item, the logic chip sends the data message through the destination interface;
the processor carries out ND learning on the sent data message and generates a software forwarding table;
the processor acquires a non-mask part of a destination IP address in a software forwarding table item according to a preset mask length;
the processor issues a result table entry of the ND containing the non-mask portion, the match flag, and forwarding information into a result table of the ND of the logic chip.
Further, the preset mask length is 64 bits or 96 bits.
With reference to the second aspect of the embodiments of the present specification, the present application provides a network device, a processor and a logic chip, including:
the processor issues a first forwarding table item to a first forwarding table of the logic chip, and issues a second forwarding table item to a second forwarding table of the logic chip, wherein the first forwarding table item comprises a mask part of an Internet Protocol (IP) address and a matching mark, and the second forwarding table item at least comprises a non-mask part of the IP address, the matching mark and forwarding information which are the same as those in the first forwarding table item;
the logic chip searches a first target table item matched with the mask part in a first forwarding table according to the destination IP address of the received data message, and obtains a matching mark in the first target table item; searching a second target table item matched with the non-mask part and the matching mark in the first target table item in a second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item; and packaging and forwarding the data message according to the forwarding information in the second target table item.
Optionally, the first forwarding table is a routing table, the first forwarding table item is a routing table item, the second forwarding table is an access control list ACL, and the second forwarding table item is an ACL table item;
the processor is specifically used for generating a software forwarding table item according to the received data message; according to the preset mask length, a mask part and a non-mask part of a destination IP address in a software forwarding table item are obtained; and issuing a routing table item comprising a mask part and a matching mark into a routing table of the logic chip, and issuing an ACL table item comprising a non-mask part, the matching mark and forwarding information into an ACL of the logic chip.
Further, the matching mark is the next hop or stream type;
the destination IP address is either an IPv6 address or an IPv4 address.
Optionally, the first forwarding table is a longest prefix matching LPM table, the first forwarding table entry is an LPM table entry, the second forwarding table is a neighbor discovery ND result table, the second forwarding table entry is a ND result table entry, and the IP address is an IPv6 address;
the processor is specifically configured to issue an LPM table entry including a mask portion, a matching flag, and a destination interface to the LPM table of the logic chip according to a preset network segment and a mask length, so that the logic chip sends a data packet through the destination interface when the data packet matches the LPM table entry; ND learning is carried out on the sent data message, and a software forwarding table is generated; acquiring a non-mask part of a destination IP address in a software forwarding table according to a preset mask length; and issuing a result table entry of the ND containing the non-mask part, the matching mark and the forwarding information into a result table of the ND of the logic chip.
Further, the preset mask length is 64 bits or 96 bits.
In connection with a third aspect of the embodiments herein, there is provided a machine-readable storage medium storing machine-executable instructions that, when invoked and executed by a processor and a logic chip, respectively, cause the processor and the logic chip to: method steps implementing any of the above.
The technical scheme provided by the embodiment of the specification can comprise the following beneficial effects:
in this embodiment of the present disclosure, through a set mask, a hardware forwarding table entry issued to a logic chip is decomposed into a first forwarding table entry including a mask portion and a second forwarding table entry including a non-mask portion, and the first forwarding table entry and the second forwarding table entry are associated through a matching tag, and when forwarding a data packet, forwarding information is determined by respectively matching the first forwarding table entry and the second forwarding table entry, so that a space occupied by each type of forwarding table is reduced, a problem that a storage space corresponding to one type of forwarding table is insufficient due to an excessively large specification of the forwarding table is avoided, and an overall size of the forwarding table accommodated in the forwarding table is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and together with the description, serve to explain the principles of the specification.
FIG. 1 is a flow chart of a method of table entry lookup in accordance with the present application;
fig. 2 is a schematic structural diagram of a network device according to the present application;
fig. 3 is a schematic structural diagram of a network device according to an embodiment of the present application, where a routing table and an ACL table are stored in a storage space in a logic chip;
fig. 4 is a schematic structural diagram of a network device according to an embodiment of the present application, where a plurality of entries are respectively stored in a storage space in a logic chip;
FIG. 5 is a schematic diagram of another network device according to an embodiment of the present application, in which a logic chip has a memory and an SRAM formed therein;
fig. 6 is a schematic structural diagram of another network device according to an embodiment of the present application, where a memory and an SRAM in a logic chip respectively store a plurality of entries.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification.
The application provides a table entry searching method which is applied to network equipment, wherein the network equipment comprises a processor and a logic chip;
the method, as shown in fig. 1, comprises the following steps:
s100, the processor issues a first forwarding table item to a first forwarding table of the logic chip, and issues a second forwarding table item to a second forwarding table of the logic chip.
In a network device such as that shown in fig. 2, at least a processor, a logic chip, a machine-readable storage medium, and a bus connecting these components to effect communications are included. When forwarding the data message, in order to increase the forwarding speed, the forwarding table items learned by the processor can be searched for the logic chip, so that the logic chip encapsulates and forwards the data message according to forwarding information carried in the forwarding table items. The forwarding table items generated in the processor are software forwarding table items, the forwarding table items stored in the logic chip are hardware forwarding table items, and the hardware forwarding table items are issued after being processed by the processor according to the software forwarding table items and received and stored by the logic chip. The logic chip may include a processing unit for processing and forwarding a message and a storage unit for storing data (forwarding entries, etc.).
The network device may be a switch, a router, or other network devices with a message forwarding function, which is not limited herein.
The logic chip may be an FPGA (field programmable logic array, field Programmable Gate Array) or a CPLD (complex programmable logic device ), and the like, which is not limited thereto.
The software forwarding table entries generated by the processor are different according to different network environments in which the network device is located or different forwarding processes of the network device. For example, the forwarding table may include a result table matching with an applicable routing table and an ACL (access control list ) table, or matching with an applicable LPM (longest prefix match ) table and ND (neighbor discovery, neighbor Discovery protocol), and the forwarding table may be implemented by other tables or combinations of other tables. Wherein, in two different combinations, the routing table and the LPM table may be referred to as a first forwarding table, the entries thereof may be referred to as first forwarding table entries, the ACL table and the result table of ND may be referred to as second forwarding table, and the entries thereof may be referred to as second forwarding table entries. It should be noted that the LPM table and the ND result table may be collectively referred to as an ND table, where the ND result table indicates that the matching result in the table is forwarding information required for the message.
The first forwarding table entry contains a masked portion of an IP (internet protocol ) address and a matching tag, and the second forwarding table entry contains at least a non-masked portion of the IP address, the same matching tag as in the first forwarding table entry, and forwarding information. In the process of forwarding the data message, a mask is set, and a plurality of IP addresses in the same range can be divided into one network segment through the mask.
In order to split the routing table and the LPM table, reduce the capacity of one forwarding table entry in the first forwarding table, so that more forwarding table entries can be accommodated in the first forwarding table, split the destination IP address in the first forwarding table based on the mask, and split the destination IP address into a mask part and a non-mask part, where the mask part is stored in the first forwarding table, and forwarding information for implementing forwarding is not stored in the first forwarding table, so that the size of one forwarding table entry in the first forwarding table is reduced, the overall specification of the first forwarding table is improved, the non-mask part and the forwarding information are placed in the second forwarding table, and the first forwarding table and the second forwarding table are associated through the matching mark, and the association manner is recorded in the first forwarding table and the second forwarding table respectively.
When the first forwarding table is a routing table, the first forwarding table entry is a routing table entry, the second forwarding table is an access control list ACL, and the second forwarding table entry is an ACL table entry, the step S100 of the processor issuing the first forwarding table entry into the first forwarding table of the logic chip and issuing the second forwarding table entry into the second forwarding table of the logic chip includes:
S100A, the processor generates a software forwarding table item according to the received data message.
S100B, the processor acquires a mask part and a non-mask part of the destination IP address in the software forwarding table according to the preset mask length.
S100C, the processor issues a routing table entry containing a mask part and a matching mark into a routing table of the logic chip, and issues an ACL table entry containing a non-mask part, the matching mark and forwarding information into an ACL of the logic chip.
And splitting the software forwarding table items in the software forwarding table, and respectively issuing the software forwarding table items to a routing table and an ACL table of the logic chip. The two forwarding tables are respectively defined into different storage spaces in the logic chip, and because the routing table and the ACL table are divided into different storage spaces when the logic chip is planned, the information in the original partial routing table is split into the ACL table, and the two forwarding tables are associated through the matching mark, the size of one routing table item in the routing table can be reduced, the number of the routing table items in the routing table is increased, and the whole size of the forwarding table is improved.
The destination IP address in the routing table may be an IPv6 address or an IPv4 address, and may be selected according to actual needs. Because the software forwarding table item is subjected to the route learning process, the data message sent to the processor is analyzed and learned, the information such as the next hop and the stream type of the data message can be obtained, the information can be added into the routing table item and the ACL table item as a matching mark to realize the association of the routing table item and the ACL table item, and a hash value generated by hashing according to the tuple information of the data message can be selected as the matching mark, so that the method is certainly not limited to the method, and the method can be set according to actual needs.
In addition, when the first forwarding table is an LPM table, the first forwarding table entry is an LPM table entry, the second forwarding table is a ND result table, the second forwarding table entry is a ND result table entry, and the destination IP address is an IPv6 address, step S100, the processor issues the first forwarding table entry to the first forwarding table of the logic chip, and issues the second forwarding table entry to the second forwarding table of the logic chip, including:
S100D, the processor issues LPM list items comprising a mask part, a matching mark and a destination interface to the LPM list of the logic chip according to the preset network segment and the mask length,
S100E, when the data message is matched with the LPM table item and is not matched with the ND result table item, the logic chip sends the data message through the destination interface.
S100F, the processor carries out ND learning on the sent data message, and a software forwarding table is generated.
S100G, the processor acquires the non-mask part of the destination IP address in the software forwarding table according to the preset mask length.
S100H, the processor issues a result table entry of the ND containing the non-mask part, the matching mark and the forwarding information into a result table of the ND of the logic chip.
A network device is used as a gateway, and a worker can set a network segment managed by the network device when the network device is used as the gateway, wherein the network segment has a preset mask length, and the mask length of the mask is defined by the network segment managed by the network device.
Through the network segment and the mask length, the network device can determine the mask part of the network segment, and issue an LPM table entry containing the mask part, the matching mark and the destination interface to the LPM table of the logic chip, through the LPM table entry, the logic chip can receive the data message to match and send the data message to the processor for ND learning through the destination interface in the LPM table entry when the result table of ND is not matched with the result table of ND.
After the processor learns the software forwarding table according to the data message, acquiring a non-mask part of the target IP address based on the mask length, and transmitting a result table item containing the non-mask part, a matching mark and the ND of forwarding information to a result table of the ND recorded in the logic chip, so that the logic chip acquires the forwarding information to forward the data message when the received data message is respectively matched with the LPM table item and the corresponding ND result table item.
Since the specification of the ND result table has a limitation, the preset mask length is also limited, and optionally, the preset mask length is 64 bits or 96 bits, but the preset mask length is not limited to 64 bits or 96 bits, and may be set to other lengths, which is not limited thereto.
Of course, other forms and combinations of forwarding tables may be included in addition to the two modes described above, and are not described in detail herein.
When the method is implemented through the LPM table and the ND result table, the length of the IP address in the ND result table stored by the SRAM is shortened (less than 128 bits), so that the space of the ND result table is saved, the specification of the forwarding table stored in the network equipment is improved, and more reasonable application is obtained.
S101, the logic chip searches a first target table item matched with the mask part in a first forwarding table according to a destination IP address of the received data message, and obtains a matching mark in the first target table item.
After the first forwarding table entry and the second forwarding table entry are issued to the logic chip, the logic chip may search in the first forwarding table entry based on the destination IP address of the data packet, for the data packet subsequently received by the network device.
If the matching to one first target table item in the first forwarding table items can be achieved, the matching mark in the first target table item can be obtained, so that the second forwarding table item can be searched later.
S102, the logic chip searches a second target table item matched with the non-mask part and the matching mark in the first target table item in a second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item.
S103, packaging and forwarding the data message according to the forwarding information in the second target table item.
After the logic chip searches the matching mark, the data message is matched with the first forwarding table item, and the matching of the second forwarding table item can be performed. And then searching the second forwarding table according to the destination IP address and the matching mark to determine a second target table item containing the non-mask part and the matching mark.
The second target table entry also includes forwarding information, where the forwarding information includes contents such as a packaging mode and an output interface for the data packet. According to the forwarding information in the second target table entry, the logic chip can package and forward the data message, so that the data message is processed.
The following description will take an example in which a routing table and an ACL table are respectively divided in a logic chip. As shown in fig. 3, the network device includes a processor, a logic chip, and a bus connecting the processor and the logic chip, where two sections are divided in a storage space of the logic chip and used for storing a routing table and an ACL table respectively.
A method of table entry lookup, comprising:
S1A, network equipment starts route learning, and a logic chip receives a data message.
S2A, the logic chip analyzes the data message, obtains the tuple information carried in the data message, and searches in the routing table according to the tuple information.
And S3A, if the logic chip does not find a matched routing table entry in the routing table, the data message is sent to the processor, and the step S4A is skipped, and if the logic chip finds the matched routing table entry in the routing table, the step S6A is skipped.
When searching the routing table, the logic chip performs matching according to the destination IP address in the tuple information and the mask part in the routing table, if the prefix of the destination IP address can hit the mask part, it is indicated that the network device has received the message with the same tuple information as the data message (such as the data message in the same data stream) before, the matching mark in the routing table item needs to be obtained (such as analyzing the obtained stream type as the matching mark), and searches the ACL table through the matching mark and the destination IP address, if the prefix of the destination IP address fails to hit the mask part, it is indicated that the network device needs to perform routing learning when receiving the data message with the tuple information (such as the data message in the same data stream) for the first time.
S4A, the processor performs route learning according to the data message, generates a software route table item, and acquires a mask part and a non-mask part of the destination IP address based on the mask length.
As shown in fig. 3, the IPv6 address obtained by parsing the data packet in the logic chip is 2000:0000:0000:0000:0001:0001:0000:0000, and if the address is not matched in the stored routing table, the address is uploaded to the processor to perform route learning, so as to generate a software routing table entry, where the software routing table entry includes a destination IP address, a matching flag (flow classification), forwarding information (out interface and encapsulation mode), and the like. Assuming that the mask length for route learning is set to 64 bits in the processor, 96 bits of IPv6 address may be split into a 64-bit mask portion (i.e., 2000: 0000) and a 32-bit non-mask portion (i.e., 0001: 0001). Thereafter, the processor and logic chip loops to step S3A.
Subsequently, based on similar steps, the processor may also learn the software routing table entry with destination IP address 2000:0000:0000:0000:0001:0002:0000:0000, which the processor may split into a 64-bit masked portion (i.e., 2000:0000:0000:0000) and a 32-bit non-masked portion (i.e., 0001:0002).
S5A, the processor respectively transmits a route table item and an ACL table item to the logic chip, the logic chip records the route table item in the route table, and the ACL table item in the ACL table.
As shown in fig. 4, two newly issued entries are received in the routing table and the ACL table in the logic chip, namely, the routing table entry 1, the routing table entry 2, the ACL table entry 1 and the ACL table entry 2. Since the routing table entry 1 and the routing table entry 2 have the same mask portion, the routing table entry 1 and the routing table entry 2 may be combined into one routing table entry (denoted as routing table entry 1) in the process of actually storing the logic chip, and the ACL table is distinguished, that is, the non-mask portion 1 and the non-mask portion 2. In the figure, the mask portion and the non-mask portion are replaced with names, and specific address information is not shown.
Wherein, the route table item 1, the ACL table item 1 and the ACL table item 2 are associated through the matching mark 2. The ACL entry 1 further includes forwarding information 1, and the ACL entry 2 further includes forwarding information 2.
S6A, the logic chip acquires the matching mark in the routing table item, searches an ACL table based on the destination IP address and the matching mark, if the ACL table item is found, executes the step S7A, and if the ACL table item is not found, processes according to the default table item in the routing table.
In the routing table of the logic chip, a default processing action, such as sending to the processor or discarding, may be set, where the priority of the processing action is lower than the priority of the processing in the ACL table, and the processing in the ACL table forwards the data packet according to the forwarding information. If the logic chip can find an ACL entry in the ACL table, i.e. the destination IP address matches the non-mask portion and matches the same matching flag 1, it can be seen from fig. 4 that it can match the ACL entry 2.
If the ACL entry in the ACL table is not matched, the logic chip processes according to the processing action in the matched routing entry, such as discarding or uploading the processor.
And S7A, the logic chip encapsulates and forwards the data message according to the forwarding information in the matched ACL table entry.
After matching to the ACL entry 2, the logic chip can process the data message based on the forwarding information such as the outgoing interface, the encapsulation mode and the like contained in the data message, and complete forwarding.
The following describes an example of a result table in which the logic chip is divided into the LPM table and the ND, respectively. The network device, as shown in fig. 5, includes a processor, a logic chip, and a bus connecting the two. A Memory is formed in the logic chip, and an SRAM (Static Random-Access Memory) is provided. The search of the LPM table is realized in the memory, and the ND result table is stored in the SRAM.
A method of table entry lookup, comprising:
S1B, the network equipment starts ND learning, and the processor issues an LPM table entry to an LPM table of the logic chip according to the network segment and the mask length managed by the network equipment.
For example, the network device manages a network that includes 3 users, and the 3 users are 2000:0000:0000:0000:0000:0000:0000:0001/64-2000:0000:0000:0000:0000:0000:0000:0003/64 respectively. At this point, the processor generates an LPM table entry including mask portions (2000:0000:0000:0000:0000:0000:0000/64), match flags (preset to value 1), and destination interfaces (pointing to ports to which the processor is connected). After receiving the LPM table entry, the logic chip stores the LPM table entry into the memory.
S2B, the logic chip analyzes the data message, obtains the tuple information carried in the data message, and searches in the LPM table according to the tuple information.
And searching in the LPM table, namely searching the logic chip through the memory.
And S3B, if the logic chip searches the matched LPM table entry in the LPM table, acquiring a matching mark and a target interface in the LPM table entry, and jumping to the step S4B. If the logic chip does not find the matched LPM table entry in the LPM table, the logic chip indicates that the data message comes from the external network and needs to directly send to the processor for route learning.
In the LPM table of the logic chip, a default processing action, such as sending to the processor or discarding, may be further set, where the priority of the processing action is lower than the priority of processing in the result table of ND, and the processing in the result table of ND performs forwarding of the data packet according to the forwarding information.
S4B, the logic chip continues to search the ND result table. If the corresponding ND result table entry is not found, the destination interface in the LPM table entry is obtained, the data message is sent to the processor for ND learning, and S5B is skipped after learning. If the ND result table entry is found, step S6B is skipped.
When the logic chip searches the LPM table through the memory, the matching is performed according to the destination IP address in the tuple information and the mask part in the LPM table, if the prefix of the destination IP address can hit the mask part, it is indicated that the network device has previously received the message (such as the data message in the same data stream) of the same tuple information as the data message, and it is required to obtain the matching flag in the LPM table entry, and search the ND result table through the matching flag and the destination IP address.
The processor performs ND learning from the data message, generates a software ND entry, and obtains a non-mask portion of the destination IP address based on the mask length.
As shown in fig. 6, the result table entry of two ND has been recorded in the logic chip, and the non-mask portions of the destination IP address are respectively: 0000:0000:0000:0001 and 0000:0000:0000:0002.
The IP addresses of the result entries of the two NDs may share one LPM entry, i.e., 2000:0000:0000:0000, because they have the same prefix. In the figure, specific address information in an entry is replaced by a name.
After receiving the data message sent by another user, the memory in the logic chip is matched with the LPM table entry, and a matching mark and a destination interface are obtained from the LPM table entry. Through the destination interface, the logic chip sends the data message to the processor for ND learning, and generates software ND table items corresponding to 2000:0000:0000:0000:0000:0000:0003/64.
Thereafter, based on the mask length, the non-masked portion of the destination IP address in the software ND entry is obtained, i.e., 0000:0000:0000:0003.
S5B, the processor respectively transmits the LPM table entry and the ND result table entry to the logic chip, the logic chip records the LPM table entry in the LPM table, and records the ND result table entry in the ND result table.
As shown in fig. 6, three entries, i.e., LPM entry 1, LPM entry 2, LPM entry 3, and ND result entry 1, ND result entry 2, and ND result entry 3, are received in the LPM table and ND result table in the logic chip, respectively. Since LPM entry 1, LPM entry 2, and LPM entry 3 have the same mask portion, in the process of actually storing the logic chip, LPM entry 1, LPM entry 2, and LPM entry 3 may be combined into one LPM entry (denoted as LPM entry 1), and the result entries of ND may be distinguished. Thereafter, the process jumps back to step S3B.
S6B, the logic chip processes the data message according to the forwarding information in the ND result table entry.
If the destination IP address of the received data packet is 2000:0000:0000:0000:0000:0000:0000:0002, after the data packet is matched with the result table entry 2 of the ND, the logic chip can process the data packet based on forwarding information such as the egress interface and the encapsulation mode contained in the data packet, and complete forwarding.
Correspondingly, the application provides a network device, as shown in fig. 2, including: a processor and a logic chip;
the processor issues a first forwarding table item to a first forwarding table of the logic chip, and issues a second forwarding table item to a second forwarding table of the logic chip, wherein the first forwarding table item comprises a mask part of an Internet Protocol (IP) address and a matching mark, and the second forwarding table item at least comprises a non-mask part of the IP address, the matching mark and forwarding information which are the same as those in the first forwarding table item;
the logic chip searches a first target table item matched with the mask part in a first forwarding table according to the destination IP address of the received data message, and obtains a matching mark in the first target table item; searching a second target table item matched with the non-mask part and the matching mark in the first target table item in a second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item; and packaging and forwarding the data message according to the forwarding information in the second target table item.
Optionally, the first forwarding table is a routing table, the first forwarding table item is a routing table item, the second forwarding table is an access control list ACL, and the second forwarding table item is an ACL table item;
the processor is specifically used for generating a software forwarding table item according to the received data message; according to the preset mask length, a mask part and a non-mask part of a destination IP address in a software forwarding table item are obtained; and issuing a routing table item comprising a mask part and a matching mark into a routing table of the logic chip, and issuing an ACL table item comprising a non-mask part, the matching mark and forwarding information into an ACL of the logic chip.
Optionally, the matching flag is the next hop or stream type;
the destination IP address is either an IPv6 address or an IPv4 address.
Optionally, the first forwarding table is a longest prefix matching LPM table, the first forwarding table entry is an LPM table entry, the second forwarding table is a neighbor discovery ND result table, the second forwarding table entry is a ND result table entry, and the IP address is an IPv6 address;
the processor issues LPM table items comprising a mask part, a matching mark and a target interface to an LPM table of the logic chip according to a preset network segment and mask length;
when the data message is matched with the LPM table item and is not matched with the ND result table item, the logic chip sends the data message through the destination interface;
the processor learns the ND result of the sent data message and generates a software forwarding table; acquiring a non-mask part of a destination IP address in a software forwarding table according to a preset mask length; and issuing a result table entry of the ND containing the non-mask part, the matching mark and the forwarding information into a result table of the ND of the logic chip.
Optionally, the preset mask length is 64 bits or 96 bits.
Correspondingly, the application provides a machine-readable storage medium storing machine-executable instructions which, when invoked and executed by a processor and a logic chip, respectively, cause the processor and the logic chip to: method steps implementing any of the above.
That is, different machine-readable storage media may be provided in the processor and the logic chip, respectively, with the processor invoking machine-executable instructions in order to perform the method steps performed by the processor and the logic chip invoking machine-executable instructions in order to perform the method steps performed by the logic chip.
In this embodiment of the present disclosure, through a set mask, a hardware forwarding table entry issued to a logic chip is decomposed into a first forwarding table entry including a mask portion and a second forwarding table entry including a non-mask portion, and the first forwarding table entry and the second forwarding table entry are associated through a matching tag, and when forwarding a data packet, forwarding information is determined by respectively matching the first forwarding table entry and the second forwarding table entry, so that a space occupied by each type of forwarding table is reduced, a problem that a storage space corresponding to one type of forwarding table is insufficient due to an excessively large specification of the forwarding table is avoided, and an overall size of the forwarding table accommodated in the forwarding table is improved.
It is to be understood that the present description is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be made without departing from the scope thereof.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.
Claims (11)
1. The table entry searching method is characterized by being applied to network equipment, wherein the network equipment comprises a processor and a logic chip;
the method comprises the following steps:
the method comprises the steps that a processor issues a first forwarding table item into a first forwarding table of a logic chip, and issues a second forwarding table item into a second forwarding table of the logic chip, wherein the first forwarding table item comprises a mask part of an Internet Protocol (IP) address and a matching mark, and the second forwarding table item at least comprises a non-mask part of the IP address, the matching mark and forwarding information which are the same as those in the first forwarding table item;
the logic chip searches a first target table item matched with the mask part in the first forwarding table according to the destination IP address of the received data message, and obtains a matching mark in the first target table item;
the logic chip searches a second target table item matched with the non-mask part and the matching mark in the first target table item in the second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item;
and the logic chip encapsulates and forwards the data message according to the forwarding information in the second target table item.
2. The method of claim 1, wherein the first forwarding table is a routing table, the first forwarding table entry is a routing table entry, the second forwarding table is an access control list ACL, and the second forwarding table entry is an ACL table entry;
the processor issues a first forwarding table item to a first forwarding table of the logic chip, issues a second forwarding table item to a second forwarding table of the logic chip, and includes:
the processor generates a software forwarding list item according to the received data message;
the processor acquires a mask part and a non-mask part of the destination IP address in the software forwarding table according to a preset mask length;
the processor issues a routing table entry containing a mask portion and a match flag into a routing table of the logic chip, and issues an ACL table entry containing a non-mask portion, a match flag, and forwarding information into an ACL of the logic chip.
3. The method of claim 2, wherein the match flag is a next hop or a stream type;
the destination IP address is an IPv6 address or an IPv4 address.
4. The method of claim 1, wherein the first forwarding table is a longest prefix match LPM table, the first forwarding table entry is an LPM table entry, the second forwarding table is a neighbor discovery ND result table, the second forwarding table entry is an ND result table entry, and the destination IP address is an IPv6 address;
the processor issues a first forwarding table item to a first forwarding table of the logic chip, issues a second forwarding table item to a second forwarding table of the logic chip, and includes:
the processor issues LPM list items comprising a mask part, a matching mark and a target interface to an LPM list of the logic chip according to a preset network segment and mask length;
when the data message is matched with the LPM table item and is not matched with the ND result table item, the logic chip sends the data message through a destination interface;
the processor carries out ND learning on the sent data message and generates a software forwarding table;
the processor acquires a non-mask part of the destination IP address in the software forwarding table according to a preset mask length;
the processor issues a result table entry of the ND containing the non-mask portion, the match flag, and forwarding information into a result table of the ND of the logic chip.
5. The method of claim 4, wherein the predetermined mask length is 64 bits or 96 bits.
6. A network device, characterized by a processor and a logic chip, comprising:
the method comprises the steps that a processor issues a first forwarding table item into a first forwarding table of a logic chip, and issues a second forwarding table item into a second forwarding table of the logic chip, wherein the first forwarding table item comprises a mask part of an Internet Protocol (IP) address and a matching mark, and the second forwarding table item at least comprises a non-mask part of the IP address, the matching mark and forwarding information which are the same as those in the first forwarding table item;
the logic chip searches a first target table item matched with the mask part in the first forwarding table according to the destination IP address of the received data message, and obtains a matching mark in the first target table item; searching a second target table item matched with the non-mask part and the matching mark in the first target table item in the second forwarding table according to the destination IP address of the received data message and the matching mark in the first target table item; and packaging and forwarding the data message according to the forwarding information in the second target table item.
7. The network device of claim 6, wherein the first forwarding table is a routing table, the first forwarding table entry is a routing table entry, the second forwarding table is an access control list ACL, and the second forwarding table entry is an ACL table entry;
the processor is specifically configured to generate a software forwarding table item according to the received data packet; according to the preset mask length, a mask part and a non-mask part of the destination IP address in the software forwarding table item are obtained; and issuing a routing table item comprising a mask part and a matching mark into a routing table of the logic chip, and issuing an ACL table item comprising a non-mask part, the matching mark and forwarding information into an ACL of the logic chip.
8. The network device of claim 7, wherein the match flag is a next hop or a stream type;
the destination IP address is an IPv6 address or an IPv4 address.
9. The network device of claim 6, wherein the first forwarding table is a longest prefix match LPM table, the first forwarding table entry is an LPM table entry, the second forwarding table is a neighbor discovery ND result table, the second forwarding table entry is an ND result table entry, and the destination IP address is an IPv6 address;
the processor is specifically configured to issue an LPM table entry including a mask portion, a matching flag, and a destination interface to an LPM table of the logic chip according to a preset network segment and a mask length, so that the logic chip sends a data packet through the destination interface when the data packet matches the LPM table entry; ND learning is carried out on the sent data message, and a software forwarding table is generated; acquiring a non-mask part of a destination IP address in the software forwarding table item according to a preset mask length; and issuing a result table entry of the ND containing the non-mask part, the matching mark and the forwarding information into a result table of the ND of the logic chip.
10. The network device of claim 9, wherein the preset mask length is 64 bits or 96 bits.
11. A machine-readable storage medium storing machine-executable instructions that, when invoked and executed by a processor and a logic chip, respectively, cause the processor and logic chip, respectively, to: method steps of any one of claims 1-5 are carried out.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117221224A (en) * | 2023-11-09 | 2023-12-12 | 格创通信(浙江)有限公司 | Table item construction and search method and device, network equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117221224A (en) * | 2023-11-09 | 2023-12-12 | 格创通信(浙江)有限公司 | Table item construction and search method and device, network equipment and storage medium |
| CN117221224B (en) * | 2023-11-09 | 2024-02-06 | 格创通信(浙江)有限公司 | Table item construction and search method and device, network equipment and storage medium |
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