CN112653464A - Digital-to-analog conversion circuit, current calibration method, device and chip - Google Patents
Digital-to-analog conversion circuit, current calibration method, device and chip Download PDFInfo
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Abstract
The application provides a digital-to-analog conversion circuit, a current calibration method, a current calibration device and a chip, wherein the digital-to-analog conversion circuit comprises the following components: a current mirror array; the current output end of each current mirror unit is respectively connected with a current bus; the calibration unit is used for receiving an original control code corresponding to the expected current and calibrating the original control code according to the deviation information of the current mirror array to obtain a target control code, wherein the target control code comprises a target row control code and a target column control code; the row decoder is connected with the calibration unit and the current mirror array and is used for controlling the row switches of the corresponding current mirror units in each row to be opened according to the target row control code; and the column decoder is connected with the current mirror array and is used for controlling the current mirror units on a first preset row in each row of current mirror units to be opened, and controlling the column switches of the current mirror units on other rows except the first preset row in each row of current mirror units to be opened.
Description
Technical Field
The present application relates to the field of digital-to-analog conversion technologies, and in particular, to a digital-to-analog conversion circuit, a current calibration method, a current calibration device, and a chip.
Background
In the implementation of a plurality of digital-to-analog conversion circuits, the mirror current tube area of a high-precision multi-bits current mirror array is large, and the current among effective bits is deviated due to factors such as connecting parasitic resistance and process local deviation in the layout implementation process. This current deviation results in both a reduced effective number of bits for the digital-to-analog conversion circuit and a degraded performance of the integral non-linearity (INL) and the differential non-linearity (DNL). The common solution is to reduce INL by using a connection method of a row-column snake arrangement during layout design, or to split a high-order current mirror unit into a plurality of smaller current mirror units, and to eliminate process deviation by using a symmetrical layout method.
However, as the number of bits of the digital-to-analog conversion circuit increases, the number of current mirror units in rows and columns increases, which results in that the deviation between the start bit and the end bit of each row of the mirror current tube becomes larger and larger, and the deviation between rows also gradually accumulates with the increase of the number of rows of the mirror current tube, which finally affects the integral non-linear performance of the digital-to-analog conversion circuit, and the current error of the output is also larger.
Disclosure of Invention
An object of the embodiments of the present application is to provide a digital-to-analog conversion circuit, a current calibration method, a current calibration device, and a chip, which can reduce a current error caused by mismatching of current mirror array units in the digital-to-analog conversion circuit, and can reduce INL.
In a first aspect, an embodiment of the present application provides a digital-to-analog conversion circuit, including:
the current mirror array comprises a plurality of current mirror units which are arranged in P rows and Q columns, wherein P, Q are positive integers; the current output end of each current mirror unit is respectively connected with a current bus, and the plurality of current mirror units are provided with a preset opening sequence;
the calibration unit is used for receiving an original control code corresponding to the expected current and calibrating the original control code according to the deviation information of the current mirror array to obtain a target control code, wherein the target control code comprises a target row control code and a target column control code;
the row decoder is connected with the calibration unit and the current mirror array and is used for controlling row switches of the corresponding current mirror units in each row to be opened according to the target row control code;
and the column decoder is connected with the current mirror array and is used for controlling the current mirror units on a first preset row in the current mirror units in each row to be opened, and controlling the column switches of the current mirror units in other rows except the first preset row in the current mirror units in each row to be opened, wherein the current mirror units output current to the current bus when the row switches and the column switches of the current mirror units are opened.
The digital-to-analog conversion circuit provided by the embodiment of the application calibrates the original control code corresponding to the expected current by adopting the deviation information of the current mirror array so as to obtain the target control code, and then controls the corresponding current mirror unit of the current mirror array to be opened by adopting the target control code, so that the error between the actual current output by the current mirror array and the expected current is small, and the beneficial effects of reducing the error and improving the linearity can be achieved.
Optionally, in the digital-to-analog conversion circuit according to the embodiment of the present application, the preset turn-on sequence is: the opening sequence of the x row is from the 1 st row to the Q column; the opening sequence of the x +1 th row is from the Q th column to the 1 st column, wherein x is a positive integer less than P.
In the embodiment of the present application, the opening sequence of the x-th row is generally from the 1 st row to the Q-th column; the opening sequence of the x +1 th row is from the Q th column to the 1 st column, wherein x is a positive integer smaller than P, so that the snake-shaped opening sequence is realized, the linearity of the current output by the digital-to-analog conversion circuit can be improved, and the error is reduced.
Optionally, in the digital-to-analog conversion circuit according to the embodiment of the present application, the deviation information includes a row deviation coefficient and/or a column deviation coefficient, the row deviation coefficient is used to describe a deviation relationship between current mirror units between adjacent rows, and the column deviation coefficient is used to describe a deviation relationship between current mirror units between adjacent columns;
the calibration unit is used for calibrating the original control code according to the row deviation coefficient and/or the column deviation coefficient of the current mirror array to obtain a target control code.
According to the embodiment of the application, the original control code is calibrated by adopting the row deviation coefficient and/or the column deviation coefficient, the calculation efficiency can be improved, and the method and the device can be suitable for the current calibration of the large-order current mirror array.
Optionally, in the digital-to-analog conversion circuit according to the embodiment of the present application, the calibration unit is configured to calibrate the original control code according to a row deviation coefficient of the current mirror array, so as to obtain a target control code; the target control code and the original control code satisfy the following relations:
c (m + n) ═ a row _ C (m) + column _ C (n) + C; wherein C (M + N) is the target control code, where M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, a is the row deviation coefficient, and C is the inherent deviation.
Optionally, in the digital-to-analog conversion circuit according to the embodiment of the present application, the calibration unit is configured to calibrate the original control code according to a column deviation coefficient of the current mirror array, so as to obtain a target control code; the target control code and the original control code satisfy the following relations:
c (m + n) ═ row _ C (m) + b column _ C (n) + C; wherein M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, b is the column deviation coefficient, and C is the inherent deviation.
Optionally, in the digital-to-analog conversion circuit according to the embodiment of the present application, the calibration unit is configured to calibrate the original control code according to a row deviation coefficient and a column deviation coefficient of the current mirror array, so as to obtain a target control code; the target control code and the original control code satisfy the following relations:
c (m + n) ═ a row _ C (m) + b column _ C (n) + C; wherein C (M + N) is the target control code, M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, b is the column deviation coefficient, and C is the inherent deviation.
Optionally, in the digital-to-analog conversion circuit according to this embodiment of the present application, the deviation information includes a deviation value between a current output value of each of the current mirror units and a standard value;
the calibration unit is used for calibrating the original control code according to the deviation value between the current output value and the standard value of each current mirror unit to obtain a target control code.
In a second aspect, an embodiment of the present application further provides a current calibration method for calibrating a current output by a current mirror array, where the method includes:
acquiring an original control code corresponding to the expected current;
calibrating the original control code according to deviation information of the current mirror array to obtain a target control code, wherein the target control code comprises a target row control code and a target column control code;
controlling the row switches of the corresponding row current mirror units to be opened according to the target row control code;
and controlling a current mirror unit corresponding to the target column control code on a first preset row in the current mirror units of each row to be opened according to the target column control code, and controlling column switches of current mirror units of other rows except the first preset row in the current mirror units of each row to be opened, wherein current is output to a current bus when the row switch and the column switch of the current mirror units are both opened.
Optionally, in the current calibration method according to the embodiment of the present application, the deviation information includes a row deviation coefficient and/or a column deviation coefficient, the row deviation coefficient is used for describing a deviation relationship between current mirror units between adjacent rows, and the column deviation coefficient is used for describing a deviation relationship between current mirror units between adjacent columns;
the calibrating the original control code according to the deviation information of the current mirror array to obtain the target control code comprises:
and calibrating the original control code according to the row deviation coefficient and/or the column deviation coefficient of the current mirror array to obtain a target control code.
Optionally, in the current calibration method according to the embodiment of the present application, the deviation information includes a deviation value between a current output value of each current mirror unit and a standard value;
the calibrating the original control code according to the deviation information of the current mirror array to obtain the target control code comprises:
and calibrating the original control code according to the deviation value between the current output value and the standard value of each current mirror unit to obtain a target control code.
In a third aspect, an embodiment of the present application further provides a current calibration apparatus for calibrating a current output by a current mirror array, where the apparatus includes:
the acquisition module is used for acquiring an original control code corresponding to the expected current;
the calibration module is used for calibrating the original control code according to the deviation information of the current mirror array to obtain a target control code, and the target control code comprises a target row control code and a target column control code;
the first control module is used for controlling the row switches of the corresponding row current mirror units to be opened according to the target row control code;
and the second control module is used for controlling the current mirror units corresponding to the target column control code on a first preset row in the current mirror units of each row to be opened according to the target column control code, and controlling the column switches of the current mirror units of other rows except the first preset row in the current mirror units of each row to be opened, and outputting current to the current bus when the row switches and the column switches of the current mirror units are both opened.
In a fourth aspect, the present application further provides a current calibration chip, including a processor and a memory, where the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the method according to any one of the above-mentioned methods.
As can be seen from the above, the digital-to-analog conversion circuit, the current calibration method, the device and the chip provided in the embodiment of the present application calibrate the original control code corresponding to the expected current by using the deviation information of the current mirror array, so as to obtain the target control code, and then control the corresponding current mirror unit of the current mirror array to open by using the target control code, so that the error between the actual current output by the current mirror array and the expected current is small, and the beneficial effects of reducing the error and improving the linearity can be achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a digital-to-analog conversion circuit in an embodiment of the present application.
Fig. 2 is a schematic diagram illustrating an opening sequence of current mirror units of a current mirror array in an embodiment of the present application.
Fig. 3 is a flow chart of a current calibration method in an embodiment of the present application.
Fig. 4 is a flowchart of a current calibration apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that the terms "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a digital-to-analog conversion circuit in some embodiments of the present application. The digital-to-analog conversion circuit comprises: a current mirror array 101, a calibration unit 102, a row decoder 103, and a column decoder 104.
The current mirror array 101 includes a plurality of current mirror units 1011, P, Q arranged in P rows and Q columns, which are positive integers; the current output terminal of each current mirror unit 1011 is connected to a current bus 1012. The plurality of current mirror units 1011 are provided with a preset turn-on sequence. The calibration unit 102 is configured to receive an original control code corresponding to an expected current, and calibrate the original control code according to deviation information of the current mirror array 101 to obtain a target control code, where the target control code includes a target row control code and a target column control code. The row decoder 103 is connected to the calibration unit 102 and the current mirror array 101, and is configured to control row switches of the corresponding row current mirror units 1011 to be turned on according to the target row control code; the column decoder 104 is connected to the current mirror array 101, and is configured to control a current mirror unit 1011 on a preset row in the current mirror units 1011 in each row corresponding to the target column control code to be turned on, and control column switches of current mirror units 1011 in other rows than the preset row in the current mirror units 1011 in each row to be turned on, where when both the row switch and the column switch of the current mirror unit 1011 are turned on, a current is output to the current bus 1012.
According to the embodiment of the application, the original control code corresponding to the expected current is calibrated by adopting the deviation information of the current mirror array, so that the target control code is obtained, and then the corresponding current mirror unit of the current mirror array is controlled to be opened by adopting the target control code, so that the error between the actual current output by the current mirror array and the expected current is smaller, and the beneficial effects of reducing the error and improving the linearity can be achieved.
Specifically, each current mirror cell 1011 in the current mirror array 101 is provided with a row switch and a column switch, and when the row switch and the column switch of the current mirror cell 1011 are simultaneously turned on, a current is output to the current bus 1012. The preset turn-on sequence of the plurality of current mirror units 1011 of the current mirror array 101 may be: from column 1 to column Q in row x and from column Q to column 1 in row x +1, thereby achieving a serpentine opening sequence.
As shown in FIG. 2, the row numbers increase from bottom to top and the column numbers increase from left to right, and the plurality of current mirror units are turned on in sequence from row 1, column 1 to row 1, column 8, and then from row 2, column 8 to row 2, column 1. Of course, the current mirror unit 1011 may be turned on in the order of increasing column number for each row and in the order of increasing row number for each column. In the embodiment of the present application, the opening sequence of the x-th row is generally from the 1 st row to the Q-th column; the opening sequence of the x +1 th row is from the Q th column to the 1 st column, wherein x is a positive integer smaller than P, so that the snake-shaped opening sequence is realized, the linearity of the current output by the digital-to-analog conversion circuit can be improved, and the error is reduced.
The calibration unit 102 may be implemented by a chip or a microprocessor. The desired current is the current that is required from the current bus output of the digital to analog conversion circuit. The original control code and the target control code are binary codes. The original control code includes m-bit original row control code and n-bit original column control code. For example, when the original control code is 00010011, the m-bit original row control code is 0001, and the n-bit original column control code is 0011. The target control code includes M-bit row control code and N-bit column control code. The value of the m-bit original row control code 0001 is the row number to be fully opened according to the preset opening sequence (in this example, the row number to be fully opened is row number 1, that is, the row number 0 and the row number 1 are to be fully opened). The value of the n-bit original column control code 0011 is: the column number of the current mirror cell of m +1 rows of the plurality of current mirror cells that are turned on.
The deviation information may include the row deviation coefficient and/or the column deviation coefficient, that is, the deviation information may include only the row deviation coefficient, only the column deviation coefficient, or both the row deviation coefficient and the column deviation coefficient. The row deviation coefficient is used to describe the deviation relationship between the current mirror units 1011 between adjacent rows, and the column deviation coefficient is used to describe the deviation relationship between the current mirror units 1011 between adjacent columns. The deviation value between any two adjacent rows is constant, that is, when two current mirror units of the same column number of two adjacent rows are turned on, the current difference output to the current bus is a fixed value, and of course, a certain error is allowed to exist. The offset value between any two adjacent columns is constant, that is, when two current mirror units of the same row number of the two adjacent columns are opened, the current difference output to the current bus is a fixed value, and of course, a certain error is allowed to exist. For example, in fig. 2, from a low row to a high row, the offset between two adjacent rows is 0.08 ma; the offset between two adjacent columns from low to high columns is 0.08 ma. From bottom to top, the current output values of a plurality of current mirror units of the same column number of the plurality of rows are linearly reduced. From left to right, the current output values of a plurality of current mirror units of the same row number of the plurality of rows are linearly reduced.
In some embodiments, the calibration unit 102 is configured to calibrate the original control code according to a row deviation coefficient and a column deviation coefficient of the current mirror array 101 to obtain a target control code; the target control code and the original control code satisfy the following relational expression: c (m + n) ═ a row _ C (m) + b column _ C (n) + C; wherein C (M + N) is the target control code, M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, b is the column deviation coefficient, and C is the inherent deviation. Wherein M is M. For example, C may be an error caused by parasitic capacitance and parasitic resistance of MOS transistors in the current mirror array. The inherent deviation can be determined by a plurality of tests and can be eliminated to a certain extent by the calibration formula.
According to the embodiment of the application, the original control code is calibrated by adopting the row deviation coefficient and the column deviation coefficient, so that the calculation efficiency can be improved, and the method and the device can be suitable for the current calibration of a large-order current mirror array. In the process of calibrating by adopting the formula, the digit of the calibrated target control code after the decimal point can be eliminated by adopting an upward rounding mode or a downward rounding mode.
In some embodiments, the calibration unit 102 is configured to calibrate the original control code according to a row deviation coefficient of the current mirror array to obtain a target control code; the target control code and the original control code satisfy the following relations: c (m + n) ═ a row _ C (m) + column _ C (n) + C; wherein C (M + N) is the target control code, where M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, a is the row deviation coefficient, and C is the inherent deviation. Wherein N is N.
In some embodiments, the calibration unit 102 is configured to calibrate the original control code according to a column deviation coefficient of the current mirror array 101 to obtain a target control code; the target control code and the original control code satisfy the following relations: c (m + n) ═ row _ C (m) + b column _ C (n) + C; wherein M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, b is the column deviation coefficient, and C is the inherent deviation.
It will be appreciated that in some embodiments, the deviation information comprises a deviation value between the current output value of each said current mirror unit 1011 and a standard value. The calibration unit 102 is configured to calibrate the original control code according to a deviation value between a current output value and a standard value of each current mirror unit, so as to obtain a target control code. For example, if the expected current value requires w current mirror units to be turned on, but according to the deviation between the current output value of each current mirror unit and the standard value, w +3 current mirror units need to be turned on to reach the allowable error range with the expected current value.
Referring to fig. 3, fig. 3 is a flowchart illustrating a current calibration method according to some embodiments of the present disclosure. The method is used in the calibration unit of the digital-to-analog conversion circuit in the above embodiment, and the method is used for calibrating the current output by the current mirror array. The calibration unit may be a chip or a microprocessor. The method comprises the following steps:
s201, acquiring an original control code corresponding to the expected current.
S202, calibrating the original control code according to deviation information of the current mirror array to obtain a target control code, wherein the target control code comprises a target row control code and a target column control code.
And S203, controlling the row switches of the corresponding row current mirror units to be opened according to the target row control code.
And S204, controlling a current mirror unit corresponding to the target column control code on a first preset row in the current mirror units of each row to be opened according to the target column control code, and controlling column switches of current mirror units of other rows except the first preset row in the current mirror units of each row to be opened, wherein when the row switch and the column switch of the current mirror unit are both opened, current is output to a current bus.
In step S201, since the number of current mirror units to be turned on is different for different current values, each expected current corresponds to an original control code, which includes an original row control code and an original column control code. Controlling the corresponding current mirror unit to open according to the original row control code and the original column control code may cause a large error, and therefore, the original control code needs to be calibrated.
Wherein, in this step S202, if the deviation information includes a row deviation coefficient and/or a column deviation coefficient, the row deviation coefficient is used for describing the deviation relationship between the current mirror units between the adjacent rows, and the column deviation coefficient is used for describing the deviation relationship between the current mirror units between the adjacent columns. Then, this step S202 includes: and calibrating the original control code according to the row deviation coefficient and/or the column deviation coefficient of the current mirror array to obtain a target control code. Of course, the three possible calibration methods are fully described in the above embodiments, and therefore, are not described herein.
In some embodiments, the deviation information includes a deviation value between the current output value of each of the current mirror units and a standard value; the step S202 includes: and calibrating the original control code according to the deviation value between the current output value and the standard value of each current mirror unit to obtain a target control code. For example, if the expected current value requires w current mirror units to be turned on, but according to the deviation between the current output value of each current mirror unit and the standard value, w +3 current mirror units need to be turned on to reach the allowable error range with the expected current value.
Referring to fig. 4, fig. 4 is a structural diagram of a current calibration device according to some embodiments of the present disclosure. In the calibration unit for the digital-to-analog conversion circuit in the above embodiment, the current calibration device is used to calibrate the current output by the current mirror array. The calibration unit may be a chip or a microprocessor. The device comprises: an acquisition module 301, a calibration module 302, a first control module 303, and a second control module 304.
The obtaining module 301 is configured to obtain an original control code corresponding to an expected current. The number of current mirror units to be turned on is different for different current values, so that each expected current corresponds to an original control code, which includes an original row control code and an original column control code. Controlling the corresponding current mirror unit to open according to the original row control code and the original column control code may cause a large error, and therefore, the original control code needs to be calibrated.
The calibration module 302 is configured to calibrate the original control code according to the deviation information of the current mirror array to obtain a target control code, where the target control code includes a target row control code and a target column control code; if the deviation information comprises a row deviation factor for describing the deviation relationship between the current mirror cells between adjacent rows and/or a column deviation factor for describing the deviation relationship between the current mirror cells between adjacent columns. Then, the calibration module 302 is configured to: and calibrating the original control code according to the row deviation coefficient and/or the column deviation coefficient of the current mirror array to obtain a target control code. Of course, the three possible calibration methods are fully described in the above embodiments, and therefore, are not described herein.
In some embodiments, the deviation information includes a deviation value between the current output value of each of the current mirror units and a standard value; the calibration module 302 is configured to calibrate the original control code according to a deviation value between a current output value and a standard value of each current mirror unit, so as to obtain a target control code. For example, if the expected current value requires w current mirror units to be turned on, but according to the deviation between the current output value of each current mirror unit and the standard value, w +3 current mirror units need to be turned on to reach the allowable error range with the expected current value.
The first control module 303 is configured to control, according to the target row control code, a row switch of each corresponding row current mirror unit to be turned on;
the second control module 304 is configured to control, according to the target column control code, a current mirror unit corresponding to the target column control code on a first preset row in each row of current mirror units to be turned on, and control column switches of current mirror units in other rows than the first preset row in each row of current mirror units to be turned on, where when both the row switch and the column switch of the current mirror unit are turned on, current is output to the current bus.
In a fourth aspect, the present application further provides a current calibration chip, which includes a processor and a memory, where the memory stores computer readable instructions, and when the computer readable instructions are executed by the processor, the method according to any of the above embodiments is performed.
The digital-to-analog conversion circuit, the current calibration method, the current calibration device and the chip provided by the embodiment of the application calibrate the original control code corresponding to the expected current by adopting the deviation information of the current mirror array, so that the target control code is obtained, and then the target control code is adopted to control the corresponding current mirror unit of the current mirror array to be opened, so that the error between the actual current output by the current mirror array and the expected current is smaller, and the beneficial effects of reducing the error and improving the linearity can be achieved.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A digital-to-analog conversion circuit, comprising:
the current mirror array comprises a plurality of current mirror units which are arranged in P rows and Q columns, wherein P, Q are positive integers; the current output end of each current mirror unit is respectively connected with a current bus, and the plurality of current mirror units are provided with a preset opening sequence;
the calibration unit is used for receiving an original control code corresponding to the expected current and calibrating the original control code according to the deviation information of the current mirror array to obtain a target control code, wherein the target control code comprises a target row control code and a target column control code;
the row decoder is connected with the calibration unit and the current mirror array and is used for controlling row switches of the corresponding current mirror units in each row to be opened according to the target row control code;
and the column decoder is connected with the current mirror array and is used for controlling the current mirror units on a first preset row in the current mirror units in each row to be opened, and controlling the column switches of the current mirror units in other rows except the first preset row in the current mirror units in each row to be opened, wherein the current mirror units output current to the current bus when the row switches and the column switches of the current mirror units are opened.
2. The digital-to-analog conversion circuit according to claim 1, wherein the preset turn-on sequence is: the opening sequence of the x row is from the 1 st row to the Q column; the opening sequence of the x +1 th row is from the Q th column to the 1 st column, wherein x is a positive integer less than P.
3. The digital-to-analog conversion circuit according to claim 1, wherein the deviation information comprises a row deviation coefficient and/or a column deviation coefficient, the row deviation coefficient is used for describing a deviation relationship between current mirror units between adjacent rows, and the column deviation coefficient is used for describing a deviation relationship between current mirror units between adjacent columns;
the calibration unit is used for calibrating the original control code according to the row deviation coefficient and/or the column deviation coefficient of the current mirror array to obtain a target control code.
4. The DAC circuit of claim 3, wherein the calibration unit is configured to calibrate the original control code according to a line deviation coefficient of the current mirror array to obtain a target control code; the target control code and the original control code satisfy the following relations:
c (m + n) ═ a row _ C (m) + column _ C (n) + C; wherein C (M + N) is the target control code, where M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, a is the row deviation coefficient, and C is the inherent deviation.
5. The DAC circuit of claim 3, wherein the calibration unit is configured to calibrate the original control code according to a column deviation coefficient of the current mirror array to obtain a target control code; the target control code and the original control code satisfy the following relations:
c (m + n) ═ row _ C (m) + b column _ C (n) + C; wherein M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, b is the column deviation coefficient, and C is the inherent deviation.
6. The DAC circuit of claim 3, wherein the calibration unit is configured to calibrate the original control code according to a row offset coefficient and a column offset coefficient of the current mirror array to obtain a target control code; the target control code and the original control code satisfy the following relations:
c (m + n) ═ a row _ C (m) + b column _ C (n) + C; wherein C (M + N) is the target control code, M is the number of bits of the target row control code, N is the number of bits of the target column control code, row _ C (M) is the M-bit original row control code, column _ C (N) is the N-bit original column control code, b is the column deviation coefficient, and C is the inherent deviation.
7. The digital-to-analog conversion circuit according to claim 1, wherein the deviation information includes a deviation value between a current output value of each of the current mirror units and a standard value;
the calibration unit is used for calibrating the original control code according to the deviation value between the current output value and the standard value of each current mirror unit to obtain a target control code.
8. A method of current calibration for calibrating a current output by a current mirror array, the method comprising:
acquiring an original control code corresponding to the expected current;
calibrating the original control code according to deviation information of the current mirror array to obtain a target control code, wherein the target control code comprises a target row control code and a target column control code;
controlling the row switches of the corresponding row current mirror units to be opened according to the target row control code;
and controlling a current mirror unit corresponding to the target column control code on a first preset row in the current mirror units of each row to be opened according to the target column control code, and controlling column switches of current mirror units of other rows except the first preset row in the current mirror units of each row to be opened, wherein current is output to a current bus when the row switch and the column switch of the current mirror units are both opened.
9. The current calibration method according to claim 8, wherein the deviation information comprises row deviation coefficients for describing deviation relationships between current mirror cells between adjacent rows and/or column deviation coefficients for describing deviation relationships between current mirror cells between adjacent columns;
the calibrating the original control code according to the deviation information of the current mirror array to obtain the target control code comprises:
and calibrating the original control code according to the row deviation coefficient and/or the column deviation coefficient of the current mirror array to obtain a target control code.
10. The method according to claim 9, wherein the deviation information includes a deviation value between the current output value of each of the current mirror units and a standard value;
the calibrating the original control code according to the deviation information of the current mirror array to obtain the target control code comprises:
and calibrating the original control code according to the deviation value between the current output value and the standard value of each current mirror unit to obtain a target control code.
11. A current calibration apparatus for calibrating current output by a current mirror array, the apparatus comprising:
the acquisition module is used for acquiring an original control code corresponding to the expected current;
the calibration module is used for calibrating the original control code according to the deviation information of the current mirror array to obtain a target control code, and the target control code comprises a target row control code and a target column control code;
the first control module is used for controlling the row switches of the corresponding row current mirror units to be opened according to the target row control code;
and the second control module is used for controlling the current mirror units corresponding to the target column control code on a first preset row in the current mirror units of each row to be opened according to the target column control code, and controlling the column switches of the current mirror units of other rows except the first preset row in the current mirror units of each row to be opened, and outputting current to the current bus when the row switches and the column switches of the current mirror units are both opened.
12. A current calibration chip comprising a processor and a memory, the memory storing computer readable instructions which, when executed by the processor, perform the method of any one of claims 8 to 10.
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