CN112653432A

CN112653432A - Power supply jitter prevention circuit with memory function

Info

Publication number: CN112653432A
Application number: CN202011534890.6A
Authority: CN
Inventors: 付春国; 饶忠; 朱兴双
Original assignee: Shanghai Shiningic Electronic Technology Co ltd
Current assignee: Shanghai Shiningic Electronic Technology Co ltd
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2021-04-13

Abstract

A power supply jitter prevention circuit with a memory function comprises a logic latch circuit, a clock circuit, an internal power supply module and an unlocking circuit; the input end of the internal power supply module is connected with a power supply VDD, and the output end of the internal power supply module is connected with the power supply end of the logic latch circuit; the logic latch circuit inputs and outputs data under the control of the clock circuit; when the power supply voltage of the power supply VDD is lower than a preset threshold value when the power supply voltage is down, the internal power supply module outputs a power supply required by a power supply end V end of the logic latch circuit, the unlocking circuit latches data entering the logic latch circuit within a period after the power supply VDD is down, and a reset signal is output when the power supply VDD works normally. Therefore, the invention realizes that the electric signal has the memory function under the condition of short power-off of the power supply VDD, and ensures that the data is not lost; in addition, the circuit of the invention has simple structure, strong anti-interference capability, wide application and strong practicability, and is suitable for various non-input capacitance circuits.

Description

Power supply jitter prevention circuit with memory function

Technical Field

The invention belongs to the technical field of lighting circuits, and relates to a power supply jitter prevention circuit with a memory function.

Background

Consumer electronics are growing rapidly, technology is developing more rapidly, electronic integration is higher and higher, and chip cost is lower and lower. Under the premise, the cost of peripheral components of the electronic product is more and more significant in the whole electronic product, such as resistance, capacitance, inductance and the like. In order to reduce the cost, it has been proposed to reduce or eliminate the filter capacitor as much as possible in the development of more and more consumer electronic products.

With the popularization of portable electronic products such as mobile phones, tablet computers, mobile power supplies and the like, lithium batteries are widely used as power supply devices. However, due to portability, the portable electronic product has abnormal conditions such as collision and falling in application, and most of the power supply batteries are connected in a contact manner by using springs, thimbles and the like in application, so that the power supply is easily interrupted briefly.

It is clear to those skilled in the art that after the power is cut off, the chip is easily reset, and especially under the condition of no power supply filter capacitor, the discontinuity of the chip operation is caused, which causes the poor experience of the user.

Therefore, how to deal with the wide application requirement range of the power supply anti-jitter design and obtain a reliable power supply anti-jitter technology with strong applicability becomes a problem to be discussed urgently in the industry.

Disclosure of Invention

In order to solve the technical problems, the invention provides a brand-new power supply jitter prevention circuit with a memory function and a method, which can effectively solve the problem of LED flicker or turn-off under over-temperature protection in LED constant-current application, and can achieve the balance of chip temperature and LED illumination by reducing output current after the chip temperature rises, thereby avoiding the problems of LED flicker and turn-off.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a power supply jitter prevention circuit with a memory function comprises a logic latch circuit, a clock circuit and an internal power supply module; the input end of the internal power supply module is connected with a power supply VDD, and the output end of the internal power supply module is connected with the power supply end of the logic latch circuit; the logic latch circuit is used for inputting and outputting data under the control of the clock circuit; when the power supply voltage of a power supply VDD is lower than a preset threshold value after power failure, the internal power supply module outputs a power supply required by a power supply end V end of the logic latch circuit, and data entering the logic latch circuit in a period after the power supply VDD is powered down is latched.

Furthermore, the internal power supply module circuit comprises a P-type MOS tube and a capacitor C; the drain electrode of the P-type MOS tube is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS tube are connected with one end of a capacitor C together in a short circuit mode, the other end of the capacitor C is grounded, and the grid electrode of the P-type MOS tube is grounded.

Further, the internal power module circuit comprises a P-type MOS tube and a capacitor C; the drain electrode of the P-type MOS tube is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS tube are connected with one end of a capacitor C together in a short circuit mode, the other end of the capacitor C is grounded, and the grid electrode of the P-type MOS tube is connected with a divided voltage.

Further, the internal power module circuit comprises a P-type MOS transistor MP1, a P-type MOS transistor MP2, a P-type MOS transistor MP3, and a capacitor C; the drain electrode of the P-type MOS transistor MP1 is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS transistor MP1 are connected with one end of the capacitor C in a short circuit mode, the other end of the capacitor C is grounded, the drain electrode of the P-type MOS transistor MP2 is connected with the source electrode of the P-type MOS transistor MP3, and the drain electrode of the P-type MOS transistor MP3 is connected with the ground end; the source electrode of the P-type MOS tube MP2 is connected with the V end.

Further, the logic latch module comprises an RS trigger, a D trigger, a latch and/or a RAM.

Further, the clock circuit includes a nand gate or a nor gate for preventing the clock CLK signal from changing in a low voltage state or during a power-up period.

Furthermore, the power supply jitter prevention circuit with the memory function further comprises an unlocking circuit, wherein the unlocking circuit comprises an anti-jitter detection unit, a rising edge detection unit, a latch unit, a director and an nor gate, and is used for preventing the logic latch circuit from being reset in a low-voltage state or a power-on period and ensuring that the logic latch module outputs a reset signal when the logic latch module works normally.

According to the technical scheme, the power supply jitter prevention circuit with the memory function can enable an electric signal to have the memory function under the condition that the power supply VDD is powered off for a short time, and data are guaranteed not to be lost; in addition, the circuit of the invention has simple structure, strong anti-interference capability, wide application and strong practicability, and is suitable for various non-input capacitance circuits.

Drawings

FIG. 1 is a schematic diagram of a circuit structure for preventing power jitter with memory function according to an embodiment of the present invention

FIG. 2 is a schematic diagram showing a voltage waveform at V-terminal when power VDD is momentarily jittered to a 0V signal according to an embodiment of the present invention

FIG. 3 is a schematic circuit diagram of an internal power module according to an embodiment of the invention

Detailed Description

The following describes the embodiments of the present invention in further detail with reference to the accompanying fig. 1-3.

Referring to fig. 1, fig. 1 is a schematic diagram of a power jitter prevention circuit with memory function according to an embodiment of the present invention. As shown in the figure, the power supply jitter prevention circuit with the memory function is realized by adopting a pure CMOS circuit design method instead of a memory storage unit mode; the power supply jitter prevention circuit with the memory function comprises a logic latch circuit 4, a clock circuit 3, an internal power supply module 1, an unlock circuit 2 and a power supply end VDD.

The input end of the internal power supply module 1 is connected with a power supply VDD, and the output end of the internal power supply module is connected with the power supply end of the logic latch circuit 4; the logic latch circuit 4 inputs and outputs data under the control of the clock circuit; when the power supply voltage of the power supply VDD is lower than a preset threshold value after power failure, the internal power supply module outputs a power supply required by the power supply end of the logic latch circuit, and data entering the logic latch circuit 4 in a period after the power supply VDD is powered down is latched.

Referring to fig. 2, fig. 2 is a schematic diagram of a voltage waveform at V when the power VDD is momentarily jittered to a 0V signal according to an embodiment of the present invention.

It is clear to a person skilled in the art that a certain supply voltage is necessary for the CMOS circuit to hold the signal. In the embodiment of the invention, the power supply jitter prevention circuit with the memory function comprises a power supply module with delayed power supply capacity, when a power supply VDD is 0V or close to 0V, because a P-type MOS is in a cut-off working state, the voltage discharge time and the discharge curve of a V end are determined by the size of all loads connected with the V end, and the V end can still have the power supply capacity under the condition that the power supply VDD loses the power supply capacity through the circuit design working logic of the invention.

Specifically, when the external circuit is in a discharging state, the V _ det signal is "0" (the voltage is determined by the external voltage detection circuit), at this time, Reset in the logic latch circuit 4 is locked, the Reset signal product is prohibited, and CLK is also locked, so that the logic circuit in the logic latch circuit 4 operates, and the load current generated by all the modules at the V terminal is reduced, thereby prolonging the time for holding the voltage required by the signal.

Under the normal condition of the power supply VDD, the important signals of the chip are stored in the logic latch circuit 4 through Data _ in, and the working state is determined by reading the Data _ out signals at regular time so as to ensure the logic sequence of the circuit.

In an embodiment of the present invention, the unlock circuit 2 may include an anti-shake detection unit 202, a rising edge detection unit 203, a latch unit 204, a director 205, and an nor gate 206, which are used to prevent the logic latch circuit from being reset in a low voltage state or during a power-on period, and ensure that the logic latch module outputs a reset signal during normal operation. Preferably, the director 205 may be an inverter.

Specifically, when the power supply VDD fluctuates as in fig. 2, the Reset in the logic latch circuit 4 is directly locked when the V _ det signal is "0", and the Reset is output from the nor gate 206. When the V _ det signal is "1", the anti-shake detection circuit 202 sets an anti-shake time (e.g., 200ms, 300ms), during which Reset is still locked, the clock circuit CLK is also locked, and after the power supply VDD is stabilized, the anti-shake detection circuit 202 sets the anti-shake time, and the logic latch circuit 4 can normally operate, so as to achieve the purpose that the signal is not triggered by mistake.

Specifically, in the embodiment of the present invention, the unlock circuit 2 may include, but is not limited to, nand gate 201, anti-shake detection 202, rising edge detection 203, latch module (latch)4, and director 205 or nor 206 combinational logic, and the purpose thereof is to output Reset "0" signal in low voltage state or power-up period, so as to prevent the logic latch circuit 4 from resetting and ensure that the logic latch module information does not change.

Referring to fig. 2 again, the internal power module circuit in fig. 2 includes a P-type MOS transistor and a capacitor C; the drain electrode of the P-type MOS tube is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS tube are connected with one end of a capacitor C together in a short circuit mode, the other end of the capacitor C is grounded, and the grid electrode of the P-type MOS tube is grounded.

Specifically, the nand gate 201, the anti-shake detection 202, the rising edge detection 203, the latch module 204 and the

director

205 or 206 in the unlock circuit 2 constitute a Reset signal connected to the logic latch circuit 4; the output of the NOR gate 3 is connected to the logic latch circuit 4 and the input end of the clock CLK; the Data _ in and Data _ out of the logic latch circuit 4 are Data input/output terminals that need to be memorized.

In addition, the internal power module circuit includes a P-type MOS transistor and an internal capacitor connection method, including but not limited to a one-stage connection, and there may also be a multi-stage cascade connection, please refer to fig. 3, where fig. 3 is a schematic structural diagram of a capacitor adjustment circuit in an embodiment of the present invention. As shown in fig. 3, the internal power module circuit includes a P-type MOS transistor MP1, a P-type MOS transistor MP2, a P-type MOS transistor MP3, and a capacitor C; the drain electrode of the P-type MOS transistor MP1 is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS transistor MP1 are connected with one end of the capacitor C in a short circuit mode, the other end of the capacitor C is grounded, the drain electrode of the P-type MOS transistor MP2 is connected with the source electrode of the P-type MOS transistor MP3, and the drain electrode of the P-type MOS transistor MP3 is connected with the ground end; the source electrode of the P-type MOS tube MP2 is connected with the V end. In addition, in the embodiment of fig. 3, MP2 and MP3 may be replaced by NMOS or diodes, and the number of the voltage dividing MOS transistors may be 3 or more MOS transistors connected in series.

The logic latch module 4 preferably includes an RS flip-flop, a D flip-flop, a latch, and/or a RAM. The clock circuit includes a NAND gate or a NOR gate for preventing the clock CLK signal from changing during a low voltage state or a power-up period.

In conclusion, the power supply jitter prevention circuit with the memory function provided by the invention has the advantages that under the condition that the power supply VDD is temporarily powered off, the electric signal can have the memory function, and the data is ensured not to be lost; in addition, the circuit of the invention has simple structure, strong anti-interference capability, wide application and strong practicability, and is suitable for various non-input capacitance circuits.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims

1. A circuit for preventing power jitter with memory function, comprising: the circuit comprises a logic latch circuit, a clock circuit and an internal power supply module; the input end of the internal power supply module is connected with a power supply VDD, and the output end of the internal power supply module is connected with the power supply end of the logic latch circuit; the logic latch circuit is used for inputting and outputting data under the control of the clock circuit;

when the power supply voltage of a power supply VDD is lower than a preset threshold value after power failure, the internal power supply module outputs a power supply required by a power supply end V end of the logic latch circuit, and data entering the logic latch circuit in a period after the power supply VDD is powered down is latched.

2. The power supply jitter prevention circuit with memory function according to claim 1; the internal power supply module circuit is characterized by comprising a P-type MOS tube and a capacitor C; the drain electrode of the P-type MOS tube is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS tube are connected with one end of a capacitor C together in a short circuit mode, the other end of the capacitor C is grounded, and the grid electrode of the P-type MOS tube is grounded.

3. The power supply jitter prevention circuit with memory function according to claim 1; the internal power supply module circuit is characterized by comprising a P-type MOS tube and a capacitor C; the drain electrode of the P-type MOS tube is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS tube are connected with one end of a capacitor C together in a short circuit mode, the other end of the capacitor C is grounded, and the grid electrode of the P-type MOS tube is connected with a divided voltage.

4. The power supply jitter prevention circuit with memory function according to claim 1; the internal power supply module circuit is characterized by comprising a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP3 and a capacitor C; the drain electrode of the P-type MOS transistor MP1 is externally connected with a power supply VDD, the source electrode and the grid electrode of the P-type MOS transistor MP1 are connected with one end of the capacitor C in a short circuit mode, the other end of the capacitor C is grounded, the drain electrode of the P-type MOS transistor MP2 is connected with the source electrode of the P-type MOS transistor MP3, and the drain electrode of the P-type MOS transistor MP3 is connected with the ground end; the source electrode of the P-type MOS tube MP2 is connected with the V end.

5. The power supply jitter prevention circuit with memory function according to claim 1; the logic latch module is characterized by comprising an RS trigger, a D trigger, a latch and/or a RAM.

6. The power supply jitter prevention circuit with memory function according to claim 1; the clock circuit comprises a NAND gate or a NOR gate and is used for preventing the clock CLK signal from changing in a low-voltage state or a power-on period.

7. The power supply jitter prevention circuit with memory function according to claim 1; the anti-shake circuit is characterized by further comprising an unlocking circuit, wherein the unlocking circuit comprises an anti-shake detection unit, a rising edge detection unit, a latch unit, a director and an OR-NOT gate, and is used for preventing the logic latch circuit from being reset in a low-voltage state or a period of power-on and ensuring that the logic latch module outputs a reset signal when the logic latch module normally works.