CN112650697A - Arbitration circuit of multiple main devices based on DDR3 storage controller interface - Google Patents
Arbitration circuit of multiple main devices based on DDR3 storage controller interface Download PDFInfo
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- CN112650697A CN112650697A CN202011543007.XA CN202011543007A CN112650697A CN 112650697 A CN112650697 A CN 112650697A CN 202011543007 A CN202011543007 A CN 202011543007A CN 112650697 A CN112650697 A CN 112650697A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to an arbitration circuit of a plurality of main devices based on a DDR3 storage controller interface. The system comprises a monitoring circuit with n ports, a page information cache circuit, a page hit arbitration circuit, an emergency polling arbitration circuit, a non-emergency polling arbitration circuit and an arbitration selection and issuing circuit; the page information cache circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit; the page hit arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit; the emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit; the non-emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit; n is the same as the number of masters. The invention provides an arbitration circuit of a plurality of main devices based on a DDR3 storage controller interface, which can improve the priority strategy and the efficiency of a controller and achieve the effect of giving consideration to the command requirement and the storage bandwidth.
Description
Technical Field
The invention belongs to the field of integrated circuit design, relates to an arbitration circuit, and particularly relates to an arbitration circuit of a plurality of main devices based on a DDR3 storage controller interface.
Background
The DDR3 memory controller interface is used to provide a channel for various masters to access external DDR3 memory. Each master device desires a small response delay and a large data bandwidth. A simple arbitration circuit, such as simple polling, when multiple masters access simultaneously, would have the following drawbacks: frequent DDR3 SDRAM page opening and closing processes, resulting in idle bandwidth loss of the data bus; emergency commands cannot respond quickly; the dense access device and the loose access device occupy the same data bandwidth. How to solve the above problems is a significant difficulty in designing the interface arbitration circuit of the DDR3 memory controller.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides an arbitration circuit of a plurality of main devices based on a DDR3 storage controller interface.
The technical solution of the invention is as follows:
an arbitration circuit of a plurality of main devices based on a DDR3 memory controller interface is characterized in that: the system comprises a monitoring circuit with n ports, a page information cache circuit, a page hit arbitration circuit, an emergency polling arbitration circuit, a non-emergency polling arbitration circuit and an arbitration selection and issuing circuit;
the page information cache circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the page hit arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the non-emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the number of n is the same as the number of master devices.
Preferably, the method comprises the following steps: the master device sends an address, a command mode and a priority (0-n) to the port monitoring circuit; the port monitoring circuit caches the main equipment request and sets the busy state to 1;
the port monitoring circuit decodes the address information of the main device into page information, and compares the page information with page cache information to generate a page hit condition; extracting bank and column information in the address information according to the hit condition; if the page is hit, sending a request to a page hit polling arbitration circuit;
the port monitoring circuit analyzes the command mode, and if the command mode is an emergency command, the port monitoring circuit sends a request to the emergency polling arbitration circuit; if the command is a non-emergency command, the request and the corresponding priority are sent to a non-emergency arbitration circuit; if the current clock cycle arbitration selection and command issuing circuit does not feed back command issuing information to the port monitoring circuit, the busy state of the next clock cycle is still set to 1, meanwhile, the priority is reduced by 1, and if the priority is reduced to 0, the request is not sent to the non-emergency arbitration circuit and the request is sent to the emergency command arbitration circuit.
Preferably, the method comprises the following steps: the page hit arbitration circuit receives the page hit arbitration request provided by the port monitoring circuit, carries out polling arbitration, and sends an arbitration result to the arbitration selection and sending circuit.
Preferably, the method comprises the following steps: the emergency polling arbitration circuit receives the emergency arbitration request provided by the port monitoring circuit, carries out polling arbitration, and issues an arbitration result to the arbitration selection and issuing circuit.
Preferably, the method comprises the following steps: the non-urgent polling arbitration circuit receives the non-urgent arbitration request and the priority information provided by the port monitoring circuit to carry out polling arbitration on the request with the minimum priority, and issues the arbitration result to the arbitration selection and issuing circuit.
Preferably, the method comprises the following steps: the arbitration selection and sending-down circuit receives the requests of the page hit arbitration circuit, the emergency polling arbitration circuit and the non-emergency polling arbitration circuit;
when the request of the emergency polling arbitration circuit is not empty, the command of the request is issued, and meanwhile, the command issuing information is fed back to the port monitoring circuit, and meanwhile, the page information of the issued command is fed back to the page information cache circuit;
when the request of the emergency polling arbitration circuit is empty and the request from the page hitting polling arbitration circuit is not empty, the command of the request is issued, and meanwhile, the command issuing information is fed back to the port monitoring circuit, and meanwhile, the page information of the issued command is fed back to the page information cache circuit;
when the requests of the page hit polling arbitration circuit and the emergency polling arbitration circuit are both null and the request from the non-emergency polling arbitration circuit is not null, the command of the request is issued, and simultaneously the issuing information of the command is fed back to the port monitoring circuit, and the page information of the command is fed back to the page information cache circuit;
the page hit does not participate in arbitration, and if the address sent in the next period of the current response master device meets the page hit, the DDR3 storage controller is locked to continuously respond;
the emergency command adopts the flat polling arbitration;
the non-emergency command adopts weight polling arbitration, and particularly, the higher the priority is, the response is earlier; when there is an emergency command, the emergency command is issued, otherwise, the arbitrated non-emergency command is issued.
Preferably, the method comprises the following steps: and each clock cycle of the page information cache circuit receives the page information of the command issued by the arbitration selection and command issuing circuit and feeds back the information to the port monitoring circuit.
The invention has the following specific advantages and effects:
in the prior art, the DDR3 memory controller interface is used to provide access to external DDR3 memory by various masters. Each master device desires a small response delay and a large data bandwidth. A simple arbitration circuit, such as simple polling, when multiple masters access simultaneously, would have the following drawbacks: frequent DDR3 SDRAM page opening and closing processes, resulting in idle bandwidth loss of the data bus; emergency commands cannot respond quickly; the dense access device and the loose access device occupy the same data bandwidth.
The arbitration circuit of the plurality of main devices based on the DDR3 memory controller interface, which is designed based on the important points, can increase the page flow of DDR3 SDRAM as much as possible, and compared with a simple polling arbitration circuit, the data bandwidth is greatly increased under the condition of complex multi-port access. Meanwhile, the respective requirements of the main equipment are considered, so that the loose access equipment and the emergency command can obtain shorter response time, and the dense access equipment can obtain larger data bandwidth. The effect of taking command requirements and DDR3 data bandwidth into account is generally achieved.
Drawings
FIG. 1 is a schematic diagram of an arbitration circuit according to the present invention;
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than the whole embodiments, and that all other embodiments, which can be derived by a person skilled in the art without inventive step based on the embodiments of the present invention, belong to the scope of protection of the present invention.
Referring to fig. 1, an arbitration circuit of multiple masters based on DDR3 memory controller interface includes a monitoring circuit with n ports, a page information cache circuit, a page hit arbitration circuit, an urgent polling arbitration circuit, a non-urgent polling arbitration circuit, and an arbitration selection and issuing circuit;
the page information cache circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the page hit arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the non-emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the number of n is the same as the number of master devices.
The master device sends an address, a command mode and a priority (0-n) to the port monitoring circuit; the port monitoring circuit caches the main equipment request and sets the busy state to 1;
the port monitoring circuit decodes the address information of the main device into page information, and compares the page information with page cache information to generate a page hit condition; extracting bank and column information in the address information according to the hit condition; if the page is hit, sending a request to a page hit polling arbitration circuit;
the port monitoring circuit analyzes the command mode, and if the command mode is an emergency command, the port monitoring circuit sends a request to the emergency polling arbitration circuit; if the command is a non-emergency command, the request and the corresponding priority are sent to a non-emergency arbitration circuit; if the current clock cycle arbitration selection and command issuing circuit does not feed back command issuing information to the port monitoring circuit, the busy state of the next clock cycle is still set to 1, meanwhile, the priority is reduced by 1, and if the priority is reduced to 0, the request is not sent to the non-emergency arbitration circuit and the request is sent to the emergency command arbitration circuit.
The page hit arbitration circuit receives the page hit arbitration request provided by the port monitoring circuit, carries out polling arbitration, and sends an arbitration result to the arbitration selection and sending circuit.
The emergency polling arbitration circuit receives the emergency arbitration request provided by the port monitoring circuit, carries out polling arbitration, and issues an arbitration result to the arbitration selection and issuing circuit.
The non-urgent polling arbitration circuit receives the non-urgent arbitration request and the priority information provided by the port monitoring circuit to carry out polling arbitration on the request with the minimum priority, and issues the arbitration result to the arbitration selection and issuing circuit.
The arbitration selection and sending-down circuit receives the requests of the page hit arbitration circuit, the emergency polling arbitration circuit and the non-emergency polling arbitration circuit;
when the request of the emergency polling arbitration circuit is not empty, the command of the request is issued, and meanwhile, the command issuing information is fed back to the port monitoring circuit, and meanwhile, the page information of the issued command is fed back to the page information cache circuit;
when the request of the emergency polling arbitration circuit is empty and the request from the page hitting polling arbitration circuit is not empty, the command of the request is issued, and meanwhile, the command issuing information is fed back to the port monitoring circuit, and meanwhile, the page information of the issued command is fed back to the page information cache circuit;
when the requests of the page hit polling arbitration circuit and the emergency polling arbitration circuit are both null and the request from the non-emergency polling arbitration circuit is not null, the command of the request is issued, and simultaneously the issuing information of the command is fed back to the port monitoring circuit, and the page information of the command is fed back to the page information cache circuit;
the page hit does not participate in arbitration, and if the address sent in the next period of the current response master device meets the page hit, the DDR3 storage controller is locked to continuously respond;
the emergency command adopts the flat polling arbitration;
the non-emergency command adopts weight polling arbitration, and particularly, the higher the priority is, the response is earlier; when there is an emergency command, the emergency command is issued, otherwise, the arbitrated non-emergency command is issued.
And each clock cycle of the page information cache circuit receives the page information of the command issued by the arbitration selection and command issuing circuit and feeds back the information to the port monitoring circuit.
Example (b):
the invention is described in further detail below with reference to the accompanying drawings, which refer to fig. 1.
An arbitration circuit for multiple masters based on a DDR3 memory controller interface. The arbitration circuit adopts the following arbitration strategy, and comprises the following steps:
the first mechanism is to set a page hit strategy: the page hit policy, i.e., the address of the originating command is consistent with the bank, row address of the page being activated by the DDR3 memory controller.
Mechanism two, the main device orders to set an emergency mode and a non-emergency mode: the command types initiated by the main device are divided into an emergency command and a non-emergency command. The emergency command has only one priority. Non-urgent commands have n (consistent with the number of masters) priorities.
Mechanism three, priority is divided into port priority and command priority: the master device can set the priority, and if no setting adopts the default priority 1; the main equipment commands to carry priority, and if the main equipment commands to carry priority response; if the priority carried by no command is default, the priority set by the equipment is used.
Mechanism four, non-urgent commands can be converted into urgent commands: and the priority of the non-emergency command which is not responded in each period is increased by one step, and if the priority reaches the highest level, the command enters an emergency mode.
The mechanism is five independent polling arbitration: and the page hit does not participate in arbitration, and if the address sent by the current response master device in the next period meets the page hit, the DDR3 memory controller is locked to continuously respond. The emergency command employs a fair polling arbitration. Non-urgent commands employ weighted round robin arbitration, i.e., respond first with higher priority. When there is an emergency command, an emergency command is issued, otherwise an arbitrated non-emergency command is issued.
Mechanism six, the emergency command can release the page hit lock: the DDR3 memory controller lock formed by a page hit may be released in the event the master sends an emergency command. If there is an urgent command for the current cycle, the DDR3 memory controller will not enter the page hit locked state.
The arbitration circuit arbitration policy for the plurality of masters based on the DDR3 memory controller interface ends.
Claims (7)
1. An arbitration circuit for a plurality of masters based on a DDR3 memory controller interface, comprising: the system comprises a monitoring circuit with n ports, a page information cache circuit, a page hit arbitration circuit, an emergency polling arbitration circuit, a non-emergency polling arbitration circuit and an arbitration selection and issuing circuit;
the page information cache circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the page hit arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the non-emergency polling arbitration circuit is respectively connected with the monitoring circuit and the arbitration selection and issuing circuit;
the number of n is the same as the number of the main devices.
2. The arbitration circuit of the plurality of masters based on the DDR3 memory controller interface of claim 1, wherein: the master device sends an address, a command mode and a priority (0-n) to the port monitoring circuit; the port monitoring circuit caches the main equipment request and sets the busy state to 1;
the port monitoring circuit is decoded into page information according to the address information of the main equipment and is compared with the page cache information to generate a page hit condition; the hit condition is that the bank and column information in the address information is extracted; if the page is hit, sending a request to a page hit polling arbitration circuit;
the port monitoring circuit analyzes the command mode, and if the command mode is an emergency command, the port monitoring circuit sends a request to the emergency polling arbitration circuit; if the command is a non-emergency command, the request and the corresponding priority are sent to a non-emergency arbitration circuit; if the current clock cycle arbitration selection and command issuing circuit does not feed back command issuing information to the port monitoring circuit, the busy state of the next clock cycle is still set to 1, meanwhile, the priority is reduced by 1, and if the priority is reduced to 0, the request is not sent to the non-emergency arbitration circuit and the request is sent to the emergency command arbitration circuit.
3. The arbitration circuit of the plurality of masters based on the DDR3 memory controller interface of claim 2, wherein: the page hit arbitration circuit receives the page hit arbitration request provided by the port monitoring circuit, carries out polling arbitration, and sends an arbitration result to the arbitration selection and sending circuit.
4. The arbitration circuit of the plurality of masters based on the DDR3 memory controller interface of claim 3, wherein: the emergency polling arbitration circuit receives the emergency arbitration request provided by the port monitoring circuit, carries out polling arbitration, and sends an arbitration result to the arbitration selection and sending circuit.
5. The arbitration circuit of the plurality of masters based on the DDR3 memory controller interface of claim 4, wherein: the non-urgent polling arbitration circuit receives the non-urgent arbitration request and the priority information provided by the port monitoring circuit to carry out polling arbitration on the request with the minimum priority, and sends the arbitration result to the arbitration selection and sending circuit.
6. The arbitration circuit of the plurality of masters based on the DDR3 memory controller interface of claim 5, wherein: the arbitration selection and sending-down circuit receives the requests of the page hit arbitration circuit, the emergency polling arbitration circuit and the non-emergency polling arbitration circuit;
when the request of the emergency polling arbitration circuit is not empty, the command of the request is issued, and meanwhile, the command issuing information is fed back to the port monitoring circuit, and meanwhile, the page information of the issued command is fed back to the page information cache circuit;
when the request of the emergency polling arbitration circuit is empty and the request from the page hitting polling arbitration circuit is not empty, the command of the request is issued, and meanwhile, the command issuing information is fed back to the port monitoring circuit, and meanwhile, the page information of the issued command is fed back to the page information cache circuit;
when the requests of the page hit polling arbitration circuit and the emergency polling arbitration circuit are both null and the request from the non-emergency polling arbitration circuit is not null, the command of the request is issued, and simultaneously the issuing information of the command is fed back to the port monitoring circuit, and the page information of the command is fed back to the page information cache circuit;
the page hit does not participate in arbitration, and if the address sent in the next period of the current response master device meets the page hit, the DDR3 storage controller is locked to continuously respond;
the emergency command adopts the flat polling arbitration;
the non-emergency command adopts weight polling arbitration, and specifically refers to that the higher the priority is, the response is earlier; when there is an emergency command, the emergency command is issued, otherwise, the arbitrated non-emergency command is issued.
7. The arbitration circuit of the plurality of masters based on the DDR3 memory controller interface of claim 5, wherein: and each clock cycle of the page information cache circuit receives the page information of the command issued by the arbitration selection and command issuing circuit and feeds back the information to the port monitoring circuit.
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Cited By (1)
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| CN114741341A (en) * | 2022-03-01 | 2022-07-12 | 西安电子科技大学 | Method, system and storage medium for realizing Crossbar structure arbitration |
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