CN108710590B - 8051 system and bus automatic arbitration management method thereof - Google Patents
8051 system and bus automatic arbitration management method thereof Download PDFInfo
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- CN108710590B CN108710590B CN201810554745.0A CN201810554745A CN108710590B CN 108710590 B CN108710590 B CN 108710590B CN 201810554745 A CN201810554745 A CN 201810554745A CN 108710590 B CN108710590 B CN 108710590B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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Abstract
An 8051 system and a bus automatic arbitration management method thereof, comprising: setting a bus arbiter which is connected with an 8051CPU connected with a bus through a pair of bus request and response signals, and is connected with a plurality of modules connected with the bus through a pair of bus request and response signals respectively; when any one of the modules initiates a bus request, the bus arbiter initiates the bus request to the 8051CPU, and when the 8051CPU confirms that the bus is released, the bus arbiter grants the corresponding module according to a set policy, and the granted module accesses the bus in burst mode. The invention has high management efficiency and can well meet the application requirement of higher real-time requirement.
Description
Technical Field
The invention relates to a single-chip microcomputer system, in particular to an 8051 series single-chip microcomputer system.
Background
In the existing 8051 system (i.e. the short for 8051 series single chip microcomputer system), the system manages the access to the RAM through the firmware due to the exclusive property of the bus and the capability of the bus for automatic arbitration. When multiple modules need to access RAM (Random Access Memory ), firmware management is extremely complex. Each module independently applies arbitration to the CPU, and when the task of one module is executed, the tasks of other modules are suspended and cannot be started. The firmware has poor flexibility, so that a large amount of time is occupied by a module bus, and the system efficiency is low. The application with high real-time requirement happens, and the firmware cannot be managed finally, so that the system cannot normally operate.
Referring to fig. 1, the existing 8051 system includes: 8051CPU101, module 1 102, module 2 103, module N104, bus 105, RAM 106, module selector 107, and request logic 108. When the 8051CPU101 needs the module n (one of the multiple modules) to work, the module n can initiate the request reqn, and after the 8051CPU101 gives a corresponding response ACK for the request, the module n can obtain the management authority of the bus 105, and access the RAM 106. In particular, the module n obtains the management authority of the bus 105 through the module selector 107. When ACK is valid, the 8051CPU101 hangs itself, loses the management authority to the bus 105, and cannot access the RAM 106. The management method for bus automatic arbitration has some defects: 1. all modules access the bus 105, the 8051cpu101 is required to enable the corresponding modules, initiate the corresponding requests, and have complex firmware management. 2. Only one module can occupy the bus 105 at a time, and the 8051cpu101 cannot operate when the module occupies the bus 105. 3. Each time a module occupies the bus 105, the task of the module must be completed, otherwise, the management complexity increases greatly. 4. As the number of modules increases, it may result in some modules not having timely access to RAM 106 via bus 105 to obtain real-time responses, resulting in system anomalies. Therefore, the existing management method for bus automatic arbitration of the 8051 system has low management efficiency, can not well meet the application requirement of higher real-time requirement, and needs to be improved.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a bus automatic arbitration management method of an 8051 system, which has high management efficiency and can well meet the application requirement of higher real-time requirement.
The technical scheme adopted by the invention for solving the technical problems comprises the following steps: provided is a management method for bus automatic arbitration of an 8051 system, comprising the following steps: setting a bus arbiter which is connected with an 8051CPU connected with a bus through a pair of bus request and response signals, and is connected with a plurality of modules connected with the bus through a pair of bus request and response signals respectively; when any one of the modules initiates a bus request, the bus arbiter initiates the bus request to the 8051CPU, and when the 8051CPU confirms that the bus is released, the bus arbiter grants the corresponding module according to a set policy, and the granted module accesses the bus in burst mode.
Wherein the set policy is priority or round robin.
Wherein the bus arbiter is coupled to the bus by a bus select signal.
Wherein the bus is connected with the RAM, and the plurality of modules are connected with the RAM through the bus.
Wherein each module can only occupy at most 4/8/16 accesses to the bus at a time.
The technical scheme adopted by the invention for solving the technical problems also comprises the following steps: there is provided an 8051 system comprising: a bus arbiter connected to the 8051CPU via a pair of bus request and response signals, and connected to the plurality of modules connected to the bus via a pair of bus request and response signals, respectively; when any one of the modules initiates a bus request, the bus arbiter initiates the bus request to the 8051CPU, and when the 8051CPU confirms that the bus is released, the bus arbiter grants the corresponding module according to a set policy, and the granted module accesses the bus in burst mode.
Compared with the prior art, the 8051 system manages the bus request and authority of each module through the bus arbiter, can allow a plurality of modules to initiate the bus request at the same time, applies for the bus to the 8051CPU, further obtains the authority according to the set strategy through the bus arbiter, the module applying for the bus can access the bus, and meanwhile, other modules not applying for the bus can only carry out new authority of the bus according to the set strategy after the current access of the current module is finished, so that the management efficiency is high; in addition, by enabling the modules to access the bus in a burst mode, each task of each module can be divided into a plurality of burst packet tasks to be completed, and the requirements of applications with high real-time requirements can be well met.
Drawings
Fig. 1 is a schematic diagram of a conventional management method for automatic bus arbitration in an 8051 system.
Fig. 2 is a schematic diagram of a method for managing bus auto-arbitration in an 8051 system according to the present invention.
FIG. 3 is an exemplary timing diagram of the bus requests and responses of three modules in the 8051 system of the invention.
FIG. 4 is an exemplary timing diagram of bus requests and responses for two modules in the 8051 system of the invention.
Wherein, the main reference numerals are as follows: 101. 8051cpu,102, modules 1, 103, modules 2, 104, modules N,105, bus, 106, RAM,107, module selector, 108, request logic; 201. 8051cpu,202, modules 1, 203, modules 2, 204, modules N,205, bus, 206, RAM,207, bus arbiter.
Detailed Description
Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
Referring to fig. 2, fig. 2 is a schematic diagram of a management method of bus automatic arbitration of the 8051 system of the present invention. The invention provides a bus automatic arbitration management method of an 8051 system. The 8051 system of the invention comprises: 8051CPU 201, module 1 202, module 2 203, module N204, bus 205, RAM206, and bus arbiter 207. The bus arbiter 207 and the 8051CPU 201 connected to the bus 205 are connected by a pair of bus request REQ and response signals ACK. The bus arbiter 207 is coupled to a plurality of bus-coupled modules 202, 203, 204 via a pair of bus requests req1, req2, reqn and response signals ack1, ack2, ackn, respectively. The bus arbiter 207 is connected to the bus 205 by a bus select signal BSSL. The bus 205 is connected to the RAM206, and the plurality of modules 202, 203, 204 are connected to the RAM206 via the bus 205.
The present invention manages a pair of bus request req1, req2, reqn and response (also called request acknowledge) ack1, ack2, ackn signals for each module (module 1, module 2..module N) by means of a bus arbiter 207; at the same time, bus arbiter 207 provides a policy arbitration mechanism, such as: priority, round-robin, etc., arbitrating and selecting bus requests req1, req2, reqn, and granting responses ack1, ack2, ackn to corresponding modules. The module to which the response is granted may obtain management rights to bus 205.
After the current module response and its corresponding task are executed, the bus arbiter 207 will continue to determine whether there are any other modules for which tasks need to be executed (i.e. req corresponding to a certain module is valid), and if so, continue to arbitrate; if not, the management authority of the bus 205 is given to the 8051CPU 201.
It should be noted that, in this method for managing bus automatic arbitration, the firmware program of the 8051CPU 201 does not need to enable only one module 202, 203, 204 at a time, but can simultaneously enable all modules 202, 203, 204, and the rights of each module 202, 203, 204 to access the bus 205 and the RAM206 are obtained by the bus arbiter 207, so that the complexity of firmware management is reduced; each module 202, 203, 204 accesses the RAM206 in burst (burst refers to a manner in which adjacent memory cells in the same row continuously transmit data, and the number of periods of continuous transmission is referred to as burst length or granularity), and each module 202, 203, 204 can only occupy 4/8/16 (i.e. the number of read/write cycles) of access to the bus 205 at most. By accessing in a burst mode, abnormal functions caused by long-term failure of real-time response of tasks of certain modules can be effectively avoided, and real-time performance of each module 202, 203 and 204 can be ensured.
Referring to fig. 3, fig. 3 is an exemplary timing diagram of the bus requests and responses of three modules in the 8051 system of the invention. Taking three modules as an example, bus requests correspond to req1, req2, reqn, respectively. The request acknowledge signals are ack1, ack2, ackn, respectively. When any one of the modules 202, 203, 204 initiates a request REQ, the bus arbiter 207 will initiate a bus request REQ to the 8051CPU 201, and when the 8051CPU 201 confirms that the release bus ACK is valid (valid high), the bus arbiter 207 first grants the bus 205 to the corresponding module 1 202; next, the bus arbiter 207 initiates the request REQ again, and when the 8051cpu 201 confirms that the release bus ACK is valid, the bus arbiter 207 grants the bus to the corresponding module 2 203; finally, the bus arbiter 207 initiates the request REQ again, and when the 8051CPU 201 confirms that the release bus ACK is valid, the bus arbiter 207 grants the bus to the module N204. Specifically, periods 301, 302, 303 correspond to modules 202, 203, 204, respectively, obtaining bus grants. It will be appreciated that in this embodiment, the policy set is round robin.
Referring to fig. 4, fig. 4 is an exemplary timing diagram of bus requests and responses for two modules in the 8051 system of the invention. Taking two modules as an example, the transmission task of 1024B information of the module 1 202 needs multiple burst access to complete. When the module 2 203 also has real-time tasks to be responded to, the module 2 203 can also obtain the authority of the bus 205 in time. Specifically, time periods 401, 403, 404, 405 correspond to multiple burst mode accesses of module 1 202, and time period 402 corresponds to one burst mode access of module 1 202.
It will be appreciated that if module 1,2..n cannot access RAM206 in burst mode, module 2 203 must wait for the transmission of 1024B information from module 1 202 to complete in order to obtain a response, then once the real-time tasks of module 2 203 cannot be satisfied, and the system may be abnormal.
Compared with the prior art, the 8051 system of the invention has the advantages that at least comprises: the bus request and authority of each module 202, 203 and 204 are managed through the bus arbiter 207, so that the plurality of modules 202, 203 and 204 can be allowed to initiate bus requests at the same time, the 8051CPU 201 is applied for buses, and then the bus arbiter 207 obtains authority according to a set strategy, the module n applied to the bus 205 can access the RAM206, and meanwhile, other modules which are not applied to the bus 205 can only carry out new authority of the bus 205 according to the set strategy after the current access of the module n is finished, so that the management efficiency is high; in addition, by enabling the modules 202, 203 and 204 to access the bus 205 in a burst mode, each task of each module 202, 203 and 204 can be divided into a plurality of burst packet tasks to be completed, and the requirements of applications with high real-time requirements can be well met.
It should be understood that the foregoing embodiments are merely illustrative of the technical solutions of the present invention, and not limiting thereof, and that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art; such modifications and substitutions are intended to fall within the scope of the appended claims.
Claims (6)
1. A method for managing bus auto-arbitration in an 8051 system, comprising: setting 8051CPU, several modules, bus, RAM and bus arbiter, where the bus arbiter is connected with the 8051CPU connected with the bus by a pair of bus request and response signals, and the bus arbiter is connected with several modules connected with the bus by a pair of bus request and response signals; the plurality of modules are connected with the RAM through the bus, the firmware program of the 8051CPU can enable all the modules at the same time, the authority of each module to access the bus and the RAM is obtained through the bus arbiter, when any one of the plurality of modules initiates a bus request, the bus arbiter initiates the bus request to the 8051CPU, when the 8051CPU confirms that the bus is released, the bus arbiter grants the corresponding module according to a set strategy, the granted module accesses the RAM in a burst mode, and each module only occupies 4/8/16 access to the bus at most.
2. The method of claim 1, wherein the policy set is priority or round robin.
3. The method of claim 1, wherein the bus arbiter is coupled to the bus via a bus select signal.
4. An 8051 system, comprising: an 8051CPU, a plurality of modules, a bus, a RAM and a bus arbiter, wherein the bus arbiter is connected with the 8051CPU connected with the bus through a pair of bus request and response signals, and the bus arbiter is connected with a plurality of modules connected with the bus through a pair of bus request and response signals respectively; the multiple modules are connected with the RAM through the bus, the firmware program of the 8051CPU can enable all the modules at the same time, the authority of each module to access the bus and the RAM is obtained through the bus arbiter, when any one of the multiple modules initiates a bus request, the bus arbiter initiates the bus request to the 8051CPU, when the 8051CPU confirms that the bus is released, the bus arbiter grants the corresponding module according to a set strategy, the granted module accesses the RAM in a burst mode, and each module only occupies 4/8/16 of accesses to the bus at most each time.
5. The 8051 system of claim 4, wherein the set policy is priority or round robin.
6. The 8051 system of claim 4, wherein the bus arbiter is coupled to the bus by a bus select signal.
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| CN101276384A (en) * | 2007-03-30 | 2008-10-01 | 成都方程式电子有限公司 | Security control chip and implementing method thereof |
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| CN101276384A (en) * | 2007-03-30 | 2008-10-01 | 成都方程式电子有限公司 | Security control chip and implementing method thereof |
| CN106155971A (en) * | 2016-07-04 | 2016-11-23 | 锐捷网络股份有限公司 | The referee method of I2C bus and device |
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