CN112647048B - Inverted electrode and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 101
- 238000001704 evaporation Methods 0.000 claims abstract description 38
- 239000002131 composite material Substances 0.000 claims abstract description 27
- 229910016570 AlCu Inorganic materials 0.000 claims abstract description 21
- 239000000956 alloy Substances 0.000 claims abstract description 21
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000007747 plating Methods 0.000 claims description 198
- 239000011248 coating agent Substances 0.000 claims description 46
- 238000000576 coating method Methods 0.000 claims description 46
- 238000002474 experimental method Methods 0.000 abstract description 10
- 238000012360 testing method Methods 0.000 abstract description 3
- 238000002360 preparation method Methods 0.000 abstract 1
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000032683 aging Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000009528 severe injury Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
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Abstract
A flip-chip electrode and its preparation method, wherein the method includes the following step, make the layer Cr of layer 1; manufacturing a 2 nd AlCu alloy layer; alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers; manufacturing a 9 th Au layer; evaporating a 10 th Ti layer and an 11 th Pt layer; manufacturing a 12 th Au layer; the 13 th Ti layer was produced. By the technical scheme, the performance of the flip electrode chip in the thimble test experiment can be improved, and the use cost can be reduced.
Description
Technical Field
The invention relates to a flip electrode design, in particular to a manufacturing method for improving the performance of a flip electrode.
Background
Gallium nitride based Light Emitting Diodes (LEDs) have the advantages of low loss of function, long lifetime, and good reliability, and are widely used in the fields of signal lamps, backlight displays, automotive lighting, and indoor lighting. With the popularization and application of high-power and high-luminous-efficiency LEDs, flip-Chip products (Filp chips) have wider application market and higher application value. In the current chip-scale packaging processing technology, a method of puncturing a blue film by a thimble is commonly used in the separation of a processing chip and the blue film by traditional chip-mounting packaging equipment such as an LED die bonder and a chip mounter; the flip chip product designed by the product needs to be subjected to the thimble performance verification, and flip chips introduced in the prior art such as CN 201320549532.1 and CN 201320550892.3 have the problem of high electrode consumption.
Disclosure of Invention
Therefore, a method for improving the chip anti-thimble test performance of the flip-chip electrode is needed.
A method for manufacturing a flip-chip electrode comprises the following steps,
manufacturing a 1 st Cr layer;
manufacturing a 2 nd AlCu alloy layer;
alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers;
manufacturing a 9 th Au layer;
evaporating a 10 th Ti layer and an 11 th Pt layer;
manufacturing a 12 th Au layer;
the 13 th Ti layer was produced.
In particular, the method comprises the steps of,
manufacturing a first layer Cr layer, and coating the surface of the chip with a plating rate of 0.2A/S;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5 Ang/S;
alternately evaporating 3 layers of the Ti layer and the Pt layer, plating the Ti layer at the plating rate of 1A/S, and plating the Pt layer at the plating rate of 1A/S to form a TiPt composite layer of the 3-8 th layer;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
a 10Ti layer and a 11 Pt layer are evaporated, the Ti layer is plated at a plating rate of 1A/S, and the Pt layer is plated at a plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th Ti layer, and plating a Ti layer at the plating rate of 1A/S.
In particular, it includes the steps of,
manufacturing a first layer Cr layer, and coating the surface of the chip with a plating rate of 0.2A/S;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5 Ang/S;
alternately evaporating 3 layers of a Ti layer and a Pt layer, plating the Ti layer at the plating rate of 2A/S, and plating the Pt layer at the plating rate of 1A/S to form a TiPt composite layer of the 3-8 th layer;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
a 10Ti layer and a 11 Pt layer are evaporated, the Ti layer is plated at a plating rate of 2A/S, and the Pt layer is plated at a plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th Ti layer, and plating a Ti layer at the plating rate of 2A/S.
In particular, the method comprises the steps of,
manufacturing a first layer Cr layer, wherein the thickness of a plated film is 30A;
manufacturing a 2 nd layer AlCu alloy layer, wherein the coating thickness is 1500 Ang;
alternately evaporating 3 Ti layers and 3 Pt layers, wherein the thickness of each Ti layer is 600A, and the thickness of each Pt layer is 500A, so as to form a TiPt composite layer of the 3-8 th layer;
manufacturing an Au layer on a 9 th layer, wherein the thickness of a plated film is 11000A;
evaporating a film with a thickness of 1500A on a 10Ti layer, and evaporating an 11 Pt layer with a film thickness of 700A;
manufacturing a 12 th Au layer, and plating a film with the thickness of 1000 ANG;
and manufacturing a 13 th Ti layer, and plating the film with the thickness of 500A.
Specifically, the method comprises the steps of manufacturing a 1 st Cr layer, and plating a film on the surface of the chip at a plating rate of 0.2A/S, wherein the thickness of the plated film is 30A;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1500A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 600A, each layer of Ti is subjected to film plating at 300A at a plating rate of 1A/S, and then subjected to film plating at 300A at a plating rate of 2A/S, each layer of Pt has a thickness of 500A, and a TiPt composite layer of a 3-8 layer is formed; each layer of Ti is 600A thick, each layer of Pt is 500A thick, and a TiPt composite layer of the 3-8 layer is formed;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 11000A;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, wherein the coating thickness is 1500A, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S, wherein the coating thickness is 700A;
manufacturing a 12 th Au layer, and plating a film with the thickness of 1000A at the plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the plating thickness is 500A.
By the technical scheme, the performance of the flip electrode chip in the thimble test experiment can be improved, and the use cost can be reduced.
Drawings
FIG. 1 is a schematic diagram of a flip chip electrode according to an embodiment;
FIG. 2 is a schematic diagram illustrating a batch result of a thimble experiment according to an embodiment;
FIG. 3 is a diagram illustrating the results of a small batch repeat experiment according to an embodiment.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
A method for manufacturing a flip-chip electrode comprises the following steps,
manufacturing a 1 st Cr layer; the Cr layer is used for realizing ohmic contact and improving the adhesion with a substrate,
manufacturing a 2 nd AlCu alloy layer; the AlCu alloy layer is used for increasing the reflectivity and reliability of the chip.
Alternately evaporating 3 Ti layers and 3 Pt layers to form a TiPt composite layer of the 3 rd to 8 th layers; wherein the Ti layer can increase the adhesion between metal layers, and the Pt layer is used for improving the aging capability.
Manufacturing a 9 th Au layer; the Au layer can enhance the electric conduction capability,
evaporating a 10 th Ti layer and an 11 th Pt layer; the Ti layer can increase the adhesion between metal layers, and the Pt layer is used to improve the aging capability.
Manufacturing a 12 th Au layer; the Au layer can enhance the electric conduction capability,
manufacturing a 13 th Ti layer; the Ti layer can increase adhesion to the chip DBR layer.
As can be seen from the figure 1, the layers are arranged in a mode of 1-13 layers from bottom to top, and the Ti layer cladding is realized on the most surface through the arrangement design, so that the top layer of the electrode and the DBR layer of the chip can be combined more tightly, and the strength of the thimble resistance experiment of the chip is improved. Meanwhile, the design of adding the TiPt layer between the two Au layers reduces the thickness of the Au layer while ensuring the structural strength, thereby reducing the use of Au and further reducing the overall design cost.
In the results of the thimble experiment batch shown in fig. 2, it can be seen that the results of the thimble experiment on the chip manufactured by the above scheme are that the serious breakage is 12.5%, the slight breakage is 48.75%, and the non-breakage rate is 38.75%. Compared with the conventional method, the method has the advantage that the lossless rate of 6.75 is greatly improved. In the small batch repeat validation results shown in fig. 3, the severe damage was 2.5%, the slight damage was 50%, and the non-damage rate was 47.5%.
In particular, it includes the steps of,
manufacturing a first layer Cr layer, and plating a film on the surface of the chip at a plating rate of 0.2A/S;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5 Ang/S;
alternately evaporating 3 layers of the Ti layer and the Pt layer, plating the Ti layer at the plating rate of 1A/S, and plating the Pt layer at the plating rate of 1A/S to form a TiPt composite layer of the 3-8 th layer;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
a 10Ti layer and an 11 th Pt layer are evaporated, the Ti layer is plated at the plating rate of 1A/S, and the Pt layer is plated at the plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th Ti layer, and plating a Ti layer at the plating rate of 1A/S.
Through the setting of the plating rate, the inside of each film layer is more compact, the combination between the film layers is more compact while the performance is ensured, and therefore the experimental performance of the ejector pin is improved.
Specifically, the method comprises the steps of manufacturing a 1 st Cr layer, and plating the surface of a chip with a plating rate of 0.2A/S;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5 Ang/S;
alternately evaporating 3 layers of a Ti layer and a Pt layer, plating the Ti layer at the plating rate of 2A/S, and plating the Pt layer at the plating rate of 1A/S to form a TiPt composite layer of the 3-8 th layer;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
a 10 < th > Ti layer and a 11 < th > Pt layer are evaporated, the Ti layer is plated at the plating rate of 2A/S, and the Pt layer is plated at the plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th Ti layer, and plating a Ti layer at the plating rate of 2A/S.
Through the setting of different plating rates, can let each rete inside compacter, can let the combination between each rete more inseparable when guaranteeing the performance to promote thimble experimental performance.
Manufacturing a first layer Cr layer, wherein the thickness of a plated film is 30A;
manufacturing a 2 nd layer AlCu alloy layer, wherein the coating thickness is 1500 Ang;
alternately evaporating 3 Ti layers and 3 Pt layers, wherein the thickness of each Ti layer is 600A, and the thickness of each Pt layer is 500A, so as to form a TiPt composite layer of the 3-8 th layer;
manufacturing a 9 th Au layer, wherein the thickness of a plated film is 11000 ANG;
evaporating a film with a thickness of 1500A on a 10Ti layer, and evaporating an 11 Pt layer with a film thickness of 700A;
manufacturing a 12 th Au layer, and plating a film with the thickness of 1000 ANG;
and manufacturing a 13 th Ti layer, and coating with the thickness of 500A. The thickness scheme allows for a 15% error adjustment, and the overall performance of the electrode can be better played through the thickness design of each layer.
In other embodiments, the method includes the step of,
manufacturing a first layer Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 30A;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1500A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 600A, each layer of Ti is subjected to film plating at 300A at a plating rate of 1A/S, and then subjected to film plating at 300A at a plating rate of 2A/S, each layer of Pt has a thickness of 500A, and a TiPt composite layer of a 3-8 layer is formed; each layer of Ti is 600A thick, each layer of Pt is 500A thick, and a TiPt composite layer of the 3-8 layer is formed;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 11000A;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, wherein the coating thickness is 1500A, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S, wherein the coating thickness is 700A;
manufacturing a 12 th Au layer, and plating a film with the thickness of 1000A at the plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the plating thickness is 500A.
According to the scheme, the Ti film is formed at different rates in the composite layer of the Ti layer and the Pt layer, so that the formed Ti is more compact, the performance is better, and the thimble resistance experiment performance is stronger.
In still further embodiments, a 1 st Cr layer was fabricated, and the surface of the chip was plated at a plating rate of 0.2 a/S, the plating thickness being 27 a;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1350A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 540A, each layer of Ti is subjected to film plating of 270A at a plating rate of 1A/S, and then subjected to film plating of 270A at a plating rate of 2A/S, each layer of Pt has a thickness of 450A, and a TiPt composite layer of a 3-8 layer is formed; forming a TiPt composite layer of the 3-8 th layer by using the Ti layer with a thickness of 540A and the Pt layer with a thickness of 450A;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 9900A;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, wherein the coating thickness is 1350A, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S, wherein the coating thickness is 630A;
manufacturing a 12 th Au layer, and plating a film with a thickness of 900A at a plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the thickness of the plated film is 450A.
According to the scheme, the Ti film is formed at different rates in the composite layer of the Ti layer and the Pt layer, so that the formed Ti is more compact, the performance is better, and the thimble resistance experiment performance is stronger.
In other embodiments, the method includes the step of,
manufacturing a first layer Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 33A;
manufacturing an AlCu alloy layer on the 2 nd layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1650A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 660, each layer of Ti is subjected to film plating of 330A at a plating rate of 1A/S, and then subjected to film plating of 330A at a plating rate of 2A/S, each layer of Pt has a thickness of 500A, and a TiPt composite layer of a 3-8 layer is formed; forming a TiPt composite layer of the 3-8 th layer by using the Ti layer with a thickness of 660A and the Pt layer with a thickness of 550A;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 12100A;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, wherein the coating thickness is 1650A, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S, wherein the coating thickness is 770A;
manufacturing a 12 th Au layer, and plating a film with a thickness of 1100A at a plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the thickness of the plated film is 550A.
According to the scheme, the Ti film is formed at different rates in the composite layer of the Ti layer and the Pt layer, so that the formed Ti is more compact, the performance is better, and the thimble resistance experiment performance is stronger.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present patent.
Claims (8)
1. A manufacturing method of a flip electrode is characterized by comprising the following steps,
manufacturing a 1 st Cr layer;
manufacturing a 2 nd AlCu alloy layer;
alternately evaporating 3 Ti layers and 3 Pt layers, wherein each Ti layer is plated at a plating rate of 1A/S, and then plated at a plating rate of 2A/S to form a TiPt composite layer of the 3-8 th layer;
manufacturing an Au layer of a 9 th layer, wherein the thickness of a plated film is 11000 +/-15% of A;
a 10Ti layer is evaporated, the thickness of a plated film is 1500 +/-15 percent of A, and the thickness of a plated film is 700 +/-15 percent of A on an 11 th layer of Pt;
manufacturing a 12 th Au layer, wherein the thickness of a plated film is 1000 +/-15% of A;
the 13 th Ti layer was produced.
2. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,
manufacturing a first layer Cr layer, and coating the surface of the chip with a plating rate of 0.2A/S;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5 Ang/S;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
a 10Ti layer and an 11 th Pt layer are evaporated, the Ti layer is plated at the plating rate of 1A/S, and the Pt layer is plated at the plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th Ti layer, and plating a Ti layer at the plating rate of 1A/S.
3. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,
manufacturing a first layer Cr layer, and coating the surface of the chip with a plating rate of 0.2A/S;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5 Ang/S;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
a 10 < th > Ti layer and a 11 < th > Pt layer are evaporated, the Ti layer is plated at the plating rate of 2A/S, and the Pt layer is plated at the plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th Ti layer, and plating a Ti layer at the plating rate of 2A/S.
4. The method of manufacturing a flip-chip electrode according to claim 1, comprising the steps of,
manufacturing a first layer Cr layer, wherein the thickness of a plated film is 30A;
manufacturing an AlCu alloy layer on the 2 nd layer, wherein the thickness of a plated film is 1500 angstroms;
and manufacturing a 13 th Ti layer, and coating with the thickness of 500A.
5. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,
manufacturing a first layer Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 30A;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1500A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 600A, each layer of Ti is subjected to film plating at 300A at a plating rate of 1A/S, and then subjected to film plating at 300A at a plating rate of 2A/S, each layer of Pt has a thickness of 500A, and a TiPt composite layer of a 3-8 layer is formed; each layer of Ti is 600A thick, each layer of Pt is 500A thick, and a TiPt composite layer of the 3-8 layer is formed;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S;
manufacturing a 12 th Au layer, and plating a film at a plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the plating thickness is 500A.
6. The method of manufacturing a flip-chip electrode according to claim 1, comprising the steps of,
manufacturing a first layer Cr layer, and plating a film on the surface of the chip at a plating rate of 0.2A/S, wherein the thickness of the plated film is 27A;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1350A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 540A, each layer of Ti is subjected to film plating of 270A at a plating rate of 1A/S, and then subjected to film plating of 270A at a plating rate of 2A/S, each layer of Pt has a thickness of 450A, and a TiPt composite layer of a 3-8 layer is formed; forming a TiPt composite layer of the 3-8 th layer by using the Ti layer with a thickness of 540A and the Pt layer with a thickness of 450A;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 9900A;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, wherein the coating thickness is 1350A, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S, wherein the coating thickness is 630A;
manufacturing a 12 th Au layer, and plating a film with a thickness of 900A at a plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the thickness of the plated film is 450A.
7. The method for fabricating a flip chip electrode according to claim 1, comprising the steps of,
manufacturing a first layer Cr layer, and coating the surface of the chip at a coating rate of 0.2A/S, wherein the coating thickness is 33A;
manufacturing a 2 nd layer AlCu alloy layer, and plating a film at a plating rate of 5A/S, wherein the thickness of the plated film is 1650A;
alternately evaporating 3 layers of a Ti layer and a Pt layer, wherein each layer of Ti has a thickness of 660, each layer of Ti is subjected to film plating of 330A at a plating rate of 1A/S, and then subjected to film plating of 330A at a plating rate of 2A/S, each layer of Pt has a thickness of 500A, and a TiPt composite layer of a 3-8 layer is formed; forming a TiPt composite layer of the 3-8 th layer by using the Ti layer with a thickness of 660A and the Pt layer with a thickness of 550A;
manufacturing a 9 th Au layer, and plating a film at a plating rate of 10A/S, wherein the thickness of the plated film is 12100A;
evaporating a 10 th layer Ti layer, performing Ti layer coating at the plating rate of 1A/S, wherein the coating thickness is 1650A, evaporating an 11 th layer Pt layer, and performing Pt layer coating at the plating rate of 1A/S, wherein the coating thickness is 770A;
manufacturing a 12 th Au layer, and plating a film with a thickness of 1100A at a plating rate of 10A/S;
and manufacturing a 13 th layer Ti layer, and plating a Ti layer at the plating rate of 2A/S, wherein the thickness of the plated film is 550A.
8. A flip chip electrode made according to the method of any one of claims 1-7.
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