CN112638105A - Power module and packaging method thereof - Google Patents
Power module and packaging method thereof Download PDFInfo
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- CN112638105A CN112638105A CN202011560566.1A CN202011560566A CN112638105A CN 112638105 A CN112638105 A CN 112638105A CN 202011560566 A CN202011560566 A CN 202011560566A CN 112638105 A CN112638105 A CN 112638105A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/14—Mounting supporting structure in casing or on frame or rack
- H05K7/1422—Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames
- H05K7/1427—Housings
- H05K7/1432—Housings specially adapted for power drive units or power converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
Abstract
The invention discloses a power module and a packaging method thereof, wherein the power module comprises an upper power module and a lower power module; the upper power module comprises a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit; the copper-clad ceramic substrate unit comprises a copper-clad ceramic substrate of a grid electrode, a source electrode, an auxiliary source electrode and a drain electrode; the copper-clad ceramic substrates of the drain electrode and the source electrode are arranged in a laminated manner; the signal collecting region unit comprises a signal collecting region of a grid, a source, an auxiliary source and a drain; the signal collecting areas are respectively arranged on the copper-clad parts of the corresponding copper-clad ceramic substrates; the chip parallel unit comprises three MOSFET chips connected in parallel; the grid, the source, the auxiliary source and the drain of the MOSFET chip are respectively connected with the corresponding signal collection regions; the upper power module and the lower power module have the same structure; the source signal collection region of the upper power module is connected with the drain signal collection region of the lower power module. The invention can improve the uniformity of current distribution.
Description
Technical Field
The invention relates to the technical field of module packaging, in particular to a power module and a packaging method thereof.
Background
In recent years, silicon-based (Si) power semiconductor devices have been limited by materials approaching their intrinsic limits of materials, and it has been difficult to meet the higher demands of power electronic equipment. Wide bandgap power semiconductor devices represented by silicon carbide (SiC) are gradually applied to the fields of high frequency, high temperature and high power electronics by virtue of their high bandgap width, high critical electric field breakdown field strength and high thermal conductivity. Due to the fact that commercial mass production of silicon carbide Metal-Oxide-semiconductor field effect transistors (MOSFET) devices is low in current level, parallel connection of devices with low cost and high reliability is an important means for meeting the requirement of high-power application.
The current power module is internally provided with a plurality of chips which are connected in parallel to realize a larger current level, but with the increase of the number of chips connected in parallel, factors such as circuit layout asymmetry and common branch impedance coupling effect can cause uneven distribution of branch stray inductance between the chips connected in parallel, and further cause unbalanced current distribution between the chips connected in parallel, so unbalanced switching loss and electric stress are generated, and devices with overlarge current distribution can fail under severe conditions, thereby endangering the safety of other parallel devices.
Disclosure of Invention
The invention aims to provide a power module and a packaging method thereof, which aim to solve the problem of uneven distribution of branch stray inductance among parallel chips caused by asymmetric circuit layout and the influence of impedance coupling effect of a common branch in the power module in the prior art.
In order to achieve the purpose, the invention provides the following scheme:
a power module includes an upper power module and a lower power module;
the upper power module comprises a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit;
the copper-clad ceramic substrate unit comprises a grid copper-clad ceramic substrate, a source copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate and a drain copper-clad ceramic substrate; the drain electrode copper-clad ceramic substrate and the source electrode copper-clad ceramic substrate are stacked;
the signal collection region unit comprises a grid signal collection region, a source signal collection region, an auxiliary source signal collection region and a drain signal collection region; the grid signal collection region is arranged on copper cladding of the grid copper-clad ceramic substrate; the source electrode signal collection region is arranged on copper cladding of the source electrode copper-clad ceramic substrate; the auxiliary source electrode signal collection region is arranged on copper cladding of the auxiliary source electrode copper cladding ceramic substrate; the drain electrode signal collection area is arranged on copper cladding of the drain electrode copper cladding ceramic substrate;
the chip parallel unit comprises a silicon carbide metal-oxide semiconductor field effect transistor (MOSFET) chip parallel group; the MOSFET chips are connected in parallel and are three mutually parallel MOSFET chips; the MOSFET chips are arranged on the drain copper-clad ceramic substrate in parallel; the grid electrodes of the MOSFET chip parallel groups are connected with the grid electrode signal collection area through bonding wires; the source electrodes of the MOSFET chip parallel groups are connected with the source electrode signal collecting area through bonding wires; the auxiliary source electrodes of the MOSFET chip parallel group are connected with the auxiliary source electrode signal collection area through bonding wires; the drain electrode of the MOSFET chip parallel group is arranged on the copper-clad layer of the drain electrode copper-clad ceramic substrate;
the upper power module and the lower power module have the same structure; and the source signal collection region of the upper power module is connected with the drain signal collection region of the lower power module.
Optionally, the chip parallel unit further includes: the silicon carbide diode chips are connected in parallel; the diode chip parallel group comprises three silicon carbide diode chips which are connected in parallel and are parallel to each other; the diode chips are arranged on the drain copper-clad ceramic substrate in a parallel connection mode; the anode of the diode chip parallel group is connected with the source electrode of the MOSFET chip parallel group through a bonding wire, the anode of the diode chip parallel group is connected with the source electrode signal collecting area through a bonding wire, and the cathode of the diode chip parallel group is arranged on the copper-clad layer of the drain electrode copper-clad ceramic substrate.
Optionally, the method further comprises: a signal terminal unit; the signal terminal unit is of a flat structure;
the signal terminal unit includes a gate driving signal terminal, a source power signal terminal, an auxiliary source driving signal terminal, and a drain power signal terminal; the grid driving signal terminal is connected with the grid signal collecting region; the source power signal terminal is connected with the source signal collecting region; the auxiliary source electrode driving signal terminal is connected with the auxiliary source electrode signal collecting region; the drain power signal terminal is connected to the drain signal collection region.
Optionally, the three parallel-connected and mutually parallel MOSFET chips are equally spaced.
Optionally, the three parallel-connected and mutually parallel diode chips are equally spaced.
A power module packaging method, which is applied to the power module, the power module packaging method comprising:
a silicon carbide MOSFET chip area is arranged on a drain copper-clad ceramic substrate of the upper power module; arranging a grid signal collection area on copper cladding of a grid copper cladding ceramic substrate of the upper power module; a source electrode signal collecting area is arranged on copper cladding of a source electrode copper cladding ceramic substrate of the upper power module; an auxiliary source electrode signal collection area is arranged on copper cladding of an auxiliary source electrode copper cladding ceramic substrate of the upper power module; a drain signal collecting area is arranged on copper cladding of a drain copper cladding ceramic substrate of the upper power module; stacking a drain electrode copper-clad ceramic substrate and a source electrode copper-clad ceramic substrate in the upper power module;
three silicon carbide MOSFET chips which are connected in parallel and are mutually parallel are welded in the silicon carbide MOSFET chip area of the upper power module;
welding the drain electrode of the MOSFET chip of the upper power module on the copper-clad layer of the drain electrode copper-clad ceramic substrate; connecting the gate of the MOSFET chip of the upper power module to the gate signal collection region through a bonding wire; connecting an auxiliary source of the MOSFET chip of an upper power module to the auxiliary source signal collection region through a bonding wire; connecting the source of the MOSFET chip of the upper power module to the source signal collection region through a bonding wire;
preparing a lower power module with the same structure as the upper power module; connecting the source signal collection region of the upper power module and the drain signal collection region of the lower power module; and pouring a liquid compound into the upper power module and the lower power module, and curing the liquid compound into the thermosetting polymer insulating material under the normal temperature condition or the heating condition.
Optionally, the method further comprises:
a silicon carbide diode chip area is arranged on the drain electrode copper-clad ceramic substrate of the upper power module; welding three parallel silicon carbide diode chips in the silicon carbide diode chip area; welding the cathode of the diode chip on the copper cladding of the drain electrode copper cladding ceramic substrate; and connecting the anode of the diode chip with the source electrode of the MOSFET chip through a bonding wire, and connecting the anode of the diode chip with the source electrode signal collection region through the bonding wire.
Optionally, the method further comprises:
welding a grid driving signal terminal in the grid signal collection area of the upper power module; welding a source power signal terminal in the source signal collection area of the upper power module; welding an auxiliary source electrode driving signal terminal in the auxiliary source electrode signal collection area of the upper power module; welding a drain power signal terminal in the drain signal collection area of the upper power module; and welding the grid electrode driving signal terminal, the source electrode power signal terminal, the auxiliary source electrode driving signal terminal and the drain electrode power signal terminal into a flat structure.
Optionally, the three parallel-connected and mutually parallel MOSFET chips are equally spaced.
Optionally, the three parallel-connected and mutually parallel diode chips are equally spaced.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a power module and a packaging method thereof, which utilize the characteristic that the current flow directions of a drain side branch and a source side branch between chips connected in parallel in the power module are opposite, and a drain copper-clad ceramic substrate and a source copper-clad ceramic substrate are arranged in a laminated manner, so that the distance-to-width ratio between the two substrates is increased, the magnetic field coupling between the two substrates is enhanced, further, the mutual inductance is enhanced to offset the branch stray inductance between parallel devices, the distribution difference of the stray inductance of a main power loop between the chips is reduced, and the uniformity of current distribution is improved. And adopt the signal terminal of platyzing structure, reduced the complexity of signal terminal design, promoted the convenience of installation. Meanwhile, the current flow directions of the drain power signal terminal of the upper power module and the source power signal terminal of the lower power module are opposite, the stray inductance of the main power loop can be further reduced by utilizing mutual inductance, and the electrical stress of the switching transient power module is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a block diagram of a power module according to an embodiment of the present invention;
fig. 2 is a structural diagram of an upper power module of a power module according to an embodiment of the present invention;
fig. 3 is a top view of an upper power module of a power module provided in an embodiment of the present invention;
fig. 4 is a structural diagram of a lower power module of the power module provided in the embodiment of the present invention;
FIG. 5 is a schematic diagram of a dual pulse test circuit of a power module according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a copper-clad ceramic substrate of a power module according to an embodiment of the invention;
fig. 7 is a schematic diagram of a chip parallel unit of an upper power module according to an embodiment of the present invention.
Description of the symbols: an upper power module 1, a lower power module 2, a bonding wire 3, an auxiliary source drive signal terminal 4, a gate drive signal terminal 5, a drain power signal terminal 6, a source power signal terminal 7, a MOSFET chip parallel group 8, a diode chip parallel group 9, a gate copper-clad ceramic substrate 10, an auxiliary source copper-clad ceramic substrate 11, a source copper-clad ceramic substrate 12, a drain copper-clad ceramic substrate 13, a drain signal collection region 14, a source signal collection region 15, a gate signal collection region 16, an auxiliary source signal collection region 17, a drain power signal terminal 18 of the lower power module, a drain copper-clad ceramic substrate 19 of the lower power module, a drain signal collection region 20 of the lower power module, a diode chip parallel group 21 of the lower power module, a source copper-clad ceramic substrate 22 of the lower power module, a MOSFET chip parallel group 23 of the lower power module, A source signal collection region 24 of the lower power module, an auxiliary source copper-clad ceramic substrate 25 of the lower power module, an auxiliary source driving signal terminal 26 of the lower power module, an auxiliary source signal collection region 27 of the lower power module, a source power signal terminal 28 of the lower power module, a gate copper-clad ceramic substrate 29 of the lower power module, a gate driving signal terminal 30 of the lower power module, and a gate signal collection region 31 of the lower power module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a power module and a packaging method thereof, which utilize the characteristic that the current flow directions of a drain electrode side branch and a source electrode side branch between parallel devices in the power module are opposite, and the drain electrode copper-clad ceramic substrate and the source electrode copper-clad ceramic substrate are stacked to enhance mutual inductance to offset branch stray inductance between the parallel devices, so that the distribution difference of stray inductance of a main power loop between chips is reduced, and the uniformity of current distribution is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a structural diagram of a power module according to an embodiment of the present invention, and as shown in fig. 1, a power module includes an upper power module 1 and a lower power module 2;
fig. 2 is a structural diagram of an upper power module of a power module according to an embodiment of the present invention, fig. 3 is a top view of the upper power module of the power module according to the embodiment of the present invention, and fig. 7 is a schematic diagram of a chip parallel unit of the upper power module according to the embodiment of the present invention, and as shown in fig. 2, fig. 3 and fig. 7, the upper power module 1 includes a copper-clad ceramic substrate unit, a signal collection area unit, and a chip parallel unit; the copper-clad ceramic substrate unit comprises a grid copper-clad ceramic substrate 10, a source copper-clad ceramic substrate 12, an auxiliary source copper-clad ceramic substrate 11 and a drain copper-clad ceramic substrate 13; the drain copper-clad ceramic substrate 13 and the source copper-clad ceramic substrate 12 are stacked.
The signal collection region unit comprises a grid signal collection region 16, a source signal collection region 15, an auxiliary source signal collection region 17 and a drain signal collection region 14; the grid signal collection region 16 is arranged on copper cladding of the grid copper-clad ceramic substrate 10; the source signal collection region 15 is arranged on the copper cladding of the source copper-clad ceramic substrate 12; the auxiliary source electrode signal collection region 17 is arranged on copper cladding of the auxiliary source electrode copper-clad ceramic substrate 11; the drain signal collection region 14 is provided on the copper clad of the drain copper clad ceramic substrate 13.
The chip parallel unit comprises a silicon carbide metal-oxide semiconductor field effect transistor MOSFET chip parallel group 8; the MOSFET chip parallel group 8 is three MOSFET chips which are connected in parallel and are mutually parallel; the MOSFET chip parallel group 8 is arranged on the drain copper-clad ceramic substrate 13; the grid of the MOSFET chip parallel group 8 is connected with the grid signal collection area 16 through a bonding wire 3; the source electrode of the MOSFET chip parallel group 8 is connected with the source electrode signal collection area 15 through a bonding wire 3; the auxiliary source electrode of the MOSFET chip parallel group 8 is connected with the auxiliary source electrode signal collection region 17 through a bonding wire 3; and the drain electrode of the MOSFET chip parallel group 8 is arranged on the copper-clad part of the drain electrode copper-clad ceramic substrate 13.
The upper power module 1 and the lower power module 2 have the same structure; the source signal collection region 15 of the upper power module 1 is connected to the drain signal collection region 20 of the lower power module.
In practical applications, the chip parallel unit further includes: the silicon carbide diode chips are connected in parallel 9; the diode chip parallel group 9 is three silicon carbide diode chips which are connected in parallel and are parallel to each other; the diode chip parallel group 9 is arranged on the drain copper-clad ceramic substrate 13; the anode of the diode chip parallel group 9 is connected with the source of the MOSFET chip parallel group 8 through a bonding wire 3, the anode of the diode chip parallel group 9 is connected with the source signal collecting region 15 through the bonding wire 3, and the cathode of the diode chip parallel group 9 is arranged on the copper-clad layer of the drain copper-clad ceramic substrate 13. The cathode of the diode chip parallel group 9 and the drain of the MOSFET chip parallel group 8 are both disposed on the copper-clad layer of the drain copper-clad ceramic substrate 13, so that the cathode of the diode chip parallel group 9 and the drain of the MOSFET chip parallel group 8 are electrically connected. As shown in fig. 7, three MOSFET drains and three diode cathodes are all soldered on the copper clad of the drain copper clad ceramic substrate 13, so that the MOSFET drains and the diode cathodes are connected.
In practical application, the method further comprises the following steps: a signal terminal unit; the signal terminal unit is of a flat structure;
the signal terminal unit comprises a gate driving signal terminal 5, a source power signal terminal 7, an auxiliary source driving signal terminal 4 and a drain power signal terminal 6; the gate driving signal terminal 5 is connected to the gate signal collection region 16; the source power signal terminal 7 is connected to the source signal collection region 15; the auxiliary source drive signal terminal 4 is connected to the auxiliary source signal collection region 17; the drain power signal terminal 6 is connected to the drain signal collection region 14.
In practical applications, the three parallel MOSFET chips are equally spaced from each other.
In practical application, the three diode chips connected in parallel and parallel to each other are equally spaced.
Fig. 4 is a structural diagram of a lower power module of a power module according to an embodiment of the present invention, and as shown in fig. 4, a drain copper clad ceramic substrate 19 of the lower power module and a source copper clad ceramic substrate 22 of the lower power module are stacked.
The grid signal collection area 31 of the lower power module is arranged on copper cladding of the grid copper-clad ceramic substrate 29 of the lower power module; the source signal collection region 24 of the lower power module is arranged on the copper cladding of the source copper-clad ceramic substrate 22 of the lower power module; the auxiliary source signal collection region 27 of the lower power module is arranged on the copper cladding of the auxiliary source copper-clad ceramic substrate 25 of the lower power module; the drain signal collection region 20 of the lower power module is arranged on the copper-clad layer of the drain copper-clad ceramic substrate 19 of the lower power module.
The parallel group 23 of the MOSFET chips of the lower power module is three parallel MOSFET chips connected in parallel and parallel to each other; the MOSFET chip parallel group 23 of the lower power module is arranged on the drain copper-clad ceramic substrate 19 of the lower power module; the grid of the parallel group 23 of the MOSFET chips of the lower power module is connected with the grid signal collection area 31 of the lower power module through a bonding wire 3; the source of the parallel group 23 of MOSFET chips of the lower power module is connected to the source signal collection region 24 of the lower power module by a bonding wire 3; the auxiliary source of the parallel group 23 of MOSFET chips of the lower power module is connected to the auxiliary source signal collection region 27 of the lower power module through a bonding wire 3; the drain electrode of the MOSFET chip parallel group 23 of the lower power module is arranged on the copper-clad layer of the drain electrode copper-clad ceramic substrate 19 of the lower power module. The diode chip parallel group 21 of the lower power module is three silicon carbide diode chips which are connected in parallel and are parallel to each other; the diode chip parallel group 21 of the lower power module is arranged on the drain copper-clad ceramic substrate 19 of the lower power module; the anode of the diode chip parallel group 21 of the lower power module is connected with the source of the MOSFET chip parallel group 23 of the lower power module through a bonding wire 3, the anode of the diode chip parallel group 21 of the lower power module is connected with the source signal collection region 24 of the lower power module through the bonding wire 3, and the cathode of the diode chip parallel group 21 of the lower power module is arranged on the copper-clad layer of the drain copper-clad ceramic substrate 19 of the lower power module. The cathode of the diode chip parallel group 21 of the lower power module and the drain of the MOSFET chip parallel group 23 of the lower power module are both arranged on the copper-clad layer of the drain copper-clad ceramic substrate 19 of the lower power module, so that the cathode of the diode chip parallel group 21 of the lower power module and the drain of the MOSFET chip parallel group 23 of the lower power module are electrically connected.
The gate driving signal terminal 30 of the lower power module is connected with the gate signal collection region 31 of the lower power module; the source power signal terminal 28 of the lower power module is connected to the source signal collection region 24 of the lower power module; the auxiliary source driving signal terminal 26 of the lower power module is connected with the auxiliary source signal collection region 27 of the lower power module; the drain power signal terminal 18 of the lower power module is connected to the drain signal collection region 20 of the lower power module, and the gate driving signal terminal 30 of the lower power module, the source power signal terminal 28 of the lower power module, the auxiliary source driving signal terminal 26 of the lower power module, and the drain power signal terminal 18 of the lower power module are all in a flat structure. The intervals between the three parallel-connected and mutually parallel MOSFET chips of the lower power module are equal, and the intervals between the three parallel-connected and mutually parallel diode chips of the lower power module are equal.
A power module packaging method, which is applied to the power module, the power module packaging method comprising:
a silicon carbide MOSFET chip area is arranged on a drain copper-clad ceramic substrate 13 of the upper power module 1; a grid signal collection area 16 is arranged on copper cladding of a grid copper-clad ceramic substrate 10 of the upper power module 1; a source signal collection area 15 is arranged on the copper cladding of a source copper-clad ceramic substrate 12 of the upper power module 1; an auxiliary source signal collection region 17 is arranged on copper cladding of an auxiliary source copper-clad ceramic substrate 11 of the upper power module 1; a drain signal collection region 14 is arranged on the copper cladding of a drain copper-clad ceramic substrate 13 of the upper power module 1; the drain copper clad ceramic substrate 13 and the source copper clad ceramic substrate 12 in the upper power module 1 are placed by lamination.
And three parallel silicon carbide MOSFET chips are welded in the silicon carbide MOSFET chip area of the upper power module 1.
Connecting the gate of the MOSFET chip of the upper power module 1 to the gate signal collection region 16 through a bonding wire 3; connecting the auxiliary source of the MOSFET chip of the upper power module 1 to the auxiliary source signal collection region 17 through a bonding wire 3; connecting the source of the MOSFET chip of the upper power module 1 to the source signal collection region 15 through a bonding wire 3; and welding the drain electrode of the MOSFET chip of the upper power module 1 on the copper-clad part of the drain electrode copper-clad ceramic substrate 13.
Preparing a lower power module 2 with the same structure as the upper power module 1; connecting the source signal collection region 15 of the upper power module 1 and the drain signal collection region 20 of the lower power module; and pouring a liquid compound into the upper power module 1 and the lower power module 2, and curing the liquid compound into a thermosetting polymer insulating material under a normal temperature condition or a heating condition.
In practical application, the method further comprises the following steps:
a silicon carbide diode chip area is arranged on the drain copper-clad ceramic substrate 13 of the upper power module 1; welding three parallel silicon carbide diode chips in the silicon carbide diode chip area; and connecting the anode of the diode chip with the source electrode of the MOSFET chip through a bonding wire 3, connecting the anode of the diode chip with the source electrode signal collection area 15 through the bonding wire 3, and welding the cathode of the diode chip on the copper-clad layer of the drain electrode copper-clad ceramic substrate 13.
In practical application, the method further comprises the following steps:
welding a gate drive signal terminal 5 to the gate signal collection region 16 of the upper power module 1; welding a source power signal terminal 7 to the source signal collection region 15 of the upper power module 1; welding an auxiliary source driving signal terminal 4 to the auxiliary source signal collection region 17 of the upper power module 1; welding a drain power signal terminal 6 on the drain signal collection area 14 of the upper power module 1; the gate drive signal terminal 5, the source power signal terminal 7, the auxiliary source drive signal terminal 4, and the drain power signal terminal 6 are all soldered to a flattened structure.
In practical applications, the three parallel MOSFET chips are equally spaced from each other.
In practical application, the three diode chips connected in parallel and parallel to each other are equally spaced.
The power module utilizes the characteristic that the current flow directions of the drain side branch and the source side branch between the parallel devices are opposite, the drain electrode copper-clad ceramic substrate and the source electrode copper-clad ceramic substrate are arranged in a laminated mode, the distance-to-width ratio between the two substrates is increased, the magnetic field coupling between the two substrates is enhanced, further, the mutual inductance is enhanced to offset branch stray inductance between the parallel devices, the distribution difference of main power loop stray inductance between chips is reduced, and therefore the uniformity of current distribution is improved.
The principle of enhancing mutual inductance is as follows: as shown in fig. 6, the length of the two conductors is l, the width of the two conductors is w, and the distance between the two conductors is d, and the stacked placement can increase the distance-to-width ratio v of the two conductors, so as to enhance the magnetic field coupling of the two conductors, and further enhance the mutual inductance. The mutual inductance calculation formula is as follows:
wherein the aspect ratio v is the ratio of d to w, μ is the ratio of l to w, μ0A permeability of 4 π × 10 for vacuum-7N/A2T is the thickness of the copper clad in the thin copper sheet or the copper clad ceramic substrate of the present invention, the thickness of the copper clad in the present invention is negligible 0.3048mm, t is considered to be 0, M represents the mutual inductance in the present invention, and the formula can be expressed by the following formula:
LM(t＝0)the mutual inductance value between two conductors with length of l is represented when the copper-clad thickness is neglected, namely t is 0,
namely, it is
The value of mutual inductance between two conductors per unit length (when l is 1 m) is expressed.
The signal terminals are flat structures, so that the complexity of the signal terminal design is reduced, and the convenience of installation is improved;
the drain power signal terminal 6 of the upper power module 1 and the source power signal terminal 28 of the lower power module are respectively connected with the positive pole and the negative pole of a power supply, the current flow directions of the drain power signal terminal 6 and the source power signal terminal 28 of the lower power module are opposite, when the current flow directions are opposite, the mutual inductance M is negative, the parasitic inductance is self-inductance L-mutual inductance M, when the current flow directions are the same, the mutual inductance M is positive, and the parasitic inductance is self-inductance L + mutual inductance M. Therefore, the parasitic inductance is reduced by the mutual inductance M through selecting the current flow direction to be opposite during design, the stray inductance of the main power loop is further reduced, and the electrical stress of the switching transient power module is reduced.
By adopting the power module and the packaging method thereof, the distribution difference of circuit stray inductance caused by circuit layout mismatching and common branch impedance coupling effect can be reduced, and better parallel current sharing characteristic of the silicon carbide MOSFET is realized.
The power module in the invention also has good heat dissipation effect, the chip is positioned at the bottom layer of the module by adopting the general design in the prior art, only the radiator can be added at the bottom layer, the chip is positioned at the upper layer and the bottom layer of the power module by adopting the laminated placement, so that two radiators can be added at the upper layer and the bottom layer for heat dissipation, and even if the radiator is not added, the chip can also carry out double-sided heat dissipation through the upper layer and the lower layer of substrates, namely two substrates, and the heat dissipation effect is better than that of the general single-sided heat dissipation.
FIG. 5 is a schematic diagram of a dual-pulse test circuit of a power module according to an embodiment of the present invention, as shown in FIG. 5, UDCThe power module is a direct current voltage source and is used for supplying power to a power loop of the power module. In fig. 5, the upper broken line indicates a power circuit, and the lower broken line indicates a drive circuit. CDCThe bus capacitor is used for maintaining the stability of the direct current voltage. L isloadAnd D is three parallel silicon carbide diodes in the upper power module 1, and is used for follow current when three parallel silicon carbide MOSFETs in the lower power module 2 are turned off. Q1Is the silicon carbide MOSFET, Q in the lower power module 2 closest to the drain signal power terminal 182Is a silicon carbide MOSFET, Q in the lower power module of the power module that is spaced a moderate distance from the drain signal power terminal 183Is the silicon carbide MOSFET, L, of the lower power module of the power module furthest from the drain signal power terminal 18d1Is Q1Of the drain side stray inductance, Ls1Is Q1Source side stray inductance of, Las1Is Q1Auxiliary source stray inductance of, Ld2Is Q2Of the drain side stray inductance, Ls2Is Q2Source side stray inductance of, Las2Is Q2Auxiliary source stray inductance of, Ld3Is Q3Of the drain side stray inductance, Ls3Is Q3Source side stray inductance of, Las3Is Q3Auxiliary source stray inductance of, Ld12Is Q1、Q2Stray inductance between drain side branches, Ld23Is Q2、Q3Stray inductance between drain side branches, Ls12Is Q1、Q2Stray inductance between source side branches, Ls23Is Q2、Q3Stray inductance between source side branches, M12Is Q1、Q2Mutual inductance between drain side branches and source side branches of (1), M23Is Q2、Q3Mutual inductance between drain side branches and source side branches of (1)LFor the current flowing through the load inductance, id1To flow through Q1Current of (i)d2To flow through Q2Current of (i)d3To flow through Q3Current of (i)d23To flow through Q2、Q3Current of (i)as1To flow through Q1Auxiliary source current of ias2To flow through Q2Auxiliary source current of ias3To flow through Q3The auxiliary source current of (1). VdriverFor the gate drive power supply, for supplying power to the drive circuit, RgIs a gate drive resistor. The following deduces and proves that the power module utilizes mutual inductance to reduce the difference of stray inductance between parallel devices and realizes better parallel current sharing characteristics of the silicon carbide MOSFET.
The drain current of a silicon carbide MOSFET chip can be represented by idCan be expressed by the following expression
Wherein g isfsIs transconductance, V, of a silicon carbide MOSFETgsIs the gate-source voltage, VthIs the threshold voltage. VgsCan be expressed by the following expression in the driving circuit
The unbalanced current of the parallel silicon carbide MOSFET chips can be expressed by the following expression
Writing the KVL equation to the power and drive loop columns may be expressed by the following expression
The unbalanced current of the parallel silicon carbide MOSFET chip obtained by the above formula can be expressed by the following expression:
by adopting the power module, the characteristic that the current flow directions of the side branch of the drain electrode and the side branch of the source electrode between the parallel devices are opposite is utilized, the distance-width ratio between the two substrates is increased by arranging the copper-clad ceramic substrate of the drain electrode and the copper-clad ceramic substrate of the source electrode in a laminated manner, the magnetic field coupling between the two substrates is enhanced, further, the mutual inductance is enhanced to offset the stray inductance of the branch between the parallel devices, the unbalanced current between the parallel devices is reduced, and the better parallel current-sharing characteristic of the silicon carbide MOSFET is realized.
Of course, the above principle description is not limited to the embodiments of the present invention, the above embodiments and the drawings are only used to illustrate the technical solutions of the present invention, and the present invention is not limited thereto, when there are n devices connected in parallel, the drain side branch and the source side branch between the two devices may also be formed by stacking the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate to enhance mutual inductance, so as to reduce the difference in stray inductance between the devices connected in parallel, and reduce the unbalanced current of the devices connected in parallel.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. A power module, comprising an upper power module and a lower power module;
the upper power module comprises a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit;
the copper-clad ceramic substrate unit comprises a grid copper-clad ceramic substrate, a source copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate and a drain copper-clad ceramic substrate; the drain electrode copper-clad ceramic substrate and the source electrode copper-clad ceramic substrate are stacked;
the signal collection region unit comprises a grid signal collection region, a source signal collection region, an auxiliary source signal collection region and a drain signal collection region; the grid signal collection region is arranged on copper cladding of the grid copper-clad ceramic substrate; the source electrode signal collection region is arranged on copper cladding of the source electrode copper-clad ceramic substrate; the auxiliary source electrode signal collection region is arranged on copper cladding of the auxiliary source electrode copper cladding ceramic substrate; the drain electrode signal collection area is arranged on copper cladding of the drain electrode copper cladding ceramic substrate;
the chip parallel unit comprises a silicon carbide metal-oxide semiconductor field effect transistor (MOSFET) chip parallel group; the MOSFET chips are connected in parallel and are three mutually parallel MOSFET chips; the MOSFET chips are arranged on the drain copper-clad ceramic substrate in parallel; the grid electrodes of the MOSFET chip parallel groups are connected with the grid electrode signal collection area through bonding wires; the source electrodes of the MOSFET chip parallel groups are connected with the source electrode signal collecting area through bonding wires; the auxiliary source electrodes of the MOSFET chip parallel group are connected with the auxiliary source electrode signal collection area through bonding wires; the drain electrode of the MOSFET chip parallel group is arranged on the copper-clad layer of the drain electrode copper-clad ceramic substrate;
the upper power module and the lower power module have the same structure; and the source signal collection region of the upper power module is connected with the drain signal collection region of the lower power module.
2. The power module of claim 1, wherein the chip parallel unit further comprises: the silicon carbide diode chips are connected in parallel; the diode chip parallel group comprises three silicon carbide diode chips which are connected in parallel and are parallel to each other; the diode chips are arranged on the drain copper-clad ceramic substrate in a parallel connection mode; the anode of the diode chip parallel group is connected with the source electrode of the MOSFET chip parallel group through a bonding wire, the anode of the diode chip parallel group is connected with the source electrode signal collecting area through a bonding wire, and the cathode of the diode chip parallel group is arranged on the copper-clad layer of the drain electrode copper-clad ceramic substrate.
3. The power module of claim 2, further comprising: a signal terminal unit; the signal terminal unit is of a flat structure;
the signal terminal unit includes a gate driving signal terminal, a source power signal terminal, an auxiliary source driving signal terminal, and a drain power signal terminal; the grid driving signal terminal is connected with the grid signal collecting region; the source power signal terminal is connected with the source signal collecting region; the auxiliary source electrode driving signal terminal is connected with the auxiliary source electrode signal collecting region; the drain power signal terminal is connected to the drain signal collection region.
4. The power module of claim 3, wherein the three parallel connected and mutually parallel MOSFET chips are equally spaced.
5. The power module of claim 4, wherein the three parallel-connected and mutually parallel diode chips are equally spaced.
6. A power module packaging method, wherein the power module packaging method is applied to the power module according to any one of claims 1 to 5, and the power module packaging method comprises:
a silicon carbide MOSFET chip area is arranged on a drain copper-clad ceramic substrate of the upper power module; arranging a grid signal collection area on copper cladding of a grid copper cladding ceramic substrate of the upper power module; a source electrode signal collecting area is arranged on copper cladding of a source electrode copper cladding ceramic substrate of the upper power module; an auxiliary source electrode signal collection area is arranged on copper cladding of an auxiliary source electrode copper cladding ceramic substrate of the upper power module; a drain signal collecting area is arranged on copper cladding of a drain copper cladding ceramic substrate of the upper power module; stacking a drain electrode copper-clad ceramic substrate and a source electrode copper-clad ceramic substrate in the upper power module;
three silicon carbide MOSFET chips which are connected in parallel and are mutually parallel are welded in the silicon carbide MOSFET chip area of the upper power module;
welding the drain electrode of the MOSFET chip of the upper power module on the copper-clad layer of the drain electrode copper-clad ceramic substrate; connecting the gate of the MOSFET chip of the upper power module to the gate signal collection region through a bonding wire; connecting an auxiliary source of the MOSFET chip of an upper power module to the auxiliary source signal collection region through a bonding wire; connecting the source of the MOSFET chip of the upper power module to the source signal collection region through a bonding wire;
preparing a lower power module with the same structure as the upper power module; connecting the source signal collection region of the upper power module and the drain signal collection region of the lower power module; and pouring a liquid compound into the upper power module and the lower power module, and curing the liquid compound into the thermosetting polymer insulating material under the normal temperature condition or the heating condition.
7. The power module packaging method of claim 6, further comprising:
a silicon carbide diode chip area is arranged on the drain electrode copper-clad ceramic substrate of the upper power module; welding three parallel silicon carbide diode chips in the silicon carbide diode chip area; welding the cathode of the diode chip on the copper cladding of the drain electrode copper cladding ceramic substrate; and connecting the anode of the diode chip with the source electrode of the MOSFET chip through a bonding wire, and connecting the anode of the diode chip with the source electrode signal collection region through the bonding wire.
8. The power module packaging method of claim 7, further comprising:
welding a grid driving signal terminal in the grid signal collection area of the upper power module; welding a source power signal terminal in the source signal collection area of the upper power module; welding an auxiliary source electrode driving signal terminal in the auxiliary source electrode signal collection area of the upper power module; welding a drain power signal terminal in the drain signal collection area of the upper power module; and welding the grid electrode driving signal terminal, the source electrode power signal terminal, the auxiliary source electrode driving signal terminal and the drain electrode power signal terminal into a flat structure.
9. The power module packaging method of claim 8, wherein the three parallel connected and mutually parallel MOSFET chips are equally spaced.
10. The power module packaging method of claim 9, wherein the three parallel-connected and mutually parallel diode chips are equally spaced.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113391180A (en) * | 2021-05-07 | 2021-09-14 | 西安交通大学 | Dynamic characteristic test platform for silicon carbide device at extremely high temperature |
| CN114141744A (en) * | 2021-10-15 | 2022-03-04 | 西安交通大学 | SiC MOSFET submodule unit crimping type encapsulation |
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113391180A (en) * | 2021-05-07 | 2021-09-14 | 西安交通大学 | Dynamic characteristic test platform for silicon carbide device at extremely high temperature |
| CN113391180B (en) * | 2021-05-07 | 2022-03-01 | 西安交通大学 | Dynamic characteristic test platform for silicon carbide device at extremely high temperature |
| CN114141744A (en) * | 2021-10-15 | 2022-03-04 | 西安交通大学 | SiC MOSFET submodule unit crimping type encapsulation |
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