CN112637444A - NTP millisecond clock synchronization algorithm of multi-path 4k splicing system - Google Patents
NTP millisecond clock synchronization algorithm of multi-path 4k splicing system Download PDFInfo
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Abstract
The invention discloses an NTP millisecond clock synchronization algorithm of a multi-path 4k splicing system, belongs to the field of internet communication, relates to a millisecond clock synchronization algorithm technology, and is used for solving the problem of NTP millisecond clock synchronization in the multi-path 4k splicing system; the invention has the advantages of low cost: according to the invention, the NTP clock server with low price is used, and one clock server can be used as a time-setting clock source of a plurality of acquisition boards, so that the cost for implementing synchronous acquisition of a direct-current power grid is effectively saved; high time synchronization precision: the time synchronization precision realized by the invention is far better than the time synchronization mode of the traditional pulse per second matched with the NTP message network; nimble pulse output need not the external circuit that expands, practices thrift system design, and the implementation cost: the system can output continuous pulses coincident with absolute time after time synchronization is finished, and the continuous pulses are supplied to the electric quantity acquisition module to serve as synchronous acquisition signals.
Description
Technical Field
The invention belongs to the field of internet communication, and relates to a millisecond clock synchronization algorithm technology, in particular to an NTP millisecond clock synchronization algorithm of a multi-path 4k splicing system.
Background
On the internet, there is no clear index requirement on the design of general computers and internet devices in terms of time stability. The clock oscillators of these devices operate in a free-running condition that is not calibrated. There are some errors between the oscillation frequency of the clock and the calibration frequency due to settling variations, electromagnetic interference, aging of the oscillator, and production debugging. These errors appear negligible at first sight, but have a considerable effect after long-term accumulation. Assuming a device that uses a relatively high accuracy clock, say 0.001%, it will produce an error of only 10 microseconds in one second, a clock skew of approximately 1 second a day, and an error of more than 5 minutes after one year of operation. Time synchronization on the internet is of great significance. In many applications, time is a very important consideration. As the internet has evolved to extend to all aspects of society, there are also many demands on time synchronization in other areas of the network, such as various real-time online transactions, manufacturing process control, time-allocation of communication networks, distributed network computing and processing, etc. applications that require precise, reliable, and well-established time. NTP (Network Time Protocol) is intended to transmit uniform and standard Time over the internet, and a specific implementation scheme is to set up a plurality of clock source websites on the Network to provide Time service for users, and these websites should be able to compare with each other to improve accuracy. PTP (Precision Time Protocol) is a Protocol defined by IEEE1588 and capable of realizing high-Precision clock synchronization in a measurement and control system. The PTP protocol integrates a plurality of technologies such as network communication, local computation, and distributed object, and is applicable to all distributed systems that communicate via a local area network supporting multicast, and is particularly applicable to ethernet, but not limited to ethernet. The protocol can synchronize various clocks with different accuracies, resolutions and stabilities in a heterogeneous system, and can achieve sub-microsecond synchronization accuracy, and only occupies a small amount of network and local computing resources.
Disclosure of Invention
The invention aims to provide an NTP millisecond clock synchronization algorithm of a multi-path 4k splicing system, which is used for solving the problem of NTP millisecond clock synchronization in the multi-path 4k splicing system.
The purpose of the invention can be realized by the following technical scheme:
the NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system comprises a redundancy module, a transmission module, an Ethernet time synchronization module and a quartz crystal oscillator compensation module;
the Ethernet time synchronization module is used for receiving Ethernet time and transmitting the Ethernet time to the multi-path 4k splicing system through the transmission module;
the multi-path 4k splicing system is internally provided with a quartz crystal oscillator compensation module, the quartz crystal oscillator compensation module is used for providing timing for the multi-path 4k splicing system in a time gap of receiving Ethernet twice at the front and the back, and the method comprises the following specific steps:
receiving Ethernet time, and resetting the time of a quartz crystal oscillator compensation module to the Ethernet receiving time;
step two: after reset according to the formula
Obtaining clock frequency deviation alpha; wherein TC is a deviation value between an actual frequency and a nominal frequency of the quartz crystal oscillator in the quartz crystal oscillator compensation module; wherein phi is a voltage coefficient; wherein ν x wd is a temperature coefficient, ν is the current temperature, wd is a preset temperature scaling coefficient;
step three: substituting the clock frequency deviation alpha into a formula tcn which is alpha × tsn to obtain the NTP time tcn;
step four: the NTP time tcn is transmitted to a redundancy module through a transmission module for backup, and the NTP time tcn is transmitted to a multi-path 4k splicing system;
step five: and re-receiving the Ethernet time, and repeating the steps from one step to four.
Further, the deviation value between the actual frequency and the nominal frequency specifically includes obtaining the actual frequency D1 of the quartz crystal oscillator, obtaining the nominal frequency D2 of the quartz crystal oscillator, and obtaining the deviation value TC between the actual frequency and the nominal frequency by a formula D2-D1 × [ (Φ × k) + (ν × wd) ].
Further, the current temperature is acquired by a temperature sensor; the voltage coefficient phi is represented by the formula phi ═ IFruit of Chinese wolfberry×RFruit of Chinese wolfberryTo obtain in the formula IFruit of Chinese wolfberryCircuit real time current, R, for quartz crystal oscillatorFruit of Chinese wolfberryIs a real-time resistance of a quartz crystal oscillator circuit, said IFruit of Chinese wolfberryCollected by a current sensor, RFruit of Chinese wolfberryAnd (4) collecting through a resistance sensor.
Further, the receiving of the ethernet time specifically includes performing data connection with an ethernet time synchronization device, where the ethernet time synchronization device includes a time processing module CPU, the time processing module CPU is connected with a clock processing FPGA through a BUS, connected with a GPS receiving module through a serial port, and connected with an IEEE1588 ground synchronous network module through a time synchronization signal, the IEEE1588 ground synchronous network module includes an IXP425 processor and an IEEE1588FPGA interface, a low temperature drift crystal oscillator is accessed as a crystal oscillator source to an FPGA phase-locked loop, the clock processing FPGA, the IEEE1588 ground synchronous network module and the time processing module CPU are provided with a time synchronization signal output interface, the time processing module CPU is a 32-bit ARM9 processor, and the time processing module CPU includes an ARM 9:
a time reference source discrimination module: judging a time reference source to obtain reference time, entering a crystal oscillator timekeeping state under the condition of satellite loss, and automatically switching to an IEEE1588 working mode after a large deviation occurs in timekeeping;
the signal processing module: processing the output of various serial port time synchronization communication messages and pulse time synchronization signals in various interface modes;
the IEEE1588FPGA interface comprises the following functional modules:
a clock type judging module: judging according to the time quality of the GPS, wherein the higher the time quality is, the higher the clock class is; if the clock class of the clock equipment selects a fixed clock class, the clock class of the clock equipment is a fixed value and cannot change along with the time quality of the GPS; selecting the optimal clock class of each IEEE1588 port according to the optimal clock algorithm;
the best main clock distinguishing module: the clock equipment is used for comparing the clock class of the clock equipment with the optimal clock class of each IEEE1588 port, if the clock class of the clock equipment is optimal, the clock equipment selects a master clock mode, otherwise, the clock equipment is in a slave clock mode;
adjusting a clock module: continuously adjusting the time of the local clock according to the network delay and deviation calculation until the time is synchronous with the time of the main clock, and if the local clock is in a main clock mode, not adjusting the local clock;
and sending an IEEE1588 ground synchronous network module time synchronization pulse module: the clock equipment is in a slave clock mode, and after the local clock is adjusted, a time tick pulse signal is sent to the time processing module CPU, at the moment, if the time processing module CPU judges that the time tick signal quality of the IEEE1588 ground synchronous network module is superior to the time quality of the clock equipment, the time tick pulse signal is switched to the IEEE1588 mode, and if the clock equipment is in a master clock mode, the time tick pulse is not sent;
the ARM9 processor is also provided with remote configuration software for remotely monitoring the running state, function customization and parameter modification of the time synchronization device.
Further, the low-temperature drift crystal oscillator is a low-temperature drift time crystal oscillator with the precision of 0.05 PPM.
Furthermore, the clock processing FPGA is connected with the signal expansion board to complete the interface between various common time setting expansion signals and the CPU of the time processing module.
Further, the IXP425 processor comprises a clock offset processing module, and calculates IEEE1588 network delay measurement and clock offset measurement by adopting an IEEE1588V2 time tracking algorithm according to the structure of the network;
and the filtering module is used for filtering the data of the network delay measurement and the clock offset measurement to obtain a relatively accurate value.
Furthermore, the time tick signal output interface comprises a PPS/PPM/PPH/DCF77/IRIG-B pulse signal level interface and supports output of time-of-second pulses, serial messages, NTP protocols, IRIG-B codes, DCF77 and IEEE1588 time signals.
Furthermore, the PPS/PPM/PPH/DCF77/IRIG-B pulse signal level interface meets the four types of TTL, 24V, differential 485 and passive empty nodes, all output signals are isolated by optical couplers, wherein the differential 485 signals are not only isolated by the optical couplers, but also isolated by DC-DC, and the isolation withstand voltage is more than 2500V.
Further, the IRIG-B pulse signal level interface is provided with a multimode ST optical fiber synchronous interface, and a time reference source can be provided for the spread clock device through an optical fiber.
Compared with the prior art, the invention has the beneficial effects that:
1. the advantages of low cost are as follows: the invention uses the NTP clock server with low price, and one clock server can be used as a time-setting clock source of a plurality of acquisition boards, thereby effectively saving the cost of synchronous acquisition and implementation of the direct-current power grid.
2. High time synchronization precision: the time synchronization precision realized by the invention is far better than the time synchronization mode of the traditional second pulse matched with the NTP message network.
3. Nimble pulse output need not the external circuit that expands, practices thrift system design, and the implementation cost: the system can output continuous pulses coincident with absolute time after time synchronization is finished, and the continuous pulses are supplied to the electric quantity acquisition module to serve as synchronous acquisition signals. The duty ratio, the period and the start-stop time of the pulse are completely realized by software, and a hardware circuit can provide a corresponding pulse group according to practical application without any modification, so that the realization difficulty and the system cost of the direct-current power grid electric quantity synchronous acquisition system are greatly saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic block diagram of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Thus, the detailed description of the embodiments of the present invention provided in the following drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention.
As shown in fig. 1, the NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system includes a redundancy module, a transmission module, an ethernet time synchronization module, and a quartz crystal oscillator compensation module;
the Ethernet time synchronization module is used for receiving Ethernet time and transmitting the Ethernet time to the multi-path 4k splicing system through the transmission module;
be equipped with quartz crystal oscillator compensation module in the multichannel 4k concatenation system, quartz crystal oscillator compensation module is used for in the two time receiving ethernet time gaps in front and back, provides the timing for multichannel 4k concatenation system, and the concrete step is:
receiving Ethernet time, and resetting the time of a quartz crystal oscillator compensation module to the Ethernet receiving time;
step two: after reset according to the formula
Obtaining clock frequency deviation alpha; wherein TC is a deviation value between an actual frequency and a nominal frequency of the quartz crystal oscillator in the quartz crystal oscillator compensation module; wherein phi is a voltage coefficient; wherein ν x wd is a temperature coefficient, ν is the current temperature, wd is a preset temperature scaling coefficient;
the actual frequency and nominal frequency deviation value is specifically that the actual frequency D1 of the quartz crystal oscillator is obtained, the nominal frequency D2 of the quartz crystal oscillator is obtained, and the actual frequency and nominal frequency deviation value TC is obtained through a formula | D2-D1| × [ (φ × k) + (ν × wd) ];
the current temperature is acquired through a temperature sensor; the voltage coefficient phi is determined by the formula phi ═ IFruit of Chinese wolfberry×RFruit of Chinese wolfberryTo obtain in the formula IFruit of Chinese wolfberryCircuit real time current, R, for quartz crystal oscillatorFruit of Chinese wolfberryIs a real-time resistor of a quartz crystal oscillator circuit, IFruit of Chinese wolfberryCollected by a current sensor, RFruit of Chinese wolfberryCollecting through a resistance sensor;
step three: substituting the clock frequency deviation alpha into a formula tcn which is alpha × tsn to obtain the NTP time tcn;
step four: the NTP time tcn is transmitted to a redundancy module through a transmission module for backup, and the NTP time tcn is transmitted to a multi-path 4k splicing system;
step five: and re-receiving the Ethernet time, and repeating the steps from one step to four.
The Ethernet time receiving device is specifically characterized in that the Ethernet time receiving device is in data connection with the Ethernet time synchronization device, the Ethernet time synchronization device comprises a time processing module CPU, the time processing module CPU is connected with a clock processing FPGA through a BUS BUS, and is connected with a GPS receiving module through a serial port, and is connected with an IEEE1588 ground synchronous network module through a time synchronization signal, the IEEE1588 ground synchronous network module comprises an IXP425 processor and an IEEE1588FPGA interface, a low-temperature drift crystal oscillator is connected into an FPGA phase-locked loop as a crystal oscillator source, the clock processing FPGA, the IEEE1588 ground synchronous network module and the time processing module CPU are provided with a time synchronization signal output interface, the time processing module CPU is a 32-bit ARM9 processor, and the ARM9 processor comprises:
a time reference source discrimination module: judging a time reference source to obtain reference time, entering a crystal oscillator timekeeping state under the condition of satellite loss, and automatically switching to an IEEE1588 working mode after a large deviation occurs in timekeeping;
the signal processing module: processing the output of various serial port time synchronization communication messages and pulse time synchronization signals in various interface modes;
the IEEE1588FPGA interface comprises the following functional modules:
a clock type judging module: judging according to the time quality of the GPS, wherein the higher the time quality is, the higher the clock class is; if the clock class of the clock equipment selects a fixed clock class, the clock class of the clock equipment is a fixed value and cannot change along with the time quality of the GPS; selecting the optimal clock class of each IEEE1588 port according to the optimal clock algorithm;
the best main clock distinguishing module: the clock equipment is used for comparing the clock class of the clock equipment with the optimal clock class of each IEEE1588 port, if the clock class of the clock equipment is optimal, the clock equipment selects a master clock mode, otherwise, the clock equipment is in a slave clock mode;
adjusting a clock module: continuously adjusting the time of the local clock according to the network delay and deviation calculation until the time is synchronous with the time of the main clock, and if the local clock is in a main clock mode, not adjusting the local clock;
and sending an IEEE1588 ground synchronous network module time synchronization pulse module: the clock equipment is in a slave clock mode, and after the local clock is adjusted, a time tick pulse signal is sent to the time processing module CPU, at the moment, if the time processing module CPU judges that the time tick signal quality of the IEEE1588 ground synchronous network module is superior to the time quality of the clock equipment, the time tick pulse signal is switched to the IEEE1588 mode, and if the clock equipment is in a master clock mode, the time tick pulse is not sent;
the ARM9 processor is also provided with remote configuration software for remotely monitoring the running state, function customization and parameter modification of the time synchronization device.
The low-temperature drift crystal oscillator is a low-temperature drift time-keeping crystal oscillator with the precision of 0.05 PPM.
The clock processing FPGA is connected with the signal expansion board to complete the interface between various common time-setting expansion signals and the CPU of the time processing module.
The IXP425 processor comprises a clock skew processing module, and calculates IEEE1588 network delay measurement and clock skew measurement by adopting an IEEE1588V2 time tracking algorithm according to the structure of the network;
and the filtering module is used for filtering the data of the network delay measurement and the clock offset measurement to obtain a relatively accurate value.
The time signal output interface comprises a PPS/PPM/PPH/DCF77/IRIG-B pulse signal level interface and supports the output of time signals of second time-sharing pulse, serial port message, NTP protocol, IRIG-B code, DCF77 and IEEE 1588.
PS/PPM/PPH/DCF77/IRIG-B pulse signal level interfaces meet the requirements of TTL, 24V, differential 485 and passive empty nodes, all output signals are isolated by optical couplers, differential 485 signals are isolated by the optical couplers, channels are isolated by DC-DC, and isolation withstand voltage is more than 2500V.
The IRIG-B pulse signal level interface is provided with a multimode ST optical fiber synchronous interface, and can provide a time reference source for the spread clock device through an optical fiber.
The invention is implemented as follows:
the multi-path 4k splicing system firstly receives the Ethernet time and compensates the module of the quartz crystal oscillatorResetting time to Ethernet receiving time according to formula
Obtaining clock frequency deviation alpha; wherein TC is a deviation value between an actual frequency and a nominal frequency of the quartz crystal oscillator in the quartz crystal oscillator compensation module; wherein phi is a voltage coefficient; wherein ν x wd is a temperature coefficient, ν is the current temperature, wd is a preset temperature scaling coefficient; substituting the clock frequency deviation alpha into a formula tcn which is k multiplied by tsn to obtain NTP time tcn; the NTP time tcn is transmitted to a redundancy module through a transmission module for backup, and the NTP time tcn is transmitted to a multi-path 4k splicing system at the same time, so that NTP millisecond clock synchronization of the multi-path 4k splicing system is completed.
The above formulas are all calculated by taking the numerical value of the dimension, the formula is a formula which obtains the latest real situation by acquiring a large amount of data and performing software simulation, and the preset parameters in the formula are set by the technical personnel in the field according to the actual situation.
In the embodiments provided by the present invention, it should be understood that the disclosed apparatus, device and method can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical functional division, and there may be other divisions when the actual implementation is performed; the modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the method of the embodiment.
It will also be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof.
The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned.
Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the system claims may also be implemented by one unit or means in software or hardware. The terms second, etc. are used to denote names, but not any particular order.
Finally, it should be noted that the above examples are only intended to illustrate the technical process of the present invention and not to limit the same, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical process of the present invention without departing from the spirit and scope of the technical process of the present invention.
Claims (10)
1. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system is characterized by comprising a redundancy module, a transmission module, an Ethernet time synchronization module and a quartz crystal oscillator compensation module;
the Ethernet time synchronization module is used for receiving Ethernet time and transmitting the Ethernet time to the multi-path 4k splicing system through the transmission module;
the multi-path 4k splicing system is internally provided with a quartz crystal oscillator compensation module, the quartz crystal oscillator compensation module is used for providing timing for the multi-path 4k splicing system in a time gap of receiving Ethernet twice at the front and the back, and the method comprises the following specific steps:
receiving Ethernet time, and resetting the time of a quartz crystal oscillator compensation module to the Ethernet receiving time;
step two: after reset according to the formula
Obtaining clock frequency deviation alpha; wherein TC is quartz crystalThe deviation value of the actual frequency and the nominal frequency of the quartz crystal oscillator in the oscillator compensation module; wherein phi is a voltage coefficient; wherein ν x wd is a temperature coefficient, ν is the current temperature, wd is a preset temperature scaling coefficient;
step three: substituting the clock frequency deviation alpha into a formula tcn which is alpha × tsn to obtain the NTP time tcn; tsn is oscillation time;
step four: the NTP time tcn is transmitted to a redundancy module through a transmission module for backup, and the NTP time tcn is transmitted to a multi-path 4k splicing system;
step five: and re-receiving the Ethernet time, and repeating the steps from one step to four.
2. The NTP millisecond clock synchronization algorithm for the multi-path 4k splicing system according to claim 1, wherein the deviation value between the actual frequency and the nominal frequency is specifically obtained by obtaining the actual frequency D1 of the quartz crystal oscillator, obtaining the nominal frequency D2 of the quartz crystal oscillator, and obtaining the deviation value TC between the actual frequency and the nominal frequency by using a formula | D2-D1| × [ (Φ × k) + (ν × wd) ].
3. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 1, wherein the current temperature is collected by a temperature sensor; the voltage coefficient phi is represented by the formula phi ═ IFruit of Chinese wolfberry×RFruit of Chinese wolfberryTo obtain in the formula IFruit of Chinese wolfberryCircuit real time current, R, for quartz crystal oscillatorFruit of Chinese wolfberryIs a real-time resistance of a quartz crystal oscillator circuit, said IFruit of Chinese wolfberryCollected by a current sensor, RFruit of Chinese wolfberryAnd (4) collecting through a resistance sensor.
4. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 1, wherein the received ethernet time is specifically data-connected to an ethernet time synchronization device, the ethernet time synchronization device includes a time processing module CPU, the time processing module CPU is connected to a clock processing FPGA through a BUS, connected to a GPS receiving module through a serial port, and connected to an IEEE1588 ground synchronous network module through a time synchronization signal, the IEEE1588 ground synchronous network module includes an IXP425 processor and an IEEE1588FPGA interface, the low temperature drift crystal oscillator is connected to the FPGA as a crystal oscillator source, the clock processing FPGA, the IEEE1588 ground synchronous network module and the time processing module CPU are provided with a time synchronization signal output interface, the time processing module CPU is a 32-bit ARM9 processor, and the ARM9 processor includes:
a time reference source discrimination module: judging a time reference source to obtain reference time, entering a crystal oscillator timekeeping state under the condition of satellite loss, and automatically switching to an IEEE1588 working mode after a large deviation occurs in timekeeping;
the signal processing module: processing the output of various serial port time synchronization communication messages and pulse time synchronization signals in various interface modes;
the IEEE1588FPGA interface comprises the following functional modules:
a clock type judging module: judging according to the time quality of the GPS, wherein the higher the time quality is, the higher the clock class is; if the clock class of the clock equipment selects a fixed clock class, the clock class of the clock equipment is a fixed value and cannot change along with the time quality of the GPS; selecting the optimal clock class of each IEEE1588 port according to the optimal clock algorithm;
the best main clock distinguishing module: the clock equipment is used for comparing the clock class of the clock equipment with the optimal clock class of each IEEE1588 port, if the clock class of the clock equipment is optimal, the clock equipment selects a master clock mode, otherwise, the clock equipment is in a slave clock mode;
adjusting a clock module: continuously adjusting the time of the local clock according to the network delay and deviation calculation until the time is synchronous with the time of the main clock, and if the local clock is in a main clock mode, not adjusting the local clock;
and sending an IEEE1588 ground synchronous network module time synchronization pulse module: the clock equipment is in a slave clock mode, and after the local clock is adjusted, a time tick pulse signal is sent to the time processing module CPU, at the moment, if the time processing module CPU judges that the time tick signal quality of the IEEE1588 ground synchronous network module is superior to the time quality of the clock equipment, the time tick pulse signal is switched to the IEEE1588 mode, and if the clock equipment is in a master clock mode, the time tick pulse is not sent;
the ARM9 processor is also provided with remote configuration software for remotely monitoring the running state, function customization and parameter modification of the time synchronization device.
5. The NTP millisecond clock synchronization algorithm for the multi-path 4k splicing system according to claim 4, wherein the low temperature drift crystal oscillator is a low temperature drift time-keeping crystal oscillator with the precision of 0.05 PPM.
6. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 4, wherein the clock processing FPGA is connected with a signal expansion board to complete interfaces between various common time setting expansion signals and a time processing module CPU.
7. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 4, wherein the IXP425 processor comprises a clock offset processing module, and calculates IEEE1588 network delay measurement and clock offset measurement by adopting an IEEE1588V2 time tracking algorithm according to the structure of a network;
and the filtering module is used for filtering the data of the network delay measurement and the clock offset measurement to obtain a relatively accurate value.
8. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 4, wherein the time-tick signal output interface comprises a PPS/PPM/PPH/DCF77/IRIG-B pulse signal level interface, and supports second time-sharing pulse, serial port message, NTP protocol, IRIG-B code, DCF77 and IEEE1588 time signal output.
9. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 8, wherein the PPS/PPM/PPH/DCF77/IRIG-B pulse signal level interface meets the four types of TTL, 24V, differential 485 and passive null nodes, all output signals are isolated by optical couplers, the differential 485 signals are not only isolated by the optical couplers, but also isolated by DC-DC, and the isolation withstand voltage is more than 2500V.
10. The NTP millisecond clock synchronization algorithm of the multi-path 4k splicing system according to claim 9, wherein the IRIG-B pulse signal level interface has a multimode ST fiber synchronization interface, and a time reference source can be provided for the spread clock device through an optical fiber.
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