CN112637027A

CN112637027A - Frame boundary defining device based on UART (universal asynchronous receiver/transmitter), transmitting method and receiving method

Info

Publication number: CN112637027A
Application number: CN202011531186.5A
Authority: CN
Inventors: 邵枝晖; 肖磊
Original assignee: Beijing Neuron Network Technology Co ltd
Current assignee: Beijing Neuron Network Technology Co ltd
Priority date: 2020-12-22
Filing date: 2020-12-22
Publication date: 2021-04-09
Anticipated expiration: 2040-12-22
Also published as: CN112637027B

Abstract

The application relates to a frame boundary defining device, a frame boundary sending method and a frame boundary receiving method based on UART, wherein the frame boundary defining device and the frame boundary sending method based on UART comprise the following steps: the sending buffer is used for receiving and buffering the communication information to be sent in the communication information frame to be sent from the preset processor; and the transmission arbitration shifter is used for shifting the communication information to be transmitted to the UART from the transmission buffer, so that the communication information to be transmitted is transmitted to a preset communication link through the asynchronous receiving and transmitting transmitter, and effective waiting is carried out, so that the idle time of data transmission of the UART after the communication information to be transmitted is ensured to be more than or equal to a preset time interval.

Description

Frame boundary defining device based on UART (universal asynchronous receiver/transmitter), transmitting method and receiving method

Technical Field

The present technology belongs to the field of industrial communication, and in particular, relates to a UART-based information transmission method, a UART-based information reception method, a UART-based frame boundary defining apparatus, an electronic device, and a communication system.

Background

Currently, a serial communication method is often used in the field of industrial communication. For example, UART (universal asynchronous receiver transmitter) is used for serial communication, and data communication is performed in a serial communication manner in units of characters by using a serial communication bus.

Some application layer communication protocols (such as modbus) that run on top of this mechanism are in the form of data frames as the communication transport unit. Also in such communication protocols, there is often a strict time specification on the frame-to-frame spacing (such as the 3.5 character free range required between modbus protocol frames).

The mainstream implementation manner in the industry is that the frames of the protocol data frames are delimited by the CPU system, and then serial transmission in units of characters is performed by the UART terminal. And the time interval control between frames is realized by a time delay control method carried out by a CPU system. In general, the processing speed of UARTs is relatively low. The control of UART transmissions by the CPU on a character-by-character basis can slow the CPU execution, place some load on the CPU system, and process relatively inefficiently.

Disclosure of Invention

Based on this, the present application provides a frame boundary defining apparatus based on UART, comprising: the sending buffer is used for receiving and buffering the communication information to be sent in the communication information frame to be sent from the preset processor; and the transmission arbitration shifter is used for shifting the communication information to be transmitted to the UART from the transmission buffer, so that the communication information to be transmitted is transmitted to a preset communication link through the asynchronous receiving and transmitting transmitter, and effective waiting is carried out, so that the idle time of data transmission of the UART after the communication information to be transmitted is ensured to be more than or equal to a preset time interval.

The present application further provides a frame boundary defining apparatus based on UART, comprising: the receiving buffer buffers the received communication information in the received communication information frame and sends the received communication information to the preset processor; and the receiving arbitration shifter acquires received communication information from the UART, the received communication information is received from the preset communication link by the UART, the receiving arbitration shifter buffers the received communication information in the receiving buffer, and if the receiving dead time of the UART is more than or equal to the preset time interval, the received communication information is packaged into a received communication information frame.

The application also provides a UART-based information sending method, which is characterized by comprising the following steps: acquiring a communication information frame from a preset processor; moving the communication information in the communication information frame to a UART (universal asynchronous receiver transmitter), so that the communication information is sent to a preset communication link by the asynchronous receiver transmitter one by one; after the communication information in the communication information frame is sent, effective waiting is carried out to ensure that the idle time of data sending of the UART is more than or equal to a preset time interval after the communication information frame is sent.

The present application further provides a UART-based information receiving method, which is characterized by comprising: acquiring communication information from a UART character by character, wherein the communication information is received from a preset communication link by the UART character by character; sending the communication information to a preset processor; and detecting the idle time of data receiving of the UART, and if the idle time is more than or equal to a preset time interval, closing the plate, wherein the communication information is a communication information frame.

The present application also provides an electronic device, comprising: a processor; UART; any one of the above devices, connected between the processor and the UART.

The application further provides a communication system, which is characterized by comprising any one of the electronic devices.

The present application also provides a chip, which is characterized by comprising: any one of the foregoing devices; at least one of a processor and a UART coupled to the apparatus.

The device, the information sending method, the information receiving method, the electronic equipment, the communication system and the chip are utilized. Frame boundary delineation for the predetermined protocol may be performed using processor-independent means. The apparatus may be disposed between the processor and the UART interface unit. And frame boundary delineation can be performed automatically by the device during communication. And may reduce the workload of the processor to some extent. The working energy of the processor can be saved to process more valuable work.

For example, when communication is performed according to a communication frame protocol based on time delay, the end of the communication information to be sent can be defined by using the tail tag at the sending end, and the device can be used to automatically control the time interval between frames. The processor may transfer at least one frame of communication information directly into the frame boundary defining means. And the at least one frame of communication information may be buffered in a buffer in the frame boundary defining means. At which time the processor may switch to processing other transactions. The frame boundary delimiting means may transmit the communication information in the frame of the frame communication information character by character to the preset communication link through the UART. And may effectively wait at the end of a frame to ensure that the time interval between frames is a preset time interval. The automatic control of the time interval between frames is realized through the method.

The time interval between the reception of character information may be detected at the receiving end and the frame-to-frame interval may be defined according to the interval. And encapsulating the received communication into a complete communication frame based on the determination of the interval. And may prompt the processor to receive the communication information frame and may prompt the processor to read the communication information frame.

By using the mode, the workload of the processor can be effectively reduced, so that the system efficiency can be improved. When other communication protocols are adopted for communication, the technical solutions provided by the present application may also have similar technical effects, which are not described herein.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without exceeding the protection scope of the present application.

Fig. 1 is a schematic diagram illustrating a UART-based communication system in the prior art.

Fig. 2 is a schematic diagram illustrating the components of the UART-based frame boundary defining apparatus according to an embodiment of the present application.

Fig. 3 is a block diagram of a UART-based frame boundary defining apparatus according to an embodiment of the present application.

Fig. 4 shows a schematic diagram of waveforms when a communication information frame is received by the apparatus shown in fig. 3.

Fig. 5 is a flowchart illustrating a UART-based information transmitting method according to another embodiment of the present application.

Fig. 6 is a flowchart illustrating a UART-based information receiving method according to another embodiment of the present application.

Fig. 7 shows a schematic composition diagram of an electronic device according to another embodiment of the present application.

Fig. 8 shows a schematic block diagram of a communication system according to another embodiment of the present application.

Fig. 9 is a schematic diagram illustrating a communication path from the electronic device 711 to the electronic device 712 in the communication system illustrated in fig. 8.

FIG. 10 shows a block diagram of an electronic device according to an example embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Current communication systems based on a communication frame protocol with time delay generally adopt a topology as shown in fig. 1. At a sending end, a processor 111 performs packing on data according to a preset communication protocol to obtain a communication information frame, and stores the communication information frame in a memory (RAM), where the memory may be built in the processor 111 or connected to the processor 111. The processor 111 may further transmit the communication information to the UART112 of the transmitting end, and transmit the communication information to the UART122 of the receiving end through a predetermined communication link by the UART 112. The processor 121 at the receiving end may receive the communication information from the UART122 and perform frame parsing.

For example, the modbus protocol requires a time interval corresponding to 3.5 character transmission time between frames during communication, and thus the communication system requires the processor 111 at the transmitting end to control the interval between frames when transmitting information. It is also desirable that the processor 121 at the receiving end detect the interval between characters to determine whether a complete communication frame has been received. Therefore, the workload of the processor is increased to a certain extent, and the working efficiency of the system is reduced.

As shown in fig. 2, the frame boundary defining apparatus 2000 is a frame boundary defining apparatus for a transmitting end. The frame boundary defining device 2000 may include a transmission buffer 21 and a transmission arbitration shifter 22.

As shown in fig. 2, the transmission buffer 21 may be connected to a processor 28. The transmission buffer 21 receives and buffers the communication information to be transmitted in the communication information frame to be transmitted from the processor 28.

Alternatively, the transmission buffer 21 may include a memory. The memory may include at least one write interface coupled to the processor 28 for receiving communication information in a frame of communication information to be transmitted; the memory may also include at least one read interface, connected to the transport arbitration mover 22, for moving the communication information. Further, the transmission buffer 21 may include a dual-port random access memory, and two read/write ports of the dual-port random access memory are respectively connected to the processor 28 and the transmission arbitration shifter 22. Alternatively, the transmission buffer 21 may be a first-in-first-out buffer (FIFO).

Alternatively, the transmission buffer 21 may be connected to the processor 28 via a bus. The transmission buffer 21 may be connected to the processor 28 via a serial data bus, or may be connected to the processor 28 via a parallel data bus. Alternatively, the transmission buffer 21 may read communication information to be transmitted and write received communication information from a memory built in the processor 28. Alternatively, the transmission buffer 21 may be connected to the same memory as the processor 28, and communication information may be exchanged via the same memory. Alternatively, processor 28 may also write the communication information to be transmitted and read the received communication information directly to a memory in transmission buffer 21.

As shown in fig. 2, the transmission arbitration mover 22 may be connected to a UART 29. The communication information to be transmitted buffered in the transmission buffer 21 may be shifted to the UART29 character by character, so that the communication information to be transmitted can be transmitted to the preset communication link through the UART 29. Optionally, after all the communication information to be sent in the communication information frame to be sent is moved, the sending arbitration mover 22 may perform an effective wait to ensure that the idle time of the data sending of the UART29 after the sending of the communication information frame is greater than or equal to the preset time interval. In this way, automatic control of the frame-to-frame interval can be automatically achieved using the frame boundary delimiting means 2000. In the channel, the delimitation of a plurality of communication information frames is automatically effected. Optionally, the communication information frame conforms to a latency-based communication frame protocol. The latency-based communication frame protocol may include a modbus protocol, a profibus protocol, and the like. Alternatively, the predetermined time interval may be 3.5 UART29 single byte transmission times. Alternatively, the preset time interval may be other time lengths. Alternatively, the preset time interval may be configurable.

Alternatively, the transmission buffer 21 may include at least one buffer block arranged sequentially. Alternatively, the transmission buffer 21 may include a reception buffer block for buffering received communication information and a transmission buffer block for buffering information to be transmitted. As shown in the example embodiment shown in fig. 2, the transmission buffer 21 may include: send buffer block 21T₁、21T₂、……、21T_n. Optionally, the buffer block 21T to be sent₁、21T₂、……、21T_nMay be arranged according to a preset order. Alternatively, the preset order may be 21T₁->21T₂->……->21T_n->21T₁… …, and circulating. Optionally, the buffer block 21T to be sent₁、21T₂、……、21T_nMay all be the same, e.g. mayAre each 64 bytes. Alternatively, the length of the communication information frame to be transmitted may be smaller than the capacity of one buffer block, or may be larger than the capacity of one buffer block. That is, one communication information frame to be sent may occupy only one buffer block, or may occupy two or more buffer blocks.

Alternatively, the cache block may have a descriptive structure. Alternatively, the description structure may be used to record at least one type of state information of the cache block. Such as a descriptive structure, may be used to store the tail tag. Alternatively, the tail tag may be a flag character or bit set to a particular address in the description structure. Alternatively, the tail tag may be other forms of flag information. Optionally, a tail tag may be used to mark whether the current cache block has cached the end of a communication frame. Alternatively, the trailer tag may be written by the processor 28 or by itself by the frame boundary defining means 2000.

For example, a communication information frame to be transmitted may be received from processor 28, and may be stored in at least one buffer block that is continuously set according to the length of the communication information frame to be transmitted. Assume that a frame of communication information to be transmitted occupies 3 buffer blocks. The communication information to be sent in the communication information frame to be sent can be sequentially buffered in the buffer block 21T₂、21T₃、21T₄(not shown). Can be in the cache block 21T₄The tail tag is stored in the description structure of (1), and the cache block 21T₂、21T₃The tail tag is not stored. Alternatively, the tag may be written to the designated cache block by processor 28, or may be written to itself by transmit buffer 21 in response to instructions from processor 28. Optionally, the number of bytes of the communication information to be sent, which is occupied by the current cache block, may also be recorded in the description structure, so as to determine whether the moving of the communication information in the current cache block is completed.

Alternatively, the transmission arbitration mover 22 may buffer the buffer in the buffer block 21T₂、21T₃、21T₄The communication information to be transmitted in (1) is moved to UART29 character by character. And may transmit the communication information to be transmitted character by character to the predetermined communication link via UART 29. Alternatively,the frequency at which the transmit arbitration mover 22 moves characters may match the rate at which characters are transmitted by the UART 29. Alternatively, the transmission arbitration mover 22 may detect whether the description structure in a buffer block has stored the tail tag when the communication information to be transmitted in the buffer block is moved. If not, determining the next mixed memory block according to the preset sequence, and moving the communication information to be sent in the next cache block. If so, an active wait may be made to ensure that the transmit dead time of UART29 is greater than or equal to a preset time interval.

Alternatively, the communication information frame to be transmitted may conform to a delay-based communication frame protocol. The latency-based communication frame protocol may include a modbus protocol, a profibus protocol, and the like. Alternatively, the preset time interval may be 3.5 transmission times of one byte information of the UART 29. Alternatively, the preset time interval may be other time lengths. Alternatively, the preset time interval may be configurable. Optionally, the tail tag in the current cache block may be erased at this time. If other communication information to be sent is cached in the next cache block, the other communication information to be sent in the next cache block can be moved continuously after effective waiting.

As shown in fig. 3, the frame boundary defining device 3000 is a frame boundary defining device for the receiving end. The frame boundary defining apparatus 3000 includes a receiving buffer 31 and a receiving arbitration shifter 32.

As shown in fig. 3, the receive buffer 31 may be coupled between the processor 38 and the receive arbitration mover 32. Optionally, the receive buffer 31 may be used to buffer the received communication information in the received communication information frame. And may send the received communication to processor 28.

Alternatively, the reception buffer 31 may include a memory. The memory may include at least one write interface coupled to the receive arbitrated mover 32. The reception arbitration shifter 32 can shift the received communication information to the reception buffer 31 using the write interface. The memory may also include at least one read interface coupled to the processor 38. The processor 38 may read the received communication information from the reception buffer 31 via the read interface. The receiving buffer 31 may optionally also comprise a dual port random access memory. The two read/write interfaces of the dual port random access memory are connected to the memory 38 and the receiving arbitration shifter 32, respectively. Alternatively, the reception buffer 31 may be a first-in first-out buffer (FIFO).

The connection between the receiving buffer 31 and the processor 38 is similar to the connection between the receiving buffer 21 and the processor 28 in fig. 3, and is not described herein again.

As shown in fig. 3, the receiving arbitration shifter 32 may be connected between the receiving buffer 31 and the UART 39. Alternatively, after the UART39 receives the communication information from the preset communication link, the reception arbitration mover 32 may obtain the received communication information from the UART39 and may move the received communication information to the reception buffer 31.

The receive arbitration mover 32 may monitor the status of the UART 39. This state may include whether UART39 is in a receive idle state. When the receiving dead time of the UART39 is greater than or equal to the preset time interval, it indicates that the receiving of one frame of communication information is completed at this time. At this time, the receiving arbitration shifter 32 may encapsulate the received communication into a received communication frame. In this way, serial communication can be utilized where the frame-to-frame boundaries are automatically determined by the time interval at which the information is received. The receive buffer 31 may send the received communication in the received communication frame to the processor 38. Processor 38 may also be notified to receive the received communication in the received communication frame.

Alternatively, the reception buffer 31 may include at least one buffer block arranged in sequence. E.g. receive buffer block 31R₁、31R₂、……、31R_n. Optionally, the receive buffer block 31R₁、31R₂、……、31R_nMay also be 64 bytes each. Alternatively, after the information is received by the UART39, the receiving arbitration mover 32 may obtain the received communication information from the UART39 and may buffer the received communication information to the receiving terminalIn the current buffer block in the buffer 31. For example, the current cache block may be cache block 31R₂. The receivable arbitration mover 32 may obtain the received communication information character by character from the UART39 and buffer the received communication information character by character into the buffer block 31R₂. When the cache block 31R₂When full, the cache blocks 31R may be ordered according to a specified order₃Designates the current buffer block and buffers the subsequent communication information in the buffer block 31R₃。

If the receiving dead time of the UART39 is detected to be greater than or equal to the predetermined time interval, it indicates that the end of a communication frame has been received. Alternatively, the frame structure of the received communication information frame may conform to a latency-based communication frame protocol. The latency-based communication frame protocol may include a modbus protocol, a profibus protocol, and the like. Optionally, the preset time interval is 3.5 single-byte transmission time of UART 39. Alternatively, the preset time interval may be other time lengths. Alternatively, the preset time interval may be configurable.

At this time, the block 31R can be sealed₃I.e. cache blocks 31R₃The communication information is no longer cached. Subsequent other received communications may be stored in the next cache block according to the specified order, cache block 31R₄(not shown). And may be in a cache block 31R₃The description structure of (2) stores tail tags. Alternatively, the tail tag may be written to the current cache block when a complete frame of communication information is received. Alternatively, the tail tag may be written by the receive arbitration mover 32. Alternatively, a signal may be sent to processor 38 upon receipt of a complete frame of communication information, prompting processor 38 to receive a received buffer including buffer block 31R₂And a cache block 31R₃Communication information in at least one cache block within. The processor 38 may read the description structure in the corresponding buffer block when reading the communication information from the receiving buffer 31. If the tail tag is read from the current cache block, the reading of the communication information can be finished after the current cache block is read, and corresponding frame analysis and processing work can be carried out.

As shown in FIG. 4, when transmitting the communication frame PACKET0, the receiving arbitration shifter 32 sequentially obtains the communication information C _0, C _1, … …, C _ n-1 in the received communication frame PACKET0 from the UART 39. And buffers the above communication information in the reception buffer 31. An IDLE period of length IDLE time occurs on the communication link after the character C _ n-1. When the receiving arbitration mover 32 detects an IDLE state for the length of time IDLE time that the UART39 exists. The aforementioned communication may be encapsulated as a communication frame.

As shown in fig. 5, in S410, a communication information frame may be obtained from a preset processor (not shown), wherein the communication information is a communication information frame to be sent. Alternatively, the communication information frame may be directly read from a preset address field of a RAM built in the preset processor. Alternatively, the processor can be connected with the preset processor through a dual-port RAM. And can directly obtain the communication information frame from the preset processor from the dual-port RAM. Alternatively, the communication information frame may be acquired by communicating with the predetermined processor through another serial or parallel interface. Alternatively, the preset processor may directly write the communication information in the communication information frame into the transmission buffer.

As shown in fig. 5, in S430, the communication information in the communication information frame may be moved to a predetermined asynchronous transceiver (not shown) character by character. And the asynchronous transceiver can transmit the communication information to a preset communication link character by character. Optionally, an effective wait may be performed after the communication information frame is transmitted, so as to ensure that the idle time of the data transmission of the asynchronous transceiver transmitter is greater than or equal to a preset time interval. Optionally, the communication information frame may conform to a modbus protocol standard. Alternatively, the predetermined time interval may be the time for 3.5 asynchronous transceivers to transmit a single byte of data.

As shown in fig. 5, S420 may also be included between S410 and S430. The aforementioned communication information frame may be buffered in S420. Alternatively, the communication information in the communication information frame may be sequentially buffered in at least one preset buffer block. Optionally, the size of each of the at least one cache block may be the same or different. Alternatively the size of each cache block may be 64 bytes. Optionally, at least one of the at least one cache blocks may be a first-in-first-out (FIFO) cache block.

Alternatively, each cache block may have a description structure. The description structure may be used to store tail tags. Where the tail tag may be preset flagging information at a preset address describing the structure. The flag information may be a flag bit, or may be flag information composed of one or more bytes. Optionally, the tail tag may be used to mark the end of the frame of communication information that the current cache block has stored. Alternatively, it may be determined whether the communication information frame has been transmitted by detecting whether the tail tag is stored in the current cache block.

That is, after the information in one cache block is sent, it may be detected whether the tail tag is already stored in the current cache block. If not, the information of the next cache block is moved and sent continuously. If yes, effective waiting is carried out to ensure that the idle time of data transmission of the UART is more than or equal to the preset time interval before the next communication information frame is transmitted.

As shown in fig. 6, communication information may be acquired character by character from the UART in S510. Optionally, the communication information is received communication information, and may be received from a predetermined communication link character by the UART.

As shown in fig. 6, the communication information may be transmitted to the preset processor in S530. The communication information can be directly written into a preset address field in a RAM built in the preset processor. The communication information may also be written to other RAM connected to the preset processor. The communication information may also be sent to the predetermined processor through other serial or parallel interfaces. Alternatively, the preset processor may also directly read the communication information from the receiving buffer, where the receiving buffer is disposed in the device applying the method.

As shown in fig. 6, a dead time of data reception of the UART may be detected in S540. If the dead time is greater than or equal to the preset time interval, the communication information can be packaged into a communication information frame. Alternatively, the communication information frame may conform to a latency-based communication frame protocol. The latency-based communication frame protocol may include a modbus protocol, a profibus protocol, and the like. The predetermined time interval may be 3.5 UARTs transmitting one byte of data. Alternatively, the preset time interval may be other time lengths. Alternatively, the preset time interval may be configurable.

As shown in fig. 6, S520 may also be included between S510 and S530. In S520, the aforementioned communication information may be buffered. Alternatively, the aforementioned communication information may be stored with at least one cache block arranged in order.

Alternatively, after the asynchronous transceiver transmitter receives the communication information from the predetermined communication link, the received communication information may be read from the asynchronous transceiver transmitter. And may buffer the received communication in the current buffer block. If the current cache block is full, the communication may continue to be cached to the next cache block. The receive dead time of the asynchronous transceiver transmitter may be detected. If the dead time is greater than the predetermined time interval. The communication may be encapsulated into a communication frame. Alternatively, the cache block may have a descriptive structure. Wherein the description structure may store a tail tag, wherein the tail tag may be used to indicate that the traffic stored by the current cache block includes the end of the traffic frame. Optionally, at encapsulation time, a tail tag may be written in the description structure in the current cache block. And the current cache block can be sealed, namely the current cache block does not accept the communication information any more. Subsequently received communication information may be buffered in the next buffer block.

As shown in fig. 7, the electronic apparatus 6000 may include a processor 61, a frame boundary defining unit 62, a frame boundary defining unit 63, a UART641 and a UART 642.

The frame boundary defining device 62 may be any one of the frame boundary defining devices for the transmitting end. As shown in the exemplary embodiment, frame boundary delineating means 62 may include a transmit buffer 621 and a transmit arbitration shifter 622. The frame boundary defining means 63 may be any one of the frame boundary defining means for the receiving end. Alternatively, the frame boundary defining device 63 may include a receiving buffer 631 and a receiving arbitration shifter 632. Alternatively, the electronic apparatus 6000 may include only one of the frame boundary defining means 62 and the frame boundary defining means 63.

The processor 61 may package data and/or instructions to be transmitted according to a preset communication protocol, so as to obtain an information frame to be transmitted. The processor 61 may also parse the received communication information frame according to a preset communication protocol to obtain the received data and/or instructions. Alternatively, the preset communication protocol may be a latency-based communication frame protocol. The latency-based communication frame protocol may include a modbus protocol, a profibus protocol, and the like.

The processor 61 may have a memory 611 and a memory 612 built therein for storing a communication information frame to be transmitted and a received communication information frame, respectively. The memory 611 and the memory 612 may be different address segments of the same memory. Alternatively, the memory 611 and the memory 612 may be other memories connected to the processor 61.

As shown in fig. 7, the transmission buffer 621 may be connected to the processor 61. The transmission buffer 621 may obtain and buffer a communication information frame to be transmitted from the processor 61. Alternatively, the transmission buffer 621 may be directly connected to the memory 611, and directly acquire the communication information frame to be transmitted from the memory 611. Alternatively, the transmission buffer 621 may be connected to the processor 61 through another serial or parallel communication interface, and acquire the to-be-transmitted communication information frame from the processor 61. Alternatively, processor 61 may write the frame of communication information to be transmitted directly into transmission buffer 621.

As shown in fig. 7, the transmission arbitration shifter 622 may be connected between the transmission buffer 621 and the UART 641. The transmission arbitration shifter 622 can be used to shift the communication information buffered in the frame of communication information to be transmitted in the transmission buffer 621 to the UART641 byte by byte. And optionally, the rate of sending the arbitration mover 622 communication may match the rate of sending the UART641 communication.

As shown in fig. 7, UART641 may be connected with a preset communication link. UART641 may send the communication received from transmit arbitration mover 622 to the communication link.

Alternatively, after the communication information in one communication information frame to be transmitted is completely carried, the transmission arbitration mover 622 may perform an effective wait to ensure that the transmission idle time of the UART641 is greater than or equal to the preset time interval. Alternatively, the time interval may be the time when 3.5 UARTs 641 transmit a single character. Alternatively, the preset time interval may be other time lengths. Alternatively, the preset time interval may be configurable.

Alternatively, the transmission buffer 621 may include a plurality of buffer blocks. The transmit buffer 621 may buffer frames of communication information to be transmitted in blocks. Alternatively, the cache block may have a description structure for storing the tail tag. Wherein the tail tag may indicate that the cache block includes an end of a communication protocol frame to be transmitted. Alternatively, the tail tag may be written into a designated buffer block of transmission buffer 621 by processor 61 after the frame of communication information to be transmitted is fed into transmission buffer 621. Or the sending buffer 621 writes the information frame after completely acquiring the communication information frame to be sent.

Alternatively, the sending arbitration mover 622 may detect whether the specified cache block has a tail tag stored therein after moving all the communication information in the cache block. If so, an effective wait is performed to ensure that the transmission idle time of the UART641 is greater than or equal to the preset time interval. Optionally, the length of the communication information in the cache block in which the communication information is stored may also be stored in the description structure. Alternatively, it can be determined by the length whether all communication information in the specified cache block has been moved.

As shown in fig. 7, UART642 may be coupled to a communication link and may receive communications from the communication link. UART641 and UART642 may be identical or similar. UART641 and UART642 may be two components of the same UART. The electronic device 6000 may also include only one of the

UARTs

641 and 642.

As shown in fig. 7, the receiving arbitration shifter 632 may be connected between the receiving buffer 631 and the UART 642. And may buffer communications received by UART642 to receive buffer 631. The receiving arbitration shifter 632 can detect the idle time of the receiving end of the UART 642. If the idle time is greater than or equal to the preset time interval, the communication information can be packaged into a received communication information frame. Receive arbitration mover 632 may be the same as or similar to transmit arbitration mover 622. Receive arbitration mover 632 and send arbitration mover 622 may be part of the same mover. Electronic device 6000 can also include only one of sending arbitration mover 622 and receiving arbitration mover 632.

As shown in fig. 7, the receive buffer 631 may be coupled between the receive arbitration shifter 632 and the processor 61 to buffer the communication in the received communication frame. And may send the transmitted communication information frame to the processor 61. The receive buffer 631 may be the same as or similar to the transmit buffer 621. The buffer 631 and the transmit buffer 621 may be two components of the same buffer. Alternatively, the electronic device 6000 may include only one of the reception buffer 631 and the transmission buffer 621.

The receive buffer 631 may also include a plurality of buffer blocks and buffer received communication in blocks. Optionally, each cache block may also have a description structure. Alternatively, the description structure may store the tail tag. Wherein the tail tag may be used to indicate that the cache block in which it is located contains the end of the received communication information frame. The tail tag may be written on the cache block when encapsulating the communication. The processor 61 can perform fast frame boundary delimitation based on the trailer tag in retrieving the communication information frame from the receiving buffer 631.

As shown in fig. 8, communication system 7000 may include electronic device 711, electronic device 712, and communication link 72. At least one of the electronic device 711 and the electronic device 712 may be any of the electronic devices described above.

The communication link 72 may include at least one of a simplex channel, a half-duplex channel, or a full-duplex channel. The communication link 72 may comprise a limited communication link or may comprise a wireless communication link. The communication link 72 may be a twisted pair channel, a fiber channel, or other communication channel.

As shown in fig. 9, a processor (CPU) in the electronic device 711 may package data and/or instructions to be transmitted as a frame of communication information to be transmitted according to a preset communication protocol. The frame of communication information may be buffered in at least one buffer block in a buffer (FIFO) in the electronic device 711. The transmit arbitration shifter (IDLE RB TX) of the electronic device 711 may shift the communication information in the communication information frame to the uart (uart TX) character by character. And may be transmitted by uart (uart tx) to the electronic device 712 via the communication link 72. The transmit arbitration shifter (IDLE RB TX) of the electronic device 711 may define the boundaries of the communication frame based on whether the tail tag is stored in a buffer block of the buffer (FIFO). I.e., to determine whether all of the traffic in the traffic frame has been completely transmitted. And can effectively wait after completely sending all the communication information in the communication information frame to ensure that the sending idle time of UART (UART TX) is more than or equal to the preset time interval.

The uart (uart rx) in the electronic device 712 may receive the communication information in the aforementioned communication information frame from the communication link 72. The receive arbitration shifter (IDLE RB RX) of the electronic device 712 may obtain the received communication information from the uart (uart RX) of the electronic device 712 and buffer the received communication information in at least one buffer block of a buffer (FIFO) of the electronic device 712. The receive arbitration shifter (IDLE RB RX) of the electronic device 712 may detect the receive dead time of the uart (uart RX) in the electronic device 712. If the receiving dead time is greater than or equal to the preset time interval, it can be determined that the communication information frame is completely received. The received communication may be encapsulated at this point as a received communication frame. And may store tail tags in the corresponding cache blocks. A processor (CPU) in the electronic device 712 may receive the communication in the received communication frame from a buffer (FIFO) in the electronic device 712. And may define the boundaries of the communication information frame by the trailer tag. And can perform protocol parsing after a received communication information frame is completely received, recover to obtain data and/or instructions sent by the electronic device 711, and perform related processing.

The application also provides a chip comprising any one of the frame boundary defining devices. Optionally, the chip may further include at least one of a processor and a UART, coupled to the apparatus.

An electronic device 200 according to this embodiment of the present application is described below with reference to fig. 10. The electronic device 200 shown in fig. 10 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 10, the electronic device 200 is embodied in the form of a general purpose computing device. The components of the electronic device 200 may include, but are not limited to: at least one processing unit 210, at least one memory unit 220, a bus 230 connecting different system components (including the memory unit 220 and the processing unit 210), a display unit 240, and the like.

Wherein the storage unit stores program code executable by the processing unit 210 to cause the processing unit 210 to perform the methods according to various exemplary embodiments of the present application described herein. For example, the processing unit 210 may execute a transmission method as shown in fig. 5, or a reception method as shown in fig. 6.

The memory unit 220 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM)2201 and/or a cache memory unit 2202, and may further include a read only memory unit (ROM) 2203.

The storage unit 220 may also include a program/utility 2204 having a set (at least one) of program modules 2205, such program modules 2205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 230 may be one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 200 may also communicate with one or more external devices 300 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 200, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 200 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 250. Also, the electronic device 200 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via the network adapter 260. The network adapter 260 may communicate with other modules of the electronic device 200 via the bus 230. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or computer program product. Accordingly, this application may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to as a "circuit," module "or" system. Furthermore, the present application may take the form of a computer program product embodied in any tangible expression medium having computer-usable program code embodied in the medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the description of the embodiments is only intended to facilitate the understanding of the methods and their core concepts of the present application. Meanwhile, a person skilled in the art should, according to the idea of the present application, change or modify the embodiments and applications of the present application based on the scope of the present application. In view of the above, the description should not be taken as limiting the application.

Claims

1. A UART-based frame boundary defining apparatus, comprising:

the sending buffer is used for receiving and buffering the communication information to be sent in the communication information frame to be sent from the preset processor;

and the transmission arbitration shifter is used for shifting the communication information to be transmitted to the UART from the transmission buffer, so that the communication information to be transmitted is transmitted to a preset communication link through the asynchronous receiving and transmitting transmitter, and effective waiting is carried out, so that the idle time of data transmission of the UART after the communication information to be transmitted is ensured to be more than or equal to a preset time interval.

2. The frame boundary defining device of claim 1,

the sending buffer also stores a tail tag of the communication information to be sent;

the processor writes the end of the communication information to be sent into the tail tag, or writes the end of the communication information to be sent into the frame boundary defining device;

after the sending arbitration mover moves the to-be-sent communication information of the sending buffer, the sending arbitration mover detects whether the frame boundary defining device stores the tail tag of the to-be-sent communication information, and if so, the sending arbitration mover effectively waits to ensure that the idle time of the UART data sending after the to-be-sent communication information is sent is greater than or equal to a preset time interval.

3. The frame boundary defining device according to claim 2,

the transmission buffer comprises at least one buffer block which is arranged in sequence;

the sending buffer sequentially buffers the communication information to be sent in the at least one buffer block;

after the communication information in the current cache block is moved, the sending arbitration moving device detects whether the current cache block stores a tail tag, and if so, the sending arbitration moving device effectively waits to ensure that the idle time of the UART data sending after the communication information to be sent is greater than or equal to a preset time interval.

4. The frame boundary defining device according to claim 3,

and the frame structure of the communication information frame to be sent conforms to a communication frame protocol based on time delay.

5. A UART-based frame boundary defining apparatus, comprising:

a receiving arbitration mover for obtaining received communication information from a UART, wherein the received communication information is received from the predetermined communication link by the UART, the receiving arbitration mover buffers the received communication information in a receiving buffer, and if the receiving dead time of the UART is greater than or equal to the predetermined time interval, the received communication information is encapsulated into a received communication information frame;

and the receiving buffer buffers the received communication information in the received communication information frame and sends the received communication information to the preset processor.

6. The frame boundary defining device of claim 5,

after the receiving arbitration mover buffers the received communication information in the receiving buffer, if the receiving dead time of the UART is greater than or equal to the preset time interval, writing a tail tag at the end of the received communication information.

7. The frame boundary defining device of claim 6,

the receiving buffer comprises at least one buffer block arranged in sequence;

the receiving buffer sequentially buffers the received communication information in the at least one buffer block;

and if the receiving arbitration mover detects that the idle time of the data receiving of the UART is greater than or equal to a preset time interval, the receiving arbitration mover seals the current cache block and writes a tail tag in the current cache block.

8. The frame boundary defining device of claim 5,

the frame structure of the received communication information frame conforms to a delay-based communication frame protocol.

9. A UART-based information sending method is characterized by comprising the following steps:

acquiring a communication information frame from a preset processor;

moving the communication information in the communication information frame to a UART one by one, and sending the communication information through the UART;

after all the communication information in the communication information frame is sent, effective waiting is carried out to ensure that the idle time of data sending of the UART is more than or equal to a preset time interval after the communication information frame is sent.

10. A UART-based information receiving method, comprising:

acquiring communication information from a UART character by character, wherein the communication information is received from a preset communication link by the UART character by character;

sending the communication information to a preset processor;

and detecting the idle time of data reception of the UART, and if the idle time is more than or equal to a preset time interval, packaging the communication information into a communication information frame.

11. An electronic device, comprising:

a processor;

UART；

frame boundary delimiting means according to one of the claims 1-4 and/or frame boundary delimiting means according to any of the claims 5-8, connected between the processor and the UART.

12. A chip, comprising:

frame boundary delimiting means according to one of the claims 1-4 and/or frame boundary delimiting means according to any of the claims 5-8.