CN112636736A

CN112636736A - Logic circuit

Info

Publication number: CN112636736A
Application number: CN201910955723.XA
Authority: CN
Inventors: 李承龙; 卢斌; 侯开华; 蔡燕飞
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-10-09
Filing date: 2019-10-09
Publication date: 2021-04-09

Abstract

A logic circuit, the logic circuit comprising: a first circuit and a second circuit connected to the first circuit; one end of the first circuit, which is connected with the second circuit, is an output end of the logic circuit; wherein the first circuit comprises: the circuit comprises a first logic branch and a second logic branch which is connected with the first logic branch in parallel; the first logic branch and the second logic branch are composed of N first MOS tubes, and N/2 first MOS tubes in the N first MOS tubes are connected with the first input signal output end, and N/2 first MOS tubes are connected with the second input signal output end; n is an even number and is not less than 6; and one end of the first logic branch circuit, which is connected with the second logic branch circuit, is connected with the second circuit. By applying the scheme, the current accumulation effect in the metal connecting wire where the output end of the logic circuit is positioned can be improved, and the problem of overlarge current migration caused by the current accumulation effect can be improved.

Description

Logic circuit

Technical Field

The embodiment of the invention relates to the field of chip design, in particular to a logic circuit.

Background

In the integrated circuit of the chip, a logic circuit with large driving is often required for respectively executing logical operations such as nor operation, nand operation, or operation and operation on a plurality of groups of input signals.

As chip design advances to more advanced processes, the size of the transistor becomes smaller and the line width becomes narrower, so that the average current flowing through the metal line and the connection hole causes a dc phenomenon called Electromigration (EM) at the 14nm process and below.

Failures due to electromigration can be catastrophic and these failures typically occur on the part of the user. At this point, the chip is already mounted on the substrate in a large system, which may cause the chip to be recalled once a problem occurs. With advanced process nodes, the problem of electromigration becomes more pronounced and has become a non-negligible part of the chip design.

The electromigration effect of the existing logic circuit is still more remarkable, and how to improve the electromigration effect of the logic circuit becomes a problem to be solved urgently.

Disclosure of Invention

The technical problem solved by the invention is to improve the electromigration effect of a logic circuit.

To solve the above technical problem, an embodiment of the present invention provides a logic circuit, where the logic circuit includes: a first circuit and a second circuit connected to the first circuit; one end of the first circuit, which is connected with the second circuit, is an output end of the logic circuit;

the first circuit and the second circuit are both connected with a first input signal output end and a second input signal output end and are suitable for executing logic operation on the first input signal and the second input signal;

wherein the first circuit comprises: the circuit comprises a first logic branch and a second logic branch which is connected with the first logic branch in parallel; the first logic branch and the second logic branch are composed of N first MOS tubes, and N/2 first MOS tubes in the N first MOS tubes are connected with the first input signal output end, and N/2 first MOS tubes are connected with the second input signal output end; n is an even number and is not less than 6;

one end of the first logic branch circuit, which is connected with the second logic branch circuit, is connected with the second circuit;

the second circuit is composed of N second MOS tubes which are connected in parallel, in the N second MOS tubes which are connected in parallel, N/2 second MOS tubes are connected with the first input signal output end, and N/2 second MOS tubes are connected with the second input signal output end.

Optionally, the first MOS transistor is a PMOS transistor, the second MOS transistor is an NMOS transistor, and the logic circuit is adapted to perform a nor operation on the first input signal and the second input signal.

Optionally, the first logic branch is formed by connecting a first PMOS transistor and a second PMOS transistor in series, where a gate of the first PMOS transistor is connected to the second input signal output terminal, a source of the first PMOS transistor is connected to the power supply voltage output terminal, and a drain of the first PMOS transistor is connected to a drain of the second PMOS transistor; and the grid electrode of the second PMOS tube is connected with the first input signal output end, and the source electrode of the second PMOS tube is connected with the drain electrode of the second MOS tube.

Optionally, the second logic branch includes: a first logical sub-branch, the first logical sub-branch comprising: a first logic module and a second logic module,

wherein the first logic module is connected in series with the second logic module; the first logic module is composed of more than two third PMOS tubes connected in parallel, and the second logic module is composed of more than two fourth PMOS tubes connected in parallel;

the grid electrode of the third PMOS tube is connected with the second input signal output end, the source electrode of the third PMOS tube is connected with the power supply voltage input end, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube; and the grid electrode of the fourth PMOS tube is connected with the first input signal output end, and the source electrode of the fourth PMOS tube is connected with the drain electrode of the second MOS tube.

Optionally, the number of the first logic sub-branches is one, and the number of the third PMOS transistors connected in parallel is more than three.

Optionally, the number of the first logic sub-branches is two or more, and the two or more first logic sub-branches are connected in parallel.

Optionally, the first MOS transistor is an NMOS transistor, the second MOS transistor is a PMOS transistor, and the logic circuit is adapted to perform a nand operation on the first input signal output terminal and the second input signal.

Optionally, the first logic branch is formed by connecting a first NMOS transistor and a second NMOS transistor in series, where a gate of the first NMOS transistor is connected to the first input signal output terminal, a drain of the first NMOS transistor is connected to the second MOS transistor, and a source of the first logic branch is connected to a drain of the second NMOS transistor; and the grid electrode of the second NMOS tube is connected with the second input signal output end, and the source electrode of the second NMOS tube is connected with the ground wire.

Optionally, the second logic branch includes: a second logical sub-branch, the second logical sub-branch comprising: a third logic module and a fourth logic module,

wherein the third logic module is connected in series with the fourth logic module; the third logic module is composed of more than two third NMOS tubes connected in parallel, and the fourth logic module is composed of more than two fourth NMOS tubes connected in parallel;

the grid electrode of the third NMOS tube is connected with the first input signal output end, the drain electrode of the third NMOS tube is connected with the second MOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube; and the grid electrode of the fourth NMOS tube is connected with the second input signal output end, and the source electrode of the fourth NMOS tube is connected with the ground wire.

Optionally, the number of the second logic sub-branches is one, and the number of the third NMOS transistors connected in parallel is more than three.

Optionally, the number of the second logic sub-branches is two or more, and the two or more second logic sub-branches are connected in parallel.

Optionally, the number of the first logic branches is two or more, and the two or more first logic branches are connected in parallel.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

by adopting the scheme, the first circuit comprises the first logic branch circuit and the second logic branch circuit, and the first logic branch circuit and the second logic branch circuit are connected in parallel, so that the first circuit can adopt two rows of metal wires for connection among MOS (metal oxide semiconductor) tubes in a layout during implementation, and active areas of power supply voltage output ends in the layout are distributed in a scattered manner, thereby improving a current accumulation effect in a metal wire where the logic circuit output ends are positioned, and further improving the problem of overlarge current migration caused by the current accumulation effect.

Drawings

FIG. 1 is a schematic circuit diagram of a logic circuit driven to 1;

FIG. 2 is a schematic diagram of a circuit configuration of a logic circuit driven as 2;

FIG. 3 is a schematic circuit diagram of another logic circuit driven as 2;

FIG. 4 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a first logic branch according to an embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of a second logic branch according to an embodiment of the present invention;

FIG. 7 is a schematic circuit diagram of another first logic branch according to an embodiment of the present invention;

FIG. 8 is a schematic circuit diagram of another second logic branch according to an embodiment of the present invention;

FIG. 9 is a circuit diagram of a first circuit of a 14-bit NAND gate logic circuit according to an embodiment of the present invention;

FIG. 10 is a schematic circuit diagram of a first circuit of the NOR gate 14 in the embodiment of the present invention;

FIG. 11 is a layout diagram of the first circuit shown in FIG. 10;

FIG. 12 is a diagram illustrating the results of an electromigration analysis performed on the layout shown in FIG. 11;

fig. 13 is a layout diagram of a first circuit in a nor gate logic circuit of the prior art, where the drive is 14;

fig. 14 is a diagram illustrating the result of the electromigration analysis performed on the layout shown in fig. 13.

Detailed Description

The research of the inventor finds that the current migration of the existing large driving logic circuit is too large.

Further research finds that the reason for the overlarge current migration of the large driving logic circuit is as follows: the current value flowing through the output end of the logic circuit is larger, so that the current accumulation effect is caused, and the electromigration effect is caused by the current accumulation effect.

The following describes in detail the reason why the output end of the logic circuit causes the current accumulation effect with reference to a specific logic circuit structure:

fig. 1 shows a nor gate logic circuit driven to 1, that is, a logic circuit performing nor operation on only one set of input signals.

Referring to fig. 1, the logic circuit 10 includes two PMOS transistors connected in series and two NMOS transistors connected in parallel. The grid electrodes of the two PMOS tubes and the grid electrodes of the two NMOS tubes are suitable for being connected with an input signal A2 or an input signal A1. The output terminal of the logic circuit 10 is ZN. VDD is a power voltage output end, and GND is a ground wire.

Fig. 2 shows a nor gate logic circuit driven as 2, i.e. a logic circuit which performs nor operation only on two sets of input signals.

Referring to fig. 2, in the logic circuit 20, all PMOS transistors connected to the input signal a2 are connected in parallel, all NMOS transistors connected to the input signal a1 are connected in parallel, and then two parallel circuits are connected in series. Meanwhile, the NMOS transistors for complementation are all connected in parallel. The output of the logic circuit 20 is ZN. VDD is a power voltage output end, and GND is a ground wire.

When the PMOS part of the logic circuit 20 in fig. 2 is implemented, the power voltage output terminal VDD is distributed on one side of the active region in the layout, and two rows of metal wires are used to connect the MOS transistors. The first row of metal connecting lines are used for connecting the drain electrode of the PMOS tube with the input signal of A2 and the source electrode of the PMOS tube with the input signal of A1, and the second row of metal connecting lines are used for connecting the drain electrode of the PMOS tube with the input signal of A1 and the NMOS tube part. The current flowing through the second row of metal lines, i.e. the metal line on which the output ZN of the logic circuit 20 is located.

Because the power voltage output ends VDD are uniformly distributed on one side of the active region in the layout, the value of the current flowing through the metal line where the output end ZN of the logic circuit 20 is located is large, and the current accumulation effect is easily caused.

Fig. 3 is another nor gate logic circuit driven as 2.

Referring to fig. 3, the logic circuit 30 includes a plurality of logic branches connected in parallel, and each logic branch includes two PMOS transistors connected in series. Meanwhile, the NMOS transistors for complementation are all connected in parallel. The output of the logic circuit 30 is ZN. VDD is a power voltage output end, and GND is a ground wire.

In the implementation of the PMOS part of the logic circuit 30 in fig. 3, the power voltage output terminals VDD are distributed in the layout and distributed in the active region, but only one row of metal connecting wires is used to connect the MOS transistors, so that the current flowing through the metal wire where the output terminal ZN of the logic circuit 30 is located is still large, and the current accumulation effect is still easily caused.

It can be seen that, in both the logic circuit with the circuit structure shown in fig. 2 and the logic circuit with the circuit structure shown in fig. 3, the output terminal is easy to cause the circuit accumulation effect, and finally the logic circuit exists

Although two rows of metal connecting wires are adopted, the power supply voltage output ends VDD are uniformly distributed on one side of an active area in the layout, and the problem of overlarge current migration is finally caused. The electromigration effect causes a voltage drop of the electronic devices in the chip, which in turn causes a reduction in the speed of the device in which the chip is located. In addition, electromigration effects can cause short or open circuits in the logic circuit, which can lead to permanent failure of the logic circuit.

In view of the above problems, an embodiment of the present invention provides a logic circuit, in which a first circuit includes not only a first logic branch but also a second logic branch, and the first logic branch and the second logic branch are connected in parallel, so that in a layout of the first circuit during implementation, not only two rows of metal lines may be used for connection between MOS transistors, but also power voltage output ends may be distributed in an active region in the layout, and thus a current accumulation effect may be improved in a metal connection line where the logic circuit output end is located, and a problem of excessive current migration due to the current accumulation effect may also be improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 4, an embodiment of the present invention provides a logic circuit 40, where the logic circuit 40 may include: a first circuit 41, and a second circuit 42 connected to the first circuit 41. One end of the first circuit 41 connected to the second circuit 42 is an output end ZN of the logic circuit 40. The first circuit 41 and the second circuit 42 are both connected to the first input signal output terminal and the second input signal output terminal, and are adapted to perform a logic operation on the first input signal and the second input signal.

Specifically, the first circuit 41 may include: a first logic branch 411, and a second logic branch 412 connected in parallel with the first logic branch. The first logic branch 411 and the second logic branch 412 are composed of N first MOS transistors, of which N/2 first MOS transistors are connected to the first input signal output terminal and N/2 first MOS transistors are connected to the second input signal output terminal; n is an even number and is more than or equal to 6.

The end of the first logic branch connected to the second logic branch, i.e. the output ZN of the logic circuit 40, is connected to the second circuit 42.

The second circuit 42 is composed of N second MOS transistors connected in parallel, wherein, among the N second MOS transistors connected in parallel, N/2 second MOS transistors are connected to the first input signal output terminal, and N/2 second MOS transistors are connected to the second input signal output terminal.

In an implementation, the logic circuit 40 can perform various logic operations on the first input signal and the second input signal, such as nor operation, nand operation, or operation and operation, and the like, and can be configured as required.

In an embodiment of the invention, the first MOS transistor is a PMOS transistor, the second MOS transistor is an NMOS transistor, and the logic circuit 40 is adapted to perform a nor operation on the first input signal output terminal and the second input signal.

At this time, when the PMOS transistors in the first circuit 41 are turned on, the NMOS transistors in the second circuit 42 are turned off, so that the output signal from the output terminal ZN is maintained at a logic high level.

When the PMOS transistors in the first circuit 41 are turned off, the NMOS transistors in the second circuit 42 are turned on, so that the output signal from the output terminal ZN is maintained at a logic low level.

When the PMOS transistors connected to the first input signal in the first circuit 41 are turned on and the PMOS transistors connected to the second input signal are turned off, the NMOS transistors connected to the second input signal in the second circuit 42 are turned on and the PMOS transistors connected to the first input signal are turned off, so that the output signal at the output terminal ZN is maintained at a logic low level.

When the PMOS transistors connected to the second input signal in the first circuit 41 are turned on and the PMOS transistors connected to the first input signal are turned off, the NMOS transistors connected to the first input signal in the second circuit 42 are turned on and the PMOS transistors connected to the second input signal are turned off, so that the output signal of the output terminal ZN is maintained at a logic ground level.

When the logic circuit 40 is a logic circuit performing a nor operation on the first input signal and the second input signal, in an embodiment of the invention, as shown in fig. 5, the first logic branch 411 may be composed of two first PMOS transistor P1 and a second PMOS transistor P2 connected in series. The grid electrode of the first PMOS pipe P1 is connected with the second input signal output end and is suitable for being connected with a second input signal A2. The source electrode of the first PMOS pipe P1 is connected with a power supply voltage output end VDD, and the drain electrode of the first PMOS pipe P1 is connected with the drain electrode of the second PMOS pipe P2. The grid electrode of the second PMOS pipe P2 is connected with the first input signal output end and is suitable for being connected with a first input signal A1. The source of the second PMOS transistor P2 is used as the output terminal ZN of the logic circuit 40, and is connected to the drain of the second MOS transistor.

In a specific implementation, the number of the first logic branches 411 may be only one, or may be multiple. When the number of the first logic branches 411 is two or more, the two or more first logic branches 411 are connected in parallel.

In an embodiment of the present invention, as shown in fig. 6, the second logic branch 412 may include: a first logical sub-branch 51. The first logical sub-branch 51 may comprise: a first logic module 511 and a second logic module 512.

Wherein the first logic module 511 is connected in series with the second logic module 512. The first logic module 511 is composed of more than two third PMOS transistors P3 connected in parallel, and the second logic module 512 is composed of more than two fourth PMOS transistors P4 connected in parallel. The gate of the third PMOS transistor P3 is connected to the second input signal output terminal, and is adapted to receive a second input signal a 2. The source electrode of the third PMOS tube P3 is connected with a power supply voltage input end VDD, and the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the fourth PMOS tube P4. The gate of the fourth PMOS transistor P4 is connected to the first input signal output terminal, and is adapted to receive the first input signal a 1. The source of the fourth PMOS transistor P4 is used as the output terminal ZN of the logic circuit 40, and is connected to the drain of the second MOS transistor.

In an embodiment of the present invention, the number of the first logic sub-branches 51 may be only one, and at this time, all the third PMOS transistors P3 accessing the second input signal except the first logic branch 411 belong to the first logic module 511 and are connected in parallel, and all the third PMOS transistors P4 accessing the first input signal belong to the second logic module 512 and are connected in parallel.

In the implementation of the layout, if the MOS transistors in the second logic branch 412 are placed first, and then the MOS transistors in the first logic branch 411 are placed, the number of the third PMOS transistors P3 connected in parallel should be more than three, so that the power voltage output terminals VDD can be distributed on the active regions of the layout. If the MOS transistors in the first logic branch 411 are placed first, and then the MOS transistors in the second logic branch 412 are placed, the number of the third PMOS transistors P3 connected in parallel is more than two, so that the power voltage output terminals VDD are distributed in the active regions of the layout.

In another embodiment of the present invention, the number of the first logic sub-branches 51 is two or more, and the two or more first logic sub-branches 51 are connected in parallel. At this time, the number of the PMOS devices included in the first logic module 511 in different first logic sub-branches 51 may be the same or different. Similarly, the number of PMOS devices included in the second logic module 512 in different first logic sub-branches 51 may be the same or different. However, as long as the number of the first logic sub-branches 51 is more than two, no matter how the first logic branch 411 and the second logic branch 412 are sequentially placed in the layout, the power voltage output terminals VDD can be distributed on each active region of the layout, and are connected to each PMOS transistor through two rows of metal connecting wires.

In another embodiment of the present invention, with reference to fig. 4, the first MOS transistor may be an NMOS transistor, the second MOS transistor is a PMOS transistor, and the logic circuit 40 is adapted to perform a nand operation on the first input signal output terminal and the second input signal.

At this time, when the PMOS transistors in the second circuit 42 are turned on, the NMOS transistors in the first circuit 41 are turned off, so that the output signal from the output terminal ZN is maintained at a logic high level.

When the PMOS transistors in the second circuit 42 are turned off, the NMOS transistors in the first circuit 41 are turned on, so that the output signal from the output terminal ZN is maintained at a logic low level.

When the PMOS transistors connected to the first input signal in the second circuit 42 are turned on and the PMOS transistors connected to the second input signal are turned off, the NMOS transistors connected to the second input signal in the first circuit 41 are turned on and the NMOS transistors connected to the first input signal are turned off, so that the output signal at the output terminal ZN is maintained at a logic low level.

When the PMOS transistors connected to the second input signal in the second circuit 42 are turned on and the PMOS transistors connected to the first input signal are turned off, the NMOS transistors connected to the first input signal in the first circuit 41 are turned on and the NMOS transistors connected to the second input signal are turned off, so that the output signal of the output terminal ZN is maintained at a logic ground level.

In an embodiment of the invention, referring to fig. 7, the first logic branch 411 is composed of two serially connected first and second NMOS transistors N1 and N2, wherein a gate of the first NMOS transistor N1 is connected to the first input signal output terminal and is adapted to receive a first input signal a 1. The drain of the first NMOS transistor N1 is connected to the second MOS transistor, that is, to the output terminal ZN of the logic circuit 40. The source electrode of the first NMOS transistor N1 is connected with the drain electrode of the second NMOS transistor N2. The grid electrode of the second NMOS tube N2 is connected with the second input signal output end and is suitable for being connected with a second input signal A2. The source of the second NMOS transistor N2 is connected to ground GND.

In an embodiment of the present invention, referring to fig. 8, the second logic branch 412 includes: a second logical sub-branch 52, the second logical sub-branch 52 may include: a third logic module 521 and a fourth logic module 522.

Wherein the third logic module 521 is connected in series with the fourth logic module 522; the third logic module 521 is composed of more than two third NMOS transistors N3 connected in parallel, and the fourth logic module 522 is composed of more than two fourth NMOS transistors N4 connected in parallel.

The grid electrode of the third NMOS tube N3 is connected with the first input signal output end and is suitable for being connected with a first input signal A1. The drain electrode of the third NMOS transistor N3 is connected with the second MOS transistor, and the source electrode is connected with the drain electrode of the fourth NMOS transistor N4. The grid electrode of the fourth NMOS transistor N4 is connected to the second input signal output end, and is adapted to receive a second input signal. The source of the fourth NMOS transistor N4 is connected to ground GND.

In an embodiment of the present invention, the number of the second logic sub-branches 52 is one. At this time, all the third NMOS transistors N3 connected to the first input signal except the first logic branch 411 belong to the third logic module 521 and are connected in parallel, and all the PMOS transistors N4 connected to the second input signal a2 belong to the fourth logic module 522 and are connected in parallel.

In another embodiment of the present invention, the number of the second logic sub-branches 52 is two or more, and the two or more second logic sub-branches 52 are connected in parallel. At this time, in different second logic sub-branches 52, the number of the NMOS devices included in the third logic module 521 may be the same or different. Similarly, the number of the NMOS devices included in the fourth logic block 522 in different second logic sub-branches 52 may be the same or different. However, as long as the number of the second logic sub-branches 52 is more than two, no matter how the first logic branch 411 and the second logic branch 412 are sequentially placed in the layout, the power voltage output terminals VDD can be distributed on each active region of the layout, and are connected to each NMOS transistor through two rows of metal connecting wires.

In the embodiment of the present invention, no matter the logic circuit is a nand gate logic circuit or a nor gate logic circuit, the number of the first logic branches 411 is two or more, and the two or more first logic branches 411 are connected in parallel.

Fig. 9 is a schematic circuit diagram of a first circuit 141 of a nand gate 14 according to an embodiment of the present invention. The nand gate 14 is driven by 14 nand gate logic circuits, which respectively perform nand operations on 14 sets of the first input signal a1 and the second input signal a 2. As shown in fig. 9, the first circuit 141 includes 1 first logic branch 411 and 12 second logic branches 412.

Fig. 10 is a schematic circuit diagram of a first circuit 71 of a nor gate 14 logic circuit according to an embodiment of the present invention. The nor gate 14 is driven by 14 nor gate logic circuits, which respectively perform nor operation on 14 sets of the first input signal a1 and the second input signal a 2. As shown in fig. 10, the first circuit 41 includes 1 first logic branch 411 and 12 second logic branches 412.

Fig. 11 is a layout diagram of the first circuit 71 in fig. 9. As shown in fig. 11, taking the gate access signal of each PMOS transistor as the identifier of each PMOS transistor, the gate placing sequence of each PMOS transistor in the first circuit 71 sequentially is: A2A1A1A2A2A1A1A 1A2A2A1A 2A2A2A2A1A1A 2A2A1A1A 2.

The metal connecting line 81 connects the drains of the second PMOS transistors connected to the first input signal a1 in each first logic branch 411 through a connecting hole disposed in the active region. The metal line 82 connects the source of the fourth PMOS transistor connected to the first input signal a1 in the second logic branch 412 to the drain of the third PMOS transistor connected to the second input signal a2 through a connection hole disposed on the active region. Thus, two rows of metal connecting wires are required on the layout corresponding to the first circuit 71, and the power voltage output ends are distributed on the active area in a dispersed manner because the first logic branch 411 and the second logic branch 412 are connected in parallel.

The electromigration analysis is performed on the layout shown in fig. 11, and the obtained simulation result is shown in fig. 12. As can be seen from fig. 9, the maximum circuit density peak on the metal wiring 81 is about 2.39.

Fig. 13 is a layout diagram of a nor gate logic circuit driven by 14 according to the connection manner between the PMOS transistors shown in fig. 3. As shown in fig. 13, although two rows of metal wires (as shown by metal wires 91 and 92) are also used in the layout to connect the PMOS transistors, the power voltage output terminals are only distributed on the active region on one side of the metal wire 91, and the current flowing through the metal wire 91 is the current flowing through the logic circuit output terminal ZN.

The electromigration analysis was performed on the layout shown in fig. 13, and the obtained simulation result is shown in fig. 14. As can be seen from fig. 14, the peak of the maximum circuit density on the metal line 91 is about 5.56, which is about one time higher than the peak of the maximum circuit density on the metal line 81. Therefore, the scheme of the invention obviously improves the electromigration problem of the logic circuit.

As can be seen from the above, with the logic circuit in the embodiment of the present invention, the first circuit includes not only the first logic branch but also the second logic branch, and the first logic branch and the second logic branch are connected in parallel, so that in a layout of the first circuit during implementation, not only two rows of metal lines may be used for connection between the MOS transistors, but also active regions of the power voltage output terminals in the layout are distributed in a scattered manner, so as to improve a current accumulation effect in the metal connection line where the output terminal of the logic circuit is located, and further improve a problem of excessive current migration due to the current accumulation effect.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A logic circuit, comprising: a first circuit and a second circuit connected to the first circuit; one end of the first circuit, which is connected with the second circuit, is an output end of the logic circuit;

2. The logic circuit of claim 1, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor, and wherein the logic circuit is adapted to perform a nor operation on the first input signal and the second input signal.

3. The logic circuit according to claim 2, wherein the first logic branch is composed of two first PMOS transistors and a second PMOS transistor connected in series, wherein the gate of the first PMOS transistor is connected to the second input signal output terminal, the source of the first PMOS transistor is connected to the power supply voltage output terminal, and the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor; and the grid electrode of the second PMOS tube is connected with the first input signal output end, and the source electrode of the second PMOS tube is connected with the drain electrode of the second MOS tube.

4. The logic circuit of claim 3, wherein the second logic branch comprises: a first logical sub-branch, the first logical sub-branch comprising: a first logic module and a second logic module,

5. The logic circuit of claim 4, wherein the number of the first logic sub-branches is one, and the number of the third PMOS tubes connected in parallel is three or more.

6. The logic circuit according to claim 4, wherein the number of the first logic sub-branches is two or more, and the two or more first logic sub-branches are connected in parallel.

7. The logic circuit of claim 1, wherein the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor, the logic circuit being adapted to perform a nand operation on the first input signal output terminal and the second input signal.

8. The logic circuit according to claim 7, wherein the first logic branch is composed of two serially connected first and second NMOS transistors, wherein the gate of the first NMOS transistor is connected to the first input signal output terminal, the drain of the first NMOS transistor is connected to the second MOS transistor, and the source of the first NMOS transistor is connected to the drain of the second NMOS transistor; and the grid electrode of the second NMOS tube is connected with the second input signal output end, and the source electrode of the second NMOS tube is connected with the ground wire.

9. The logic circuit of claim 8, wherein the second logic branch comprises: a second logical sub-branch, the second logical sub-branch comprising: a third logic module and a fourth logic module,

10. The logic circuit according to claim 9, wherein the number of the second logic sub-branches is one, and the number of the third NMOS transistors connected in parallel is three or more.

11. The logic circuit according to claim 4, wherein the number of the second logic sub-branches is two or more, and the two or more second logic sub-branches are connected in parallel.

12. The logic circuit according to claim 1, wherein the number of the first logic branches is two or more, and the two or more first logic branches are connected in parallel.