CN112635560A - Fin-shaped transistor structure and manufacturing method thereof - Google Patents

Fin-shaped transistor structure and manufacturing method thereof Download PDF

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Publication number
CN112635560A
CN112635560A CN201910948784.3A CN201910948784A CN112635560A CN 112635560 A CN112635560 A CN 112635560A CN 201910948784 A CN201910948784 A CN 201910948784A CN 112635560 A CN112635560 A CN 112635560A
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fin
fin structures
substrate
structures
layer
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CN201910948784.3A
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CN112635560B (en
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黄圣尧
陈昱瑞
朱中良
蔡仁杰
林毓翔
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201910948784.3A priority Critical patent/CN112635560B/en
Priority to US16/699,474 priority patent/US11417685B2/en
Priority to EP20173434.0A priority patent/EP3806139A1/en
Publication of CN112635560A publication Critical patent/CN112635560A/en
Priority to US17/844,067 priority patent/US11721702B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a fin-shaped transistor structure and a manufacturing method thereof. The fin transistor structure includes a first substrate. An insulating layer is disposed on the first substrate. A plurality of fin structures is disposed on the insulating layer. A support dielectric layer secures the plurality of fin structures at a location of a waist of the plurality of fin structures. A gate structure layer disposed on the support dielectric layer and covering a portion of the plurality of fin structures.

Description

Fin-shaped transistor structure and manufacturing method thereof
Technical Field
The present invention relates to semiconductor manufacturing technology, and more particularly, to Fin Field Effect Transistor (FinFET) structures and methods for fabricating the same.
Background
A large number of transistor elements are inevitably involved in an integrated circuit. The size and operating efficiency of the transistors determine the size and performance of the resulting integrated circuit. Therefore, the design of the transistor structure should be developed.
In view of the reduction of the size of transistors, various new transistor structures have been proposed to replace the earlier use of larger area transistors, wherein finfet structures, or simply finfets, have also been proposed to at least effectively reduce the size of transistors.
With the design of greatly reducing the device size, the distance between adjacent linear fin structures and fin structures is very small for the general structure of fin transistors. Isolation between fins is based on semiconductor fabrication techniques, however, typically achieved by shallow trench isolation structures formed of dielectric materials such as oxide. As the distance between the fin structures decreases, the parasitic capacitance therebetween increases. An increase in parasitic capacitance (RC) increases the RC effect, thereby reducing the operating speed.
One way to reduce the parasitic capacitance between fins is to fabricate shallow trench isolation structures with dielectric materials having a lower dielectric constant. For the dielectric material of common oxide, its dielectric constant is still relatively high, and is not suitable for use.
As is generally known, the dielectric constant of air is close to 1, almost the material with the lowest dielectric constant. The so-called air dielectric material is represented as a free space. In the free space, air in a natural state exists in nature under a non-vacuum state, and the free space is also an air isolation structure.
Therefore, how to form the air space to reduce the dielectric constant of the isolation structure and further reduce the parasitic capacitance effect is one of many research projects.
Disclosure of Invention
The present invention is directed to fin transistor structures and methods of fabricating the same that incorporate air space into isolation structures used to isolate fin structures as part of the isolation, thereby at least reducing the overall dielectric constant and, therefore, reducing parasitic capacitance.
In one embodiment, the present invention provides a fin transistor structure. The fin transistor structure includes a first substrate. An insulating layer is disposed on the first substrate. A plurality of fin structures is disposed on the insulating layer. A support dielectric layer secures the plurality of fin structures at a location of a waist of the plurality of fin structures. A gate structure layer disposed on the support dielectric layer and covering a portion of the plurality of fin structures.
In an embodiment, for the fin transistor structure, the plurality of fin structures are part of a second substrate disposed on the insulating layer and over the first substrate.
In one embodiment, for the fin transistor structure, an end portion of the support dielectric layer is fixed by a bulk portion of the second substrate.
In an embodiment, for the fin transistor structure, the insulating layer also covers an end surface of the bulk portion for attachment to the first substrate.
In an embodiment, for the fin transistor structure, the insulating layer also covers sidewalls of the plurality of fin structures at a location below the waist.
In an embodiment, for the fin transistor structure, each of the plurality of fin structures has a first end surface on the insulating layer and a second end surface opposite the first end surface covered by the gate structure layer, wherein the second end surface is wider than the first end surface for a cross-sectional direction of the plurality of fin structures.
In an embodiment, for the fin transistor structure, a distance from the first substrate to the waist location of the plurality of fin structures is half or more than half of a height of the plurality of fin structures.
In one embodiment, for the fin transistor structure, the insulating layer is an oxide layer, a nitride layer, or a dielectric layer.
In an embodiment, for the fin-shaped transistor structure, a plurality of initial fin structures are arranged on an initial substrate, and fin intervals between the plurality of initial fin structures are preset, wherein the plurality of initial fin structures are regarded as the plurality of fin structures, and a distance between two adjacent fin structures is equal to the fin intervals.
In an embodiment, for the fin-shaped transistor structure, a plurality of initial fin structures are arranged on an initial substrate, a fin interval between the plurality of initial fin structures is preset, wherein a part of the plurality of initial fin structures is taken as the plurality of fin structures, and a distance between two adjacent fin structures is at least twice of the fin interval.
In one embodiment, the present invention also provides a method of fabricating a fin transistor device. The method comprises the steps of providing a first substrate, forming a plurality of fin structures on the substrate, filling a dielectric layer between the bases of the fin structures, and arranging an insulating layer at least on first end faces of the fin structures. Disposing the first end faces of the plurality of fin structures on a second substrate. And grinding the first substrate and the dielectric layer to expose the fin structures to form a plurality of individual units. And removing a part of the dielectric layer, wherein the rest part of the dielectric layer is a supporting dielectric layer, and the fin structures are fixed at the waist positions of the fin structures. A gate structure layer is formed on the support dielectric layer and covers a portion of the plurality of fin structures.
In an embodiment, for the method of fabricating a fin transistor device, the plurality of fin structures are part of a first substrate, and the first substrate and the insulating layer are disposed over the base substrate.
In an embodiment, with the method of manufacturing a fin transistor element, an end portion of the support dielectric layer is fixed by a bulk portion of the first substrate.
In an embodiment, with the method of manufacturing a fin transistor element, the insulating layer also covers an end surface of the block portion to be attached to the first substrate.
In an embodiment, for the method of manufacturing a fin transistor element, the insulating layer also covers sidewalls of the plurality of fin structures at a position lower than the waist portion.
In an embodiment, for the method of manufacturing a fin transistor element, each of the plurality of fin structures has a first end face on the insulating layer and a second end face opposite to the first end face and covered by the gate structure layer, wherein the second end face is wider than the first end face with respect to a cross-sectional direction of the plurality of fin structures.
In an embodiment, with the method of manufacturing a fin transistor element, a distance from the first substrate to the waist position of the plurality of fin structures is half or more than half of a height of the plurality of fin structures.
In one embodiment, for the method of fabricating a fin transistor device, the insulating layer is an oxide layer, a nitride layer, or a dielectric layer.
In an embodiment, for the method of fabricating a fin transistor device, the first substrate is formed with a plurality of initial fin structures, and the plurality of initial fin structures are the plurality of fin structures.
In one embodiment, in the method for manufacturing the fin transistor device, a plurality of initial fin structures are formed on the first substrate, and a portion of the plurality of initial fin structures, which is used as dummy fins, is removed to form the plurality of fin structures.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A to 1F are schematic cross-sectional views illustrating a manufacturing process for manufacturing a fin-shaped transistor device according to an embodiment of the present invention;
fig. 2A to 2I are schematic cross-sectional views illustrating a manufacturing process for manufacturing a fin-shaped transistor device according to an embodiment of the present invention;
figure 3 is a cross-sectional view of a fin structure in the fabrication of a fin transistor, in accordance with one embodiment of the present invention;
figure 4 is a cross-sectional view of a fin structure in the fabrication of a fin transistor, in accordance with one embodiment of the present invention;
FIG. 5 is a schematic diagram of a lateral cross-sectional structure of a fin transistor according to an embodiment of the present invention; and
fig. 6 is a schematic diagram of a vertical cross-sectional structure of a fin transistor according to an embodiment of the invention.
Description of the reference numerals
100. 200 base plate
102. 202 oxide layer
104. 204 nitride layer
106. 206 groove
108. 208 fin structure
110. 110A dielectric layer
110B supporting dielectric layer
112. 214 substrate
114. 218 air isolation structure
208A fin structure
208B dummy fin structure
210. 210A, 210B dielectric layer
210C supporting dielectric layer
212 insulating layer
230 fin spacing
240 gate structure layer
242 interlayer dielectric layer
244 spacer
Detailed Description
The invention relates to a fin-shaped transistor structure and a manufacturing method thereof. The present invention proposes that the space of air can be effectively incorporated into the isolation structure for isolating the fin structure as a part of the isolation. Since the dielectric constant of the air space is close to 1, the overall effective dielectric constant can be reduced, and thus at least the parasitic capacitance can be reduced.
The present invention is described below by way of some embodiments, but the present invention is not limited to the embodiments described, and the embodiments allow possible appropriate combinations between them.
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process for manufacturing a fin-shaped transistor device according to an embodiment of the present invention. Referring to fig. 1A, a substrate 100 is provided for forming a Fin structure 108(Fin structure) in a predetermined area. The substrate 100 is, for example, a silicon substrate. Before the fin structure 108 is formed, the oxide layer 102 and the nitride layer 104 are used as a protection for etching the substrate 100. In one embodiment, the substrate 100 and the oxide layer 102 and nitride layer 104 are defined by photolithography and etching processes on the substrate 100 to remove some of the substrate 100 and form the trenches 106. The substrate 100 between the trenches 106 constitutes an initial fin structure 108. The width of the trench 106 between the fins 108 is a predetermined size. In one embodiment, no portion of the initial fin structures 108 is removed. Therefore, the isolation distance between two adjacent fin structures 108 is the width of the trench 106.
Referring to fig. 1B, a dielectric layer 110 is deposited over the substrate 100. The dielectric layer 110 is, for example, an oxide layer. In one embodiment, the dielectric layer 110 covers the nitride layer 104 and fills only the lower portion of the trench 106, not completely filling the trench 106.
Referring to fig. 1C, in one embodiment, a portion of the dielectric layer 110 is removed using an etching process. The remaining portion of dielectric layer 110 becomes dielectric layer 110A, which remains filled into the lower portion of trench 106. At the same time, the nitride layer 104 is also removed, but the oxide layer 102 may remain, for example, and may subsequently serve as an insulating layer. Oxide layer 102 remains covering the end surfaces of fin structures 108. Here, the width of the end surface of the covering fin structure 108 at the top is greater than the width of the covering fin structure 108 at the bottom.
Referring to fig. 1D, a substrate 100 is bonded to another substrate 112 through an oxide layer 102. Here, the other substrate 112 may be a silicon substrate or may not be a silicon substrate. Oxide layer 102 serves as an insulating layer between substrate 100 and substrate 112. Oxide layer 102 also covers the bulk portion of substrate 100, between substrate 100 and substrate 112.
It is noted that the partially filled trench 106 is covered by the substrate 112, thereby forming an air space, i.e. forming an air isolation structure 114. The air space is an air isolation structure 114 in terms of dielectric material, and has a dielectric constant close to 1.
Referring to FIG. 1E, taking the state of FIG. 1D as an example, in one embodiment, the substrate 100 and the substrate 112 may be inverted such that the back surface of the substrate 100 is above the overall structure. Next, a polishing process is performed on the back surface of the substrate 100 to remove a portion of the substrate 100 and expose the dielectric layer 110A and the other end surface of the fin structure 108.
Referring to fig. 1F, an etching process is performed on the dielectric layer 110A to remove a portion of the dielectric layer 110A. The remaining portion of dielectric layer 110A forms support dielectric layer 110B. The end of the support dielectric layer 110B is fixedly attached to the substrate 100. The support dielectric layer 110B also fixes the plurality of fin structures 108 at the same time and is located at the waist portion of the fin structures 108. The support dielectric layer 110B is located relative to the waist location of the fin structure 108, and the distance from the substrate 112 to the waist location is, for example, half or more than half of the height of the fin structure 108. The thickness of the fin structure 108 is not limited to a particular thickness as long as the fin structure 108 can be supported.
In such a semi-finished structure, air isolation structures 114 are substantially formed as isolation between fin structures 108. The dielectric constant of the air isolation structure 114 is close to 1, which can effectively reduce the overall dielectric constant and thus reduce the parasitic capacitance.
In one embodiment, the air isolation structure 114 may be formed in different manners, and is not limited to the embodiment of fig. 1A to 1F. Fig. 2A to 2I are schematic cross-sectional views illustrating a manufacturing process for manufacturing a fin-shaped transistor device according to an embodiment of the present invention.
Referring to fig. 2A, at the beginning of the fabrication process, similar to fig. 1A, a fin structure 208 is first formed on a substrate 200. The bulk portion of the substrate 200 and the end surfaces of the fin structures 208 are also covered with an oxide layer 202 and a nitride layer 204. Between fins 208 is a trench 206.
Referring to fig. 2B, in one embodiment, the dielectric layer 210 fills all of the trench 206. Referring to fig. 2C, a polishing process is performed to remove the upper portion of the dielectric layer 210 and expose the nitride layer 204. The remaining portion of the dielectric layer 210 is a dielectric layer 210A, which substantially fills the entire trench 206.
Referring to fig. 2D, the nitride layer 204 is removed to expose the oxide layer 202. Referring to fig. 2E, an etch back process is performed to remove the oxide, such that the upper portion of the dielectric layer 210A is removed to obtain a dielectric layer 210B. At the same time, the oxide layer 202 is also removed to expose the substrate 200.
Referring to fig. 2F, an insulating layer 212, such as an oxide layer, is formed on the exposed surface of the substrate 200, such as by a thermal oxidation process. The insulating layer 212 is bonded to the dielectric layer 210B. Insulating layer 212 covers the exposed surfaces of fin structure 208 shown in fig. 2E, including portions of the sidewalls and end surfaces.
Referring to fig. 2G, another substrate 214 covers the substrate 200, i.e., on the insulating layer 212. As such, air isolation structures 218 are formed between the fin structures 208 as isolation structures between the fin structures 208.
Referring to FIG. 2H, the substrate 214 is inverted relative to the substrate 200 such that the substrate 200 is above the structure to facilitate the polishing process. The grinding process grinds away a portion of the substrate 200 to expose the dielectric layer 210B.
Referring to fig. 2I, an oxide etch process is performed to remove a portion of the dielectric layer 210B to achieve the effect of reducing the thickness. The remaining dielectric layer 210B structurally becomes a supporting dielectric layer 210C. The insulating layer 212 of the present embodiment simultaneously covers the sidewalls of the fin structures 208 corresponding to the air isolation structures 218.
In yet another embodiment, fig. 3 is a schematic cross-sectional view of a fin structure in a fin transistor fabrication process according to an embodiment of the present invention. Referring to fig. 3, a portion of the fin structures 108, 208 may be dummy, as compared to the original fin structures 108, 208 of fig. 1A or 2A. Taking the initial fin structure 208 of fig. 2A as an example, the dummy fin structure 208B is removed to obtain the actual desired fin structure 208A. With this structure, the spacing between fin structures 208A is greater than the fin spacing between fin structures 208 as set. As a general matter, the spacing between fin structures 208A is twice the fin spacing or greater.
Figure 4 is a cross-sectional view of a fin structure in the fabrication of a fin transistor, in accordance with one embodiment of the present invention. Referring to fig. 4, continuing with the structure of fig. 3, a structure similar to that of fig. 2F may be obtained, for example, according to the process flow of fig. 2B through 2I, but with the fin spacing 230 between the fin structures 208A being increased by removing the dummy fin structure 208B.
After the fin structures 108, 208 and the air isolation structures 114, 218 are completed, the subsequent process flow may be continued. Fig. 5 is a schematic diagram of a lateral cross-sectional structure of a fin transistor according to an embodiment of the invention.
Referring to FIG. 5, in one embodiment, taking the structure of FIG. 1F as an example, an inter-layer dielectric 242 is formed overlying the substrate 100. A gate structure layer 240 is then formed in the interlayer dielectric layer 242, covering the exposed portions of the fin structures 108. Here, the gate structure layer 240 generally includes a gate layer and a gate insulating layer, and the detailed process of the fabrication thereof is not described in detail herein, and the present invention is not limited to how to fabricate the gate structure layer 240.
It is noted herein that the fabrication flow according to the present invention is structurally related. The width of the end surface of the fin structure 108 covered by the gate structure layer 240 is greater than the width of the end surface covered by the oxide layer 102. The increased width may also increase the contact area between the gate structure layer 240 and the fin structure 108, increasing the channel area under the gate structure layer 240.
Fig. 6 is a schematic diagram of a vertical cross-sectional structure of a fin transistor according to an embodiment of the invention. Referring to fig. 6, a semiconductor structure for an overall circuit generally includes a plurality of segments of a fin line extending in a longitudinal direction of the fin line. The cross-sectional direction of fig. 6 is perpendicular to the cross-sectional direction of fig. 5, and two linear fin structures 108 are illustrated. There are multiple gate structure layers 240 across fin structure 108. The gate structure layer 240 is also a gate line structure crossing the fin structure 108. Spacers 244 may also be formed on the sidewalls of the gate structure layer 240. The space between the spacers 244 is filled with an inter-layer dielectric. Air isolation structures 114 are also present between adjacent fin structures 108.
The present invention proposes to use the air isolation structure 114 as an isolation between the fin structures 108, which can at least effectively reduce the effective dielectric constant, thereby reducing the parasitic capacitance and improving the efficiency of the fin transistor.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (20)

1. A fin transistor structure, comprising:
a first substrate;
an insulating layer disposed on the first substrate;
a plurality of fin structures disposed on the insulating layer;
a support dielectric layer securing the plurality of fin structures at a waist location of the plurality of fin structures; and
a gate structure layer disposed on the support dielectric layer and covering a portion of the plurality of fin structures.
2. The fin-shaped transistor structure of claim 1, wherein the plurality of fin-shaped structures are part of a second substrate disposed on the insulating layer and over the first substrate.
3. The fin transistor structure of claim 2, wherein an end portion of the support dielectric layer is secured by a bulk portion of the second substrate.
4. The fin-shaped transistor structure of claim 3, wherein the insulating layer also covers an end surface of the block portion for attachment to the first substrate.
5. The fin-shaped transistor structure of claim 1, wherein the insulating layer also covers sidewalls of the plurality of fin-shaped structures at a location below the waist.
6. The fin-shaped transistor structure of claim 1, wherein each of the plurality of fin structures has a first end surface on the insulating layer and a second end surface opposite the first end surface covered by the gate structure layer, wherein the second end surface is wider than the first end surface for a cross-sectional direction of the plurality of fin structures.
7. The fin-shaped transistor structure of claim 1, wherein a distance from the first substrate to the waist location of the plurality of fin structures is one half or more than one half of a height of the plurality of fin structures.
8. The fin-shaped transistor structure of claim 1, wherein the insulating layer is an oxide layer, a nitride layer, or a dielectric layer.
9. The fin-shaped transistor structure of claim 1, wherein a plurality of initial fin structures are disposed on an initial substrate, a fin spacing between the plurality of initial fin structures is predetermined, wherein the plurality of initial fin structures are regarded as the plurality of fin structures, and a distance between two adjacent fin structures is equal to the fin spacing.
10. The fin-shaped transistor structure of claim 1, wherein a plurality of initial fin structures are disposed on an initial substrate, a fin spacing between the plurality of initial fin structures is predetermined, wherein a portion of the plurality of initial fin structures is regarded as the plurality of fin structures, and a distance between two adjacent ones of the plurality of fin structures is at least twice the fin spacing.
11. A method of fabricating a fin transistor device, comprising:
providing a first substrate, wherein a plurality of fin structures are formed on the substrate, a dielectric layer is filled between the bases of the fin structures, and an insulating layer is arranged at least on first end faces of the fin structures;
disposing the first end surfaces of the plurality of fin structures on a second substrate;
grinding the first substrate and the dielectric layer to expose the fin structures into a plurality of individual units;
removing a portion of the dielectric layer, wherein a remaining portion of the dielectric layer is a supporting dielectric layer, and fixing the plurality of fin structures at waist positions of the plurality of fin structures; and
a gate structure layer is formed on the support dielectric layer and covers a portion of the plurality of fin structures.
12. The method of claim 11, wherein the plurality of fin structures are part of a first substrate, and the first substrate and the insulating layer are disposed over the base substrate.
13. The method of manufacturing a fin transistor element of claim 12, wherein an end portion of the support dielectric layer is fixed by a bulk portion of the first substrate.
14. The method of manufacturing a fin transistor element according to claim 13, wherein the insulating layer also covers an end surface of the block portion to be attached to the first substrate.
15. The method of fabricating a fin transistor element of claim 11, wherein the insulating layer also covers sidewalls of the plurality of fin structures at a location below the waist.
16. The method of claim 11, wherein each of the plurality of fin structures has a first end surface on the insulating layer and a second end surface opposite the first end surface covered by the gate structure layer, wherein the second end surface is wider than the first end surface for a cross-sectional direction of the plurality of fin structures.
17. The method of manufacturing a fin transistor element of claim 11, wherein a distance from the first substrate to the waist location of the plurality of fin structures is one half or more than one half of a height of the plurality of fin structures.
18. The method of claim 11, wherein the insulating layer is an oxide layer, a nitride layer, or a dielectric layer.
19. The method of claim 11, wherein the first substrate is formed by first forming a plurality of initial fin structures, and wherein the plurality of initial fin structures are the plurality of fin structures.
20. The method of claim 11, wherein the first substrate is formed by first forming a plurality of initial fin structures, and removing portions of the plurality of initial fin structures that are to be dummy fins to form the plurality of fin structures.
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