CN112635344B - Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern - Google Patents

Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern Download PDF

Info

Publication number
CN112635344B
CN112635344B CN202011387239.0A CN202011387239A CN112635344B CN 112635344 B CN112635344 B CN 112635344B CN 202011387239 A CN202011387239 A CN 202011387239A CN 112635344 B CN112635344 B CN 112635344B
Authority
CN
China
Prior art keywords
contact hole
pull
detected
tube
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011387239.0A
Other languages
Chinese (zh)
Other versions
CN112635344A (en
Inventor
宁威
李磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hua Hong Semiconductor Wuxi Co Ltd
Original Assignee
Hua Hong Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hua Hong Semiconductor Wuxi Co Ltd filed Critical Hua Hong Semiconductor Wuxi Co Ltd
Priority to CN202011387239.0A priority Critical patent/CN112635344B/en
Publication of CN112635344A publication Critical patent/CN112635344A/en
Application granted granted Critical
Publication of CN112635344B publication Critical patent/CN112635344B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Abstract

The invention discloses a method for detecting alignment deviation of a contact hole and a polycrystalline silicon pattern, which comprises the following steps: the method comprises the following steps of firstly, utilizing the characteristic that the registration deviation of a contact hole and a polycrystalline silicon pattern of a detected product and the image brightness of the contact hole formed by scanning of an electron beam detection device have correlation, and pre-forming a fitting curve of the registration deviation of the contact hole and the polycrystalline silicon pattern corresponding to the detected product and the image brightness of the corresponding contact hole. And step two, scanning the detected product by adopting electron beam detection equipment and obtaining the image brightness of the contact hole which is aligned with the polysilicon pattern on the detected product. And step three, combining the fitting curve to convert the image brightness of the contact hole corresponding to the detected product into the overlay deviation of the contact hole and the polysilicon pattern of the detected product. The invention can quickly and comprehensively detect the overlay deviation of the contact hole and the polysilicon pattern on line.

Description

Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for detecting overlay deviation (overlay) of a contact hole (CT) and a polysilicon pattern.
Background
With the development of advanced integrated circuit processes, especially under a 55nm technology node platform, random fluctuation of overlay deviation (overlay) between contact holes and Active Area (AA) or polysilicon (poly) may seriously affect product yield. The existing method is difficult to realize online (Inline) detection of alignment deviation between a contact hole and a polysilicon pattern such as a polysilicon gate, for example, Inline overlap detection is difficult to measure and determine whether leakage risk exists in a local area of a product such as an electrostatic random access memory (SRAM).
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for detecting the overlay deviation of a contact hole and a polysilicon pattern, which can quickly and comprehensively detect the overlay deviation of the contact hole and the polysilicon pattern on line.
In order to solve the technical problem, the method for detecting the overlay deviation of the contact hole and the polysilicon pattern comprises the following steps:
the method comprises the steps of firstly, utilizing the characteristics that the registration deviation of a contact hole and a polycrystalline silicon pattern of a detected product and the image brightness of the contact hole formed by scanning of an electron Beam Inspection (E-Beam Inspection, EBI) device have correlation, and pre-forming a fitting curve of the registration deviation of the contact hole and the polycrystalline silicon pattern corresponding to the detected product and the image brightness of the corresponding contact hole.
Step two, providing the detected product, wherein the polycrystalline silicon pattern and the contact hole are formed on the detected product; and scanning the detected product by adopting the electron beam detection equipment and obtaining the image brightness of the contact hole which is aligned with the polysilicon pattern on the detected product.
And thirdly, combining the fitting curve to convert the image brightness of the contact hole corresponding to the detected product into the overlay deviation of the contact hole and the polysilicon pattern of the detected product.
In a further improvement, in the first step, the sub-step of forming the fitted curve includes:
and 11, forming the contact hole and the polysilicon pattern which are the same as the detected product on a test wafer, and performing pull bias on the space between the contact hole and the polysilicon pattern on the test wafer to form a series of overlay deviations of the contact hole and the polysilicon pattern with different sizes.
And step 12, scanning the first scanning picture formed by the test piece by adopting the electron beam detection equipment.
And step 13, determining the image brightness of each contact hole on the first scanning picture.
And 14, fitting the image brightness of each contact hole and the corresponding overlay deviation to form the fitting curve.
In a further improvement, in step 11, the test sheet is arranged according to a reverse direction gradually increasing or decreasing according to the size of the overlay deviation and according to a direction in which the overlay deviation gradually changes, so that the positions of the contact holes correspond to the size of the overlay deviation in the direction in which the overlay deviation gradually changes one to one.
In step 13, the position of the image brightness of each contact hole in the first scanned picture corresponds to the position of the corresponding contact hole on the test piece, and the overlay deviation corresponding to the image brightness of the contact hole is determined according to the position of the image brightness of the contact hole in the first scanned picture.
In a further refinement, the inspected product comprises a plurality.
In a further improvement, when the types of the detected products are the same, the detected products share the same fitting curve, and the fitting curve is formed only before the first detected product is detected.
In a further improvement, when the types of the detected products comprise a plurality of types, the steps are carried out before the first detected product of each type is detected to form the fitted curve corresponding to the type of the detected product; and in the third step, the tested products of various types adopt the fitting curve corresponding to the types of the tested products.
In a further improvement, in step 11, only the contact holes and the polysilicon patterns which are the same as the tested products of one type are formed on each test piece; the fitted curves corresponding to the detected products of various types are respectively obtained on different test sheets.
In a further improvement, in step 11, only the contact holes and the polysilicon patterns which are the same as the detected products of more than two types are formed on each test piece, and the contact holes and the polysilicon patterns which are the same as the detected products of different types are formed on different areas of the test piece; and forming the fitting curves corresponding to more than two types of the detected products on the same test sheet.
In a further improvement, the inspected product comprises an SRAM product or a logic product.
In a further improvement, the memory cell of the SRAM product comprises a 6T-type memory cell, and the 6T-type memory cell includes: the device comprises a first selection pipe, a second selection pipe, a first pull-up pipe, a second pull-up pipe, a first pull-down pipe and a second pull-down pipe.
On the layout structure of the 6T-shaped storage unit, the first pull-down tube is connected with the polysilicon gate of the first pull-up tube, and the second pull-down tube is connected with the polysilicon gate of the second pull-up tube.
The first selection tube and the first pull-down tube share a first active region, the first pull-up tube is located in a second active region, the second pull-up tube PPU2 is located in a third active region, and the second pull-down tube and the second selection tube share a fourth active region.
The drain region of the first selection tube and the drain region of the first pull-down tube are shared, and a first contact hole is formed at the top of the drain region of the first pull-down tube; the first contact hole is positioned between the polysilicon gate of the first pull-down tube and the polysilicon gate of the first selection tube.
The drain region of the second selection tube and the drain region of the second pull-down tube are shared, and a second contact hole is formed at the top of the drain region of the second pull-down tube; the second contact hole is positioned between the polysilicon gate of the second pull-down tube and the polysilicon gate of the second selection tube.
The layout of the 6T-shaped storage unit is of a central symmetry structure, the first pull-down tube and the second pull-down tube are symmetrical, the first pull-up tube and the second pull-up tube are symmetrical, the first selection tube and the second selection tube are symmetrical, and the first contact hole and the second contact hole are symmetrical.
The contact hole of the detected product is the first contact hole or the second contact hole; the polysilicon graph of the detected product is the polysilicon gate of the first pull-down tube and the polysilicon gate of the first selection tube or the polysilicon gate of the second pull-down tube and the polysilicon gate of the second selection tube.
The further improvement is that when the technical node of the SRAM product is reduced, the size of the layout structure of the 6T-type storage unit is reduced in equal proportion, and the sizes of the corresponding first contact hole and the second contact hole are also reduced in equal proportion.
The further improvement is that the technical node of the SRAM product is below 55 nm.
In a further improvement, in the second step, the detected product is formed on a product wafer, and the electron beam detection device performs full scanning on the product wafer of the detected product to form a second scanning picture.
And then selecting the image brightness of the corresponding contact hole in the second scanning picture.
In a further improvement, the image brightness of the contact hole formed by scanning of the electron beam detection device is expressed by gray level.
In a further refinement, the electron beam inspection apparatus scans an image formed by collecting Secondary Electrons (SE) and backscattered electrons (BSE) of the electron beam.
The invention realizes the detection of the overlay deviation of the contact hole and the polysilicon pattern based on the scanning of the electron beam detection equipment by utilizing the characteristic that the overlay deviation of the contact hole and the polysilicon pattern of a detected product and the image brightness of the contact hole formed by the scanning of the electron beam detection equipment have correlation, and can quickly and comprehensively detect the overlay deviation of the contact hole and the polysilicon pattern on line.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a method for detecting overlay deviation of a contact hole and a polysilicon pattern according to an embodiment of the present invention;
FIG. 2 is a fitted curve formed during a step in a method according to an embodiment of the present invention;
FIG. 3 is a layout of a 6T-type memory cell when the product to be tested is an SRAM product in the method of the embodiment of the present invention;
FIG. 4 is a partial area diagram of a second scanned picture formed in step two for the SRAM product corresponding to FIG. 3 in a method according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating alignment deviations obtained from the brightness of the contact hole image in combination with a fitted curve in step three of the method according to the embodiment of the present invention.
Detailed Description
FIG. 1 is a flow chart of a method for detecting overlay deviation of a contact hole and a polysilicon pattern according to an embodiment of the present invention; the method for detecting the overlay deviation of the contact hole and the polysilicon pattern comprises the following steps:
the method comprises the steps of firstly, utilizing the characteristic that the registration deviation of a contact hole and a polycrystalline silicon pattern of a detected product and the image brightness of the contact hole formed by scanning of an electron beam detection device have correlation, and pre-forming a fitting curve 101 of the registration deviation of the contact hole and the polycrystalline silicon pattern corresponding to the detected product and the image brightness of the corresponding contact hole.
In the method of the embodiment of the invention, the image brightness of the contact hole formed by scanning of the electron beam detection equipment is represented by gray value.
The electron beam inspection apparatus scans and forms an image by collecting secondary electrons and backscattered electrons of an electron beam.
In the method of the embodiment of the present invention, the sub-steps of forming the fitting curve 101 include:
and 11, forming the contact hole and the polysilicon pattern which are the same as the detected product on a test wafer, and performing pull bias on the space between the contact hole and the polysilicon pattern on the test wafer to form a series of overlay deviations of the contact hole and the polysilicon pattern with different sizes.
The test strip is usually a test wafer. Preferably, the test sheet is arranged according to the size of the overlay deviation and according to a direction of gradual increase or gradual decrease of the overlay deviation, and the contact holes are arranged according to a direction of gradual change of the overlay deviation, so that the positions of the contact holes correspond to the size of the overlay deviation in the direction of gradual change of the overlay deviation in a one-to-one manner.
And step 12, scanning the first scanning picture formed by the test piece by adopting the electron beam detection equipment.
And step 13, determining the image brightness of each contact hole on the first scanning picture.
The position of the image brightness of each contact hole in the first scanning picture corresponds to the position of the corresponding contact hole on the test piece, and the alignment deviation corresponding to the image brightness of the contact hole is determined according to the position of the image brightness of the contact hole in the first scanning picture.
And 14, fitting the image brightness of each contact hole and the corresponding overlay deviation to form the fitting curve 101.
FIG. 2 shows a fitting curve 101 formed in a step of a method according to an embodiment of the present invention; the abscissa of the fitting curve 101 is the overlay deviation, and the ordinate is the gray value corresponding to the image brightness of each contact hole.
In the embodiment of the invention, the detected product comprises a plurality of products.
The types of the detected products are the same, the detected products share the same fitting curve 101, and the fitting curve 101 only needs to be formed before the first detected product is detected. In step 11, only the contact hole and the polysilicon pattern which are the same as the detected product of one type are formed on each test sheet; the fitted curves 101 corresponding to the detected products of various types are obtained on different test sheets respectively.
In other embodiments can also be: the types of the detected products comprise a plurality of types, and steps are carried out before the first detected product of the various types is detected to form the fitting curve 101 corresponding to the types of the detected products; in the third subsequent step, the fitted curve 101 corresponding to the type of the detected product is adopted by each type of the detected product. In step 11, only the contact hole and the polysilicon pattern which are the same as the detected product of one type are formed on each test sheet; the fitted curves 101 corresponding to the detected products of various types are obtained on different test sheets respectively. Or, in step 11, only the contact holes and the polysilicon patterns which are the same as the two or more types of the detected products are formed on each test piece, and the contact holes and the polysilicon patterns which are the same as the different types of the detected products are formed on different areas of the test piece; and forming the fitting curves 101 corresponding to more than two types of detected products on the same test piece.
Step two, providing the detected product, wherein the polycrystalline silicon pattern and the contact hole are formed on the detected product; and scanning the detected product by adopting the electron beam detection equipment and obtaining the image brightness of the contact hole which is aligned with the polysilicon pattern on the detected product.
In the method of the embodiment of the invention, the detected product is formed on a product wafer, and the electron beam detection equipment performs full scanning on the product wafer of the detected product to form a second scanning picture.
And then selecting the image brightness of the corresponding contact hole in the second scanning picture.
The detected product comprises an SRAM product. In other embodiments can also be: the detected product comprises a logic product. The method of the embodiment of the present invention is further described below by taking an SRAM product as an example:
as shown in fig. 3, it is a layout of a 6T type memory cell when the detected product is an SRAM product in the method of the embodiment of the present invention; the storage unit of the SRAM product comprises a 6T type storage unit, and the 6T type storage unit comprises: a first selection pipe NPG1, a second selection pipe NPG2, a first pull-up pipe PPU1, a second pull-up pipe PPU2, a first pull-down pipe NPD1, and a second pull-down pipe NPD 2.
On the layout structure of the 6T-type storage unit, the first pull-down tube NPD1 is connected with the polysilicon gate 2 of the first pull-up tube PPU1, and the second pull-down tube NPD2 is connected with the polysilicon gate 2 of the second pull-up tube PPU 2.
The first selection pipe NPG1 and the first pull-down pipe NPD1 share a first active region 1a, the first pull-up pipe PPU1 is located in a second active region 1b, the second pull-up pipe PPU2 is located in a third active region 1c, and the second pull-down pipe NPD2 and the second selection pipe NPG2 share a fourth active region 1 d.
A drain region of the first selection pipe NPG1 and a drain region of the first pull-down pipe NPD1 are shared, and a first contact hole 31 is formed at the top of the drain region of the first pull-down pipe NPD 1; the first contact hole 31 is located between the polysilicon gate 2 of the first pull-down tube NPD1 and the polysilicon gate 2 of the first select tube NPG 1.
A drain region of the second selection pipe NPG2 and a drain region of the second pull-down pipe NPD2 are shared, and a second contact hole is formed at the top of the drain region of the second pull-down pipe NPD 2; the second contact hole is located between the polysilicon gate 2 of the second pull-down tube NPD2 and the polysilicon gate 2 of the second select tube NPG 2.
The layout of the 6T-shaped storage unit is of a central symmetry structure, the first pull-down tube NPD1 is symmetrical to the second pull-down tube NPD2, the first pull-up tube PPU1 is symmetrical to the second pull-up tube PPU2, the first selection tube NPG1 is symmetrical to the second selection tube NPG2, and the first contact hole 31 is symmetrical to the second contact hole. In fig. 3, contact holes 32, 33, 34, 35 and 36 are also shown, the other contact holes being symmetrical and not individually labeled. Wherein the contact hole 32 is located at the top of the drain region of the first pull-down transistor NPG1 and is connected to a Bit Line (BL), the contact hole 33 is located at the top of the drain region of the first pull-down transistor NPD1 and is connected to ground (Vss), the contact hole 34 is located at the top of the polysilicon gate 2 of the first pull-down transistor NPG1 and is connected to a Word Line (WL), the contact hole 35 is located at the top of the source region of the first pull-up transistor PPU1 and is connected to a power supply voltage (Vdd), and the contact hole 36 is simultaneously connected to the source region of the first pull-up transistor PPU1 and the polysilicon gate 2 shared by the second pull-down transistor NPD2 and the second pull-up transistor PPU 2.
In fig. 3, the contact hole of the inspected product is the first contact hole 31 or the second contact hole; the polysilicon patterns of the detected product are the polysilicon gate 2 of the first pull-down tube NPD1 and the polysilicon gate 2 of the first selection tube NPG1 or the polysilicon gate 2 of the second pull-down tube NPD2 and the polysilicon gate 2 of the second selection tube NPG 2.
When the technical node of the SRAM product is reduced, the size of the layout structure of the 6T-type storage unit is reduced in equal proportion, and the sizes of the corresponding first contact hole 31 and the second contact hole are also reduced in equal proportion. The dimensions of the contact holes of the SRAM product are different for different technology nodes, so that the fitting curve 101 needs to be formed separately for different types of products. The technical node of the SRAM product is less than 55 nm.
Fig. 4 is a partial area diagram 301 of a second scanned picture formed in step two for the SRAM product corresponding to fig. 3 in the method according to the embodiment of the present invention; the second scan pattern forms an image of each contact hole in fig. 3, because the layout structure of the 6T-type memory cell is symmetrical, the layout structures of a plurality of the 6T-type memory cells are periodically arranged on the product wafer, and the image corresponding to the word line WL in fig. 4 is an image corresponding to the contact hole including the contact hole 34 in the dashed line frame 201a or 201b in fig. 3.
The corresponding images at the two PMOS in fig. 4 are the corresponding images of the contact holes in the dashed box 203a or 203b in fig. 3, including the corresponding images of the contact holes 35 and 36; in fig. 4, VShare corresponds to the contact hole 36 or the symmetrical contact hole of the contact hole 36, and Vdd corresponds to the contact hole 35 or the symmetrical contact hole of the contact hole 35.
The corresponding image at 1 NMOS in fig. 4 is the corresponding image of the contact hole in the dashed box 202a or 202b in fig. 3, including the contact holes 31, 32, and 33. The image corresponding to Vss in fig. 4 is an image corresponding to contact hole 33 or a symmetric contact hole of contact hole 33, and the image corresponding to BL is an image corresponding to contact hole 32 or a symmetric contact hole of contact hole 32; the image corresponding to Vnn is the image corresponding to the first contact hole 31 or the symmetrical second contact hole. It can be seen that the two images corresponding to Vnn have different brightness, so that the overlay deviation is different between the two images, and therefore, the contact hole with larger overlay deviation is easily selected according to the image brightness. When the Vnn corresponding contact hole, i.e., the first contact hole 31 or the second contact hole, is closer to the corresponding polysilicon pattern, i.e., the polysilicon gate 2, electrons may flow into the Vnn corresponding contact hole from the polysilicon gate 2 during scanning by the electron beam inspection apparatus, so that the image brightness of the Vnn corresponding contact hole may be brighter, and thus, the image brightness of the Vnn corresponding contact hole and the pitch between the Vnn corresponding contact hole and the corresponding polysilicon pattern have a correlation.
And thirdly, combining the fitting curve 101 to convert the image brightness of the contact hole corresponding to the detected product into the overlay deviation of the contact hole and the polysilicon pattern of the detected product.
FIG. 5 is a schematic diagram of the alignment deviation obtained by combining the image brightness of the contact hole and the fitting curve in step three of the method according to the embodiment of the present invention; in fig. 5, three pictures corresponding to the picture 301 in fig. 4 are shown in the second scanned picture, which are marked with marks 301a, 301b and 301c, respectively, and it can be seen that the gray-scale values of the image brightness of the contact holes obtained in the pictures 301a, 301b and 301c are respectively: -35, -37 and-39, the corresponding overlay deviation being readily available in the fitted curve plot.
According to the embodiment of the invention, the characteristics that the alignment deviation of the contact hole and the polycrystalline silicon pattern of the detected product and the image brightness of the contact hole formed by scanning of the electron beam detection equipment have correlation are utilized, the alignment deviation of the contact hole and the polycrystalline silicon pattern is detected based on the scanning of the electron beam detection equipment, and the alignment deviation of the contact hole and the polycrystalline silicon pattern can be rapidly and comprehensively detected on line.
The present invention has been described in detail with reference to the specific examples, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A method for detecting overlay deviation of a contact hole and a polysilicon pattern is characterized by comprising the following steps:
the method comprises the following steps that firstly, a fitting curve of the registration deviation of a contact hole and a polycrystalline silicon pattern corresponding to a detected product and the image brightness of the corresponding contact hole is formed in advance by utilizing the characteristic that the registration deviation of the contact hole and the polycrystalline silicon pattern of the detected product and the image brightness of the contact hole formed by scanning of an electron beam detection device have correlation;
step two, providing the detected product, wherein the polycrystalline silicon pattern and the contact hole are formed on the detected product; scanning the detected product by adopting the electron beam detection equipment and obtaining the image brightness of the contact hole which is aligned with the polysilicon pattern on the detected product;
and thirdly, combining the fitting curve to convert the image brightness of the contact hole corresponding to the detected product into the overlay deviation of the contact hole and the polysilicon pattern of the detected product.
2. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 1, wherein: in the first step, the sub-step of forming the fitted curve includes:
step 11, forming the contact hole and the polysilicon pattern which are the same as the detected product on a test piece, and performing pull bias on the space between the contact hole and the polysilicon pattern on the test piece to form a series of overlay deviations of the contact hole and the polysilicon pattern with different sizes;
step 12, scanning the test piece by adopting the electron beam detection equipment to form a first scanning picture;
step 13, determining the image brightness of each contact hole on the first scanning image;
and 14, fitting the image brightness of each contact hole and the corresponding overlay deviation to form the fitting curve.
3. The method for detecting overlay deviation of contact hole and polysilicon pattern according to claim 2, wherein: in step 11, the test piece is arranged according to the overlay deviation and the overlay deviation direction, so that the positions of the contact holes and the overlay deviation correspond to each other in the overlay deviation direction;
in step 13, the position of the image brightness of each contact hole in the first scanned picture corresponds to the position of the corresponding contact hole on the test piece, and the overlay deviation corresponding to the image brightness of the contact hole is determined according to the position of the image brightness of the contact hole in the first scanned picture.
4. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 3, wherein: the detected product comprises a plurality of products.
5. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 4, wherein: when the types of the detected products are the same, the detected products share the same fitting curve, and the fitting curve is formed only before the first detected product is detected.
6. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 4, wherein: when the types of the detected products comprise a plurality of types, performing the steps before the first detected product of each type is detected, and forming the fitting curve corresponding to the type of the detected product; and in the third step, the tested products of various types adopt the fitting curve corresponding to the types of the tested products.
7. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 6, wherein: in step 11, only the contact hole and the polysilicon pattern which are the same as the detected product of one type are formed on each test sheet; the fitted curves corresponding to the detected products of various types are respectively obtained on different test sheets.
8. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 6, wherein: in step 11, only the contact holes and the polysilicon patterns which are the same as the detected products of more than two types are formed on each test piece, and the contact holes and the polysilicon patterns which are the same as the detected products of different types are formed on different areas of the test piece; and forming the fitting curves corresponding to more than two types of the detected products on the same test sheet.
9. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 4, wherein: the detected product comprises an SRAM product or a logic product.
10. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 9, wherein: the storage unit of the SRAM product comprises a 6T type storage unit, and the 6T type storage unit comprises: the device comprises a first selection pipe, a second selection pipe, a first pull-up pipe, a second pull-up pipe, a first pull-down pipe and a second pull-down pipe;
on the layout structure of the 6T-shaped storage unit, the first pull-down tube and the polysilicon gate of the first pull-up tube are connected together, and the second pull-down tube and the polysilicon gate of the second pull-up tube are connected together;
the first selection tube and the first pull-down tube share a first active region, the first pull-up tube is located in a second active region, the second pull-up tube PPU2 is located in a third active region, and the second pull-down tube and the second selection tube share a fourth active region;
the drain region of the first selection tube and the drain region of the first pull-down tube are shared, and a first contact hole is formed at the top of the drain region of the first pull-down tube; the first contact hole is positioned between the polysilicon gate of the first pull-down tube and the polysilicon gate of the first selection tube;
the drain region of the second selection tube and the drain region of the second pull-down tube are shared, and a second contact hole is formed at the top of the drain region of the second pull-down tube; the second contact hole is positioned between the polysilicon gate of the second pull-down tube and the polysilicon gate of the second selection tube;
the layout of the 6T-shaped storage unit is of a central symmetry structure, the first pull-down tube and the second pull-down tube are symmetrical, the first pull-up tube and the second pull-up tube are symmetrical, the first selection tube and the second selection tube are symmetrical, and the first contact hole and the second contact hole are symmetrical;
the contact hole of the detected product is the first contact hole or the second contact hole; the polysilicon patterns of the detected product are the polysilicon gate of the first pull-down tube and the polysilicon gate of the first selection tube or the polysilicon gate of the second pull-down tube and the polysilicon gate of the second selection tube.
11. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 10, wherein: when the technical node of the SRAM product is reduced, the size of the layout structure of the 6T-shaped storage unit is reduced in an equal proportion, and the sizes of the corresponding first contact hole and the second contact hole are also reduced in an equal proportion.
12. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 11, wherein: the technical node of the SRAM product is less than 55 nm.
13. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 1, wherein: in the second step, the detected product is formed on a product wafer, and the electron beam detection equipment carries out full scanning on the product wafer of the detected product to form a second scanning picture;
and then selecting the image brightness of the corresponding contact hole in the second scanning picture.
14. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 1, wherein: and the brightness of the image of the contact hole formed by scanning the electron beam detection equipment is represented by gray scale values.
15. The method for detecting overlay deviation of contact hole and polysilicon pattern as claimed in claim 1, wherein: the electron beam inspection apparatus scans and forms an image by collecting secondary electrons and backscattered electrons of the electron beam.
CN202011387239.0A 2020-12-02 2020-12-02 Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern Active CN112635344B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011387239.0A CN112635344B (en) 2020-12-02 2020-12-02 Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011387239.0A CN112635344B (en) 2020-12-02 2020-12-02 Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern

Publications (2)

Publication Number Publication Date
CN112635344A CN112635344A (en) 2021-04-09
CN112635344B true CN112635344B (en) 2022-08-16

Family

ID=75307200

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011387239.0A Active CN112635344B (en) 2020-12-02 2020-12-02 Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern

Country Status (1)

Country Link
CN (1) CN112635344B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376601A (en) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 Detection method and structure for deviation of contact hole
CN103346103A (en) * 2013-06-27 2013-10-09 上海华力微电子有限公司 Method for detecting alignment degree between polycrystalline silicon grid and contact hole
CN106298572A (en) * 2016-09-06 2017-01-04 上海华力微电子有限公司 A kind of method detecting the not enough defect of first floor metal derby etching connecting grid

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102944196B (en) * 2012-11-02 2015-08-19 上海华力微电子有限公司 A kind of method detecting circularity of circular contact hole of semiconductor
KR20160007192A (en) * 2014-07-11 2016-01-20 삼성전자주식회사 Overlay measuring methods and system, and method of manufacturing a semiconductor device using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376601A (en) * 2010-08-24 2012-03-14 中芯国际集成电路制造(上海)有限公司 Detection method and structure for deviation of contact hole
CN103346103A (en) * 2013-06-27 2013-10-09 上海华力微电子有限公司 Method for detecting alignment degree between polycrystalline silicon grid and contact hole
CN106298572A (en) * 2016-09-06 2017-01-04 上海华力微电子有限公司 A kind of method detecting the not enough defect of first floor metal derby etching connecting grid

Also Published As

Publication number Publication date
CN112635344A (en) 2021-04-09

Similar Documents

Publication Publication Date Title
US8089297B2 (en) Structure and method for determining a defect in integrated circuit manufacturing process
US8754372B2 (en) Structure and method for determining a defect in integrated circuit manufacturing process
US8299463B2 (en) Test structure for charged particle beam inspection and method for defect determination using the same
US8339449B2 (en) Defect monitoring in semiconductor device fabrication
US20080267489A1 (en) Method for determining abnormal characteristics in integrated circuit manufacturing process
TWI409893B (en) Test structure for charged particle beam inspection and method for defect determination using the same
US9269639B2 (en) Method of detecting and measuring contact alignment shift relative to gate structures in a semicondcutor device
US10451666B2 (en) Methodology for early detection of TS to PC short issue
US8987013B2 (en) Method of inspecting misalignment of polysilicon gate
US7859285B2 (en) Device under test array for identifying defects
CN103346103B (en) Detect the method for polysilicon gate and contact hole Aligning degree
US9735064B2 (en) Charge dynamics effect for detection of voltage contrast defect and determination of shorting location
CN112635344B (en) Method for detecting overlay deviation of contact hole and polycrystalline silicon pattern
US20060220240A1 (en) Analytic structure for failure analysis of semiconductor device
CN103346107A (en) Method for detecting alignment degree between polycrystalline silicon grid and contact hole
US6223097B1 (en) Semiconductor integrated circuit device, method of estimating failure ratio of such devices on the market, and method of manufacturing the devices
Patterson et al. In-line characterization of EDRAM for a FINFET technology using VC inspection
JP2006511077A (en) Method for manufacturing semiconductor device using test structure
Chen et al. Alternative voltage-contrast inspection for pMOS leakage due to adjacent nMOS contact-to-poly misalignment
Song SRAM failure analysis evolution driven by technology scaling
Chen et al. Detection of Electrical Defects by Distinguish Methodology Using an Advanced E-Beam Inspection System
Zhou et al. E-beam inspection BVC (Bright Voltage Contrast) verification for 14nm technology: DI: Defect inspection and reduction
Patterson et al. Creative use of vector scan for efficient SRAM inspection
Kang et al. A New Test Method for Bit Line Disturbance Leakage Current in Dynamic Random Access Memory
US20150294738A1 (en) Test structure and method of testing a microchip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant