CN112634975A - Data storage error correction method and device and electronic equipment - Google Patents
Data storage error correction method and device and electronic equipment Download PDFInfo
- Publication number
- CN112634975A CN112634975A CN202011546073.2A CN202011546073A CN112634975A CN 112634975 A CN112634975 A CN 112634975A CN 202011546073 A CN202011546073 A CN 202011546073A CN 112634975 A CN112634975 A CN 112634975A
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- stored
- block
- data block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0882—Page mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
Abstract
The embodiment of the invention provides a data storage error correction method, a data storage error correction device and electronic equipment, wherein the method comprises the following steps: respectively storing the received data to be stored into a first memory and a second memory as first data and second data; allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table. By the embodiment of the invention, the error correction capability of the solid state disk during data writing is realized, and the reliability of the data stored in the solid state disk is improved.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a data storage error correction method, an apparatus, and an electronic device.
Background
Currently, the development of NAND flash technology has pushed the Solid State Disk (SSD) industry. The performance of an SSD not only depends on the performance of NAND flash memories, but is also largely influenced by NAND controller algorithms. NAND is a non-volatile memory device, the smallest readable unit called a page (page), the smallest erasable unit called a block (block), a block often consisting of many pages. After a block erase, a write operation may be performed to a page within the block. Write operations are slow, much slower than read operations, while erase operations are much slower than writes.
The conventional SSD is mainly composed of a NAND flash Memory, a Static Random-Access Memory (SRAM) for caching data, and a main control chip (SSD Controller). Sometimes, a power-off protection system is also required. In order to guarantee the write performance of the whole SSD, after the main control chip sends data acquired from the host to the NAND memory, the main control chip directly returns to a correct state to the host after asynchronous waiting PAGE programming (NAND PAGE PROGRAM) is finished. That is, the master control chip does not determine whether the data is successfully written, and the host is informed that the data is successfully written.
It can be seen that the conventional SSD technology has a fatal problem that, when a PROGRAM failure (PAGE PROGRAM FAIL) occurs in the flash memory, the current PAGE and its dual PAGE (PAGE) cause data errors. And the correctness of the data of the page belonging to other pages of the block cannot be guaranteed. Resulting in loss of data by the system and even corruption of the entire file system, resulting in an unevaluable loss.
Disclosure of Invention
Embodiments of the present invention provide a data storage error correction method, an apparatus, and an electronic device, so as to solve the problem that when a flash memory fails to be programmed, data errors are caused, and the correctness of data of other pages of a block to which the page belongs cannot be guaranteed, so that the system loses data, and even the entire file system is damaged.
In order to solve the above technical problem, the embodiment of the present invention is implemented as follows:
in a first aspect, an embodiment of the present invention provides a data storage error correction method, including:
respectively storing the received data to be stored in a first memory and a second memory as first data and second data, wherein the first memory is a static random access memory, and the second memory is a non-volatile magnetic random access memory;
allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block;
and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table.
In a second aspect, an embodiment of the present invention provides an error correction apparatus for data storage, including:
the data receiving module is used for respectively storing the received data to be stored into a first memory and a second memory as first data and second data, wherein the first memory is a static random access memory, and the second memory is a nonvolatile magnetic random access memory;
the data storage module is used for allocating storage addresses for the data to be stored according to a data mapping table, sequentially writing the first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block;
and the data error correction module is configured to, when the state of the first data page obtained through querying is an error, write second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and update the address of the first data block to the address of the second data block in the data mapping table.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus; the processor, the communication interface and the memory complete mutual communication through a bus; the memory is used for storing a computer program; the processor is configured to execute the program stored in the memory to implement the data storage error correction method according to the first aspect.
In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the data storage error correction method according to the first aspect are implemented.
As can be seen from the technical solutions provided by the embodiments of the present invention, the embodiments of the present invention respectively store the received data to be stored in the first memory and the second memory as the first data and the second data; allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table. By the embodiment of the invention, the error correction capability of the solid state disk during data writing is realized, and the reliability of the data stored in the solid state disk is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic flow chart of a data storage error correction method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a mapping relationship of a data mapping table according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another mapping relationship of a data mapping table according to an embodiment of the present invention;
FIG. 5 is a block diagram of an error correction apparatus for data storage according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a data storage error correction method, a data storage error correction device and electronic equipment.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 and fig. 2, an embodiment of the present invention provides a data storage error correction method, where an execution subject of the method may be a solid state disk. The method may specifically comprise the steps of:
step S01, storing the received data to be stored in a first memory and a second memory as a first data and a second data, respectively, where the first memory is a static random access memory, and the second memory is a non-volatile magnetic random access memory.
As shown in fig. 2, the solid state disk 100 according to the embodiment of the present invention includes: a main control chip 101, a first memory 102, a second memory 103, and a NAND flash memory 104. The first Memory 102 is a Static Random Access Memory (SRAM), and the second Memory 103 is a non-volatile Magnetic Random Access Memory (MRAM). The host 200 connected to the solid state disk 100 may perform read/write operations on the solid state disk 100 through a preset data interface, where the data interface may be a SATA interface or a PCIe bus interface. The solid state disk 100 and the host may also perform data transmission in a wireless manner.
When data needs to be stored, the host 200 may send the data to be stored to the solid state disk 100 through the data interface. The main control chip 101 of the solid state disk 100 stores the received data to be stored in the first storage 101 and the second storage 102, respectively, where the data to be stored in the first storage 101 is referred to as first data, and the data to be stored in the second storage 102 is referred to as second data.
Step S02, allocating a storage address for the data to be stored according to a data mapping table, sequentially writing the first data in the first memory into a first data page of a first data block, and querying the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block.
The data mapping table of the solid state disk 100 records allocable storage addresses in the form of mapping entries, where the mapping entries specifically include: the block number of the data block in the NAND flash memory 104 and the page number of the data page under the data block. Therefore, according to the data mapping table, the storage address corresponding to the data to be stored, that is, the address of each corresponding first data block of the data to be stored and the address of each first data page under the first data block, can be determined. The first data in the first memory 101 is segmented by taking the data amount of a single page as a unit, and then sequentially sent to the first data page of the corresponding first data block, so as to perform a write operation, i.e., a page programming operation, on the first data page. As shown in fig. 3, the storage addresses that can be allocated for the data to be stored in the data mapping table are pages 0 to 2N-1 of the data block X, the first data in the first memory 101 is divided into pages 0 to 2N-1, and the data is sequentially written into pages 0 to 2N-1 of the data block X.
In the process of sequentially writing the first data into the first data pages of the corresponding first data block, the status of each first data page is queried, and specifically, a query operation may be performed through a corresponding status read command, for example, using a read status command.
Step S03, when the status of the first data page is found to be an error, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block to the address of the second data block in the data mapping table.
And if the state of the first data page is correct, continuing to query the state of the next data page.
And if the inquired state of the first data page is an error, judging that the page programming of the first data page is in error, and considering that all the data stored in the first data block where the first data page is located have errors.
A good data block (goodblock) is selected from the other data blocks as the second data block. Second data corresponding to the first data stored in the first data block currently is searched from the second data stored in the second memory 103, and is written into the second data block. For example, as shown in fig. 4, if the data block X currently stores page 0 data to page N data in the first data, that is, the corresponding first data exists in the page 0 to page N in the data block X, page 0 data to page N data of the second data corresponding to the page 0 data to page N data in the first data are found from the second memory 103, and the part of the second data is written into the page 0 to page N of the data block Y. The second data is used as backup data, so that the accuracy of the data can be ensured.
Meanwhile, the data mapping table is updated, and the address of the first data block in the data mapping table is changed to the address of the second data block, which is equivalent to that a new storage address is newly allocated to the data to be stored, and as shown in fig. 4, the data block X in the data mapping table is changed to the data block Y. Thus enabling remapping of logical addresses to physical addresses.
Further, after the step S03, the method further includes:
step S04, writing the remaining first data in the first memory 102 into the second data block according to the updated data mapping table.
The first memory 102 deletes the first data segment from the first memory 102 after sending the first data segment to the first data page of the first data block for writing operation. Therefore, after the data mapping table is updated, the remaining first data in the first memory 102 may be sent to the second data page of the corresponding second data block for writing.
Similarly, in the process of performing the write operation on the second data page, the state query on the second data page is also required, and whether the second data block needs to be replaced is determined according to the result of the state query.
Further, in the case that the status of the first data page obtained by the query is an error, the method further includes:
the writing of the first data in the first memory 102 into the first data block is stopped.
When the state of the first data page obtained by querying is an error, it is determined that all data in the first data block are in error, and therefore, if the first memory 102 still sends the first data to the first data block at present, the first memory 102 is first stopped sending the first data to the first data block. After the update of the data mapping table is completed, the first memory 102 is enabled to send the remaining first data to the second data block.
If the first memory 102 has started to send the first data to the third data block, the first memory 102 may not need to stop sending the first data to the third data block, that is, the writing of data to the third data block does not need to stop.
As can be seen from the technical solutions provided by the embodiments of the present invention, the embodiments of the present invention respectively store the received data to be stored in the first memory and the second memory as the first data and the second data; allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table. By the embodiment of the invention, the error correction capability of the solid state disk during data writing is realized, and the reliability of the data stored in the solid state disk is improved.
Further, the method further comprises:
and when the states of all the first data pages under the first data block are obtained through inquiry and are normal, clearing second data which are stored in the second memory and correspond to the first data stored in the first data block.
Since a page programming error of any first data page affects data of the entire first data block, the second memory may need to store second data corresponding to the entire first data block, that is, the capacity of the second memory must be greater than or equal to the capacity of the data block.
After querying the states of all the first data pages of the first data block, if the states of all the first data pages of the first data block are normal, in order to save space in the second memory, all the second data corresponding to the first data block may be cleared or overwritten, and the second memory restarts data backup of the next data block.
As can be seen from the above technical solutions provided by the embodiments of the present invention, when the states of all the first data pages under the first data block are obtained through querying, the embodiments of the present invention remove the second data corresponding to the first data already stored in the first data block and stored in the second memory. According to the embodiment of the invention, the requirement on the capacity of the MRAM is reduced, and the cost performance of the product is improved.
Based on the same technical concept, the embodiment of the present invention further provides a data storage error correction apparatus, and fig. 5 is a schematic diagram illustrating a module composition of the data storage error correction apparatus according to the embodiment of the present invention, where the data storage error correction apparatus is configured to execute the data storage error correction method described in fig. 1 to 4, and as shown in fig. 5, the data storage error correction apparatus includes: a data receiving module 501, a data saving module 502 and a data error correction module 503.
The data receiving module 501 is configured to store received data to be stored in a first memory and a second memory as first data and second data, respectively, where the first memory is a static random access memory, and the second memory is a non-volatile magnetic random access memory; the data saving module 502 is configured to allocate a storage address for the data to be stored according to a data mapping table, sequentially write first data in the first memory into a first data page of a first data block, and query a state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block; the data error correction module 503 is configured to, when the state of the first data page is found to be an error, write second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and update the address of the first data block to the address of the second data block in the data mapping table.
Further, the data saving module 502 is further configured to write the remaining first data saved in the first memory into the second data block according to the updated data mapping table.
Further, the data error correction module 503 is further configured to stop writing the first data in the first memory into the first data block.
As can be seen from the above technical solutions provided by the embodiments of the present invention, the embodiments of the present invention respectively store the received data to be stored in the first memory and the second memory as the first data and the second data; allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table. By the embodiment of the invention, the error correction capability of the solid state disk during data writing is realized, and the reliability of the data stored in the solid state disk is improved.
Further, the apparatus further comprises: and the data clearing module is used for clearing second data corresponding to the first data stored in the first data block and stored in the second memory when the states of all the first data pages under the first data block are obtained through inquiry and are normal.
As can be seen from the above technical solutions provided by the embodiments of the present invention, when the states of all the first data pages under the first data block are obtained through querying, the embodiments of the present invention remove the second data corresponding to the first data already stored in the first data block and stored in the second memory. According to the embodiment of the invention, the requirement on the capacity of the MRAM is reduced, and the cost performance of the product is improved.
The data storage error correction device provided by the embodiment of the invention can realize each process in the embodiment corresponding to the data storage error correction method, and is not described again to avoid repetition.
It should be noted that the data storage error correction apparatus provided in the embodiment of the present invention and the data storage error correction method provided in the embodiment of the present invention are based on the same inventive concept, and therefore, for specific implementation of the embodiment, reference may be made to the implementation of the data storage error correction method, and repeated details are not described again.
Based on the same technical concept, the embodiment of the present invention further provides an electronic device for executing the data storage error correction method, and fig. 6 is a schematic structural diagram of an electronic device implementing the embodiments of the present invention, as shown in fig. 6. Electronic devices may vary widely in configuration or performance and may include one or more processors 601 and memory 602, where one or more stored applications or data may be stored in memory 602. Wherein the memory 602 may be transient or persistent storage. The application program stored in memory 602 may include one or more modules (not shown), each of which may include a series of computer-executable instructions for the electronic device. Still further, the processor 601 may be arranged in communication with the memory 602 to execute a series of computer-executable instructions in the memory 602 on the electronic device. The electronic device may also include one or more power supplies 603, one or more wired or wireless network interfaces 604, one or more input-output interfaces 605, one or more keyboards 606.
Specifically, in this embodiment, the electronic device includes a processor, a communication interface, a memory, and a communication bus; the processor, the communication interface and the memory complete mutual communication through a bus; the memory is used for storing a computer program; the processor is used for executing the program stored in the memory and realizing the following method steps:
respectively storing the received data to be stored in a first memory and a second memory as first data and second data, wherein the first memory is a static random access memory, and the second memory is a non-volatile magnetic random access memory;
allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block;
and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table.
An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when executed by a processor, the computer program implements the following method steps:
respectively storing the received data to be stored in a first memory and a second memory as first data and second data, wherein the first memory is a static random access memory, and the second memory is a non-volatile magnetic random access memory;
allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block;
and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, an electronic device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, apparatus or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A method for error correction in data storage, the method comprising:
respectively storing the received data to be stored in a first memory and a second memory as first data and second data, wherein the first memory is a static random access memory, and the second memory is a non-volatile magnetic random access memory;
allocating a storage address for the data to be stored according to a data mapping table, sequentially writing first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block;
and under the condition that the state of the first data page is found to be an error by inquiry, writing second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and updating the address of the first data block into the address of the second data block in the data mapping table.
2. The data storage error correction method of claim 1, wherein after the step of updating the address of the first data block to the address of the second data block in the data mapping table, the method further comprises:
and writing the remaining first data stored in the first memory into the second data block according to the updated data mapping table.
3. The data storage error correction method of claim 1, wherein in case that the status of the first data page is found to be an error, the method further comprises:
stopping writing the first data in the first memory into the first data block.
4. The data storage error correction method of claim 1, further comprising:
and when the states of all the first data pages under the first data block are obtained through inquiry and are normal, clearing second data which are stored in the second memory and correspond to the first data stored in the first data block.
5. An apparatus for data storage error correction, the apparatus comprising:
the data receiving module is used for respectively storing the received data to be stored into a first memory and a second memory as first data and second data, wherein the first memory is a static random access memory, and the second memory is a nonvolatile magnetic random access memory;
the data storage module is used for allocating storage addresses for the data to be stored according to a data mapping table, sequentially writing the first data in the first memory into a first data page of a first data block, and inquiring the state of the first data page; the storage address comprises an address of a first data block corresponding to the data to be stored and an address of a first data page under the first data block;
and the data error correction module is configured to, when the state of the first data page obtained through querying is an error, write second data corresponding to the first data written in the first data block and stored in the second memory into a second data block, and update the address of the first data block to the address of the second data block in the data mapping table.
6. The data storage error correction device of claim 5, wherein the data storage module is further configured to write the remaining first data stored in the first memory into the second data block according to the updated data mapping table.
7. The data storage error correction device of claim 5, wherein the data error correction module is further configured to stop writing the first data in the first memory into the first data block.
8. The data storage error correction apparatus of claim 5, wherein the apparatus further comprises: and the data clearing module is used for clearing second data corresponding to the first data stored in the first data block and stored in the second memory when the states of all the first data pages under the first data block are obtained through inquiry and are normal.
9. An electronic device comprising a processor, a communication interface, a memory, and a communication bus; the processor, the communication interface and the memory complete mutual communication through a bus; the memory is used for storing a computer program; the processor is used for executing the program stored in the memory to realize the data storage error correction method steps according to any one of claims 1 to 4.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the data storage error correction method steps of any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011546073.2A CN112634975A (en) | 2020-12-24 | 2020-12-24 | Data storage error correction method and device and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011546073.2A CN112634975A (en) | 2020-12-24 | 2020-12-24 | Data storage error correction method and device and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112634975A true CN112634975A (en) | 2021-04-09 |
Family
ID=75324361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011546073.2A Pending CN112634975A (en) | 2020-12-24 | 2020-12-24 | Data storage error correction method and device and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112634975A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114327258A (en) * | 2021-11-30 | 2022-04-12 | 苏州浪潮智能科技有限公司 | Solid state disk processing method, system, equipment and computer storage medium |
| TWI811674B (en) * | 2021-05-06 | 2023-08-11 | 大陸商北京集創北方科技股份有限公司 | Operation method of flash memory, system single chip and information processing device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100131736A1 (en) * | 2008-11-21 | 2010-05-27 | Jae Don Lee | Memory device and method of operation |
| US20150143198A1 (en) * | 2013-11-15 | 2015-05-21 | Qualcomm Incorporated | Method and apparatus for multiple-bit dram error recovery |
| US20170052708A1 (en) * | 2015-08-21 | 2017-02-23 | Mstar Semiconductor, Inc. | Method for accessing flash memory and associated memory controller and electronic device |
| US20180225176A1 (en) * | 2017-02-06 | 2018-08-09 | Samsung Electronics Co., Ltd. | Storage device for processing corrupted metadata and method of operating the same |
| US20180307558A1 (en) * | 2017-04-25 | 2018-10-25 | Silicon Motion, Inc. | Data Storage Devices and Methods for Rebuilding a Memory Address Mapping Table |
| US20190138445A1 (en) * | 2017-11-03 | 2019-05-09 | Hefei Core Storage Electronic Limited | Mapping table updating method, memory control circuit unit and memory storage device |
-
2020
- 2020-12-24 CN CN202011546073.2A patent/CN112634975A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100131736A1 (en) * | 2008-11-21 | 2010-05-27 | Jae Don Lee | Memory device and method of operation |
| US20150143198A1 (en) * | 2013-11-15 | 2015-05-21 | Qualcomm Incorporated | Method and apparatus for multiple-bit dram error recovery |
| US20170052708A1 (en) * | 2015-08-21 | 2017-02-23 | Mstar Semiconductor, Inc. | Method for accessing flash memory and associated memory controller and electronic device |
| US20180225176A1 (en) * | 2017-02-06 | 2018-08-09 | Samsung Electronics Co., Ltd. | Storage device for processing corrupted metadata and method of operating the same |
| US20180307558A1 (en) * | 2017-04-25 | 2018-10-25 | Silicon Motion, Inc. | Data Storage Devices and Methods for Rebuilding a Memory Address Mapping Table |
| US20190138445A1 (en) * | 2017-11-03 | 2019-05-09 | Hefei Core Storage Electronic Limited | Mapping table updating method, memory control circuit unit and memory storage device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI811674B (en) * | 2021-05-06 | 2023-08-11 | 大陸商北京集創北方科技股份有限公司 | Operation method of flash memory, system single chip and information processing device |
| CN114327258A (en) * | 2021-11-30 | 2022-04-12 | 苏州浪潮智能科技有限公司 | Solid state disk processing method, system, equipment and computer storage medium |
| WO2023098269A1 (en) * | 2021-11-30 | 2023-06-08 | 苏州浪潮智能科技有限公司 | Solid-state drive processing method, system, and device, and non-volatile readable storage medium |
| CN114327258B (en) * | 2021-11-30 | 2023-08-15 | 苏州浪潮智能科技有限公司 | Solid state disk processing method, system, equipment and computer storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2920700B1 (en) | Memory segment remapping to address fragmentation | |
| CN109426619B (en) | Method for accessing flash memory module, related flash memory controller and electronic device | |
| US8650379B2 (en) | Data processing method for nonvolatile memory system | |
| US10468077B2 (en) | Adaptive object buffering and meta-data indexing using persistent memory to improve flash memory durability in tiered storage | |
| US20110320689A1 (en) | Data Storage Devices and Data Management Methods for Processing Mapping Tables | |
| JP2013222435A (en) | Semiconductor storage device and method of controlling the same | |
| CN112634975A (en) | Data storage error correction method and device and electronic equipment | |
| CN111831215A (en) | Apparatus for transferring mapping information in memory system | |
| CN114356248A (en) | Data processing method and device | |
| CN110989931A (en) | Bad block processing method, device and equipment for storage equipment and storage medium | |
| CN111124294B (en) | Sector mapping information management method and device, storage medium and equipment | |
| KR20200058867A (en) | Apparatus and method for reducing repeated access to the same block of the memory system during receovery procedure | |
| CN115617542A (en) | Memory exchange method and device, computer equipment and storage medium | |
| CN115079957A (en) | Request processing method, device, controller, equipment and storage medium | |
| CN112083883B (en) | Storage system and method for use in storage system | |
| CN109002265B (en) | Data processing method and related device | |
| KR20230081505A (en) | Memory controller and operating method thereof | |
| CN110286850B (en) | Writing method and recovery method of metadata of solid state disk and solid state disk | |
| JP2013196155A (en) | Memory system | |
| CN108509295B (en) | Operation method of memory system | |
| JP4239754B2 (en) | Nonvolatile memory system | |
| US10671322B1 (en) | Method for performing storage space management, associated data storage device, and controller thereof | |
| US11366611B2 (en) | Apparatus for transmitting map information in a memory system | |
| US20230305721A1 (en) | Method and apparatus for memory management in memory disaggregation environment | |
| CN113703671B (en) | Data block erasing method and related device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210409 |