CN112634961A - Three-dimensional memory and control method thereof - Google Patents
Three-dimensional memory and control method thereof Download PDFInfo
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- CN112634961A CN112634961A CN202110004811.9A CN202110004811A CN112634961A CN 112634961 A CN112634961 A CN 112634961A CN 202110004811 A CN202110004811 A CN 202110004811A CN 112634961 A CN112634961 A CN 112634961A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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Abstract
The invention relates to a control method of a three-dimensional memory, wherein the three-dimensional memory comprises a plurality of memory strings, each memory string comprises a plurality of memory units which are connected in series, and the control method comprises the following steps: simultaneously performing a precharge operation on a bit line connected to the top of each memory string and an array common source connected to the bottom of each memory string during a precharge phase of the program operation; wherein the precharge operation is for clearing channel residual electrons in the top dummy memory cells of the plurality of memory strings.
Description
Technical Field
The invention relates to a control method of a three-dimensional memory, which can clear channel residual electrons in a plurality of dummy memory cells positioned at the top in a plurality of memory strings and optimize programming interference.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
As market demands for memory density continue to increase, programming methods with more programming states are being developed so that each physical memory cell (cell) can represent more bits (bit) of information. However, the implementation of more programmed states has higher requirements on the formation process of a single memory cell and the distribution uniformity among multiple memory cells. Therefore, how to increase the storage density of the memory cells and improve the performance of the three-dimensional memory is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a control method of a three-dimensional memory, which can eliminate channel residual electrons in a plurality of dummy memory units positioned at the top in a plurality of memory strings and optimize programming interference.
The present invention has been made to solve the above-mentioned problems, and an aspect of the present invention is to provide a method for controlling a three-dimensional memory, the three-dimensional memory including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series, the method including: simultaneously performing a precharge operation on a bit line connected to the top of each of the memory strings and an array common source connected to the bottom of each of the memory strings during a precharge phase of a program operation; wherein the precharge operation is to clear channel residual electrons in a top plurality of dummy memory cells of the plurality of memory strings.
In an embodiment of the present invention, a method of performing the precharge operation on the bit line includes: a floating voltage is applied to the bit lines, and a first turn-on voltage is applied to top select gates connected to a plurality of top select transistors of each of the memory strings.
In an embodiment of the present invention, a method for performing the precharge operation on the array common source includes: a bias voltage is applied to the array common source, and a second turn-on voltage is applied to the bottom select gates connected to the plurality of bottom select transistors of each of the memory strings.
In one embodiment of the invention, the bias voltage is maintained coincident with the floating voltage by coupling.
In an embodiment of the invention, the first turn-on voltage and the second turn-on voltage have the same magnitude.
In an embodiment of the invention, the magnitude of the bias voltage is 0 to 5V.
In an embodiment of the invention, the first turn-on voltage and the second turn-on voltage are respectively 0 to 5V.
In an embodiment of the invention, the bias voltage, the first turn-on voltage and the second turn-on voltage are adjustable voltages.
In an embodiment of the present invention, the control method is performed when a memory cell near the top among the plurality of memory cells is programmed.
In one embodiment of the present invention, the programming is reverse programming.
Another aspect of the present invention provides a three-dimensional memory including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series, the three-dimensional memory further including: a control circuit configured to simultaneously precharge a bit line connected to a top of each of the memory strings and an array common source connected to a bottom of each of the memory strings during a precharge phase of a program operation; wherein the precharge operation is to clear channel residual electrons in a top plurality of dummy memory cells of the plurality of memory strings.
In an embodiment of the present invention, a method of the control circuit performing the precharge operation on the bit line includes: a floating voltage is applied to the bit lines, and a first turn-on voltage is applied to top select gates connected to a plurality of top select transistors of each of the memory strings.
In an embodiment of the present invention, the method for the control circuit to perform the precharge operation on the array common source includes: a bias voltage is applied to the array common source, and a second turn-on voltage is applied to the bottom select gates connected to the plurality of bottom select transistors of each of the memory strings.
In one embodiment of the invention, the bias voltage is maintained coincident with the floating voltage by coupling.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
the control method of the three-dimensional memory effectively eliminates channel residual electrons in a plurality of dummy memory units positioned at the top in a plurality of memory strings and optimizes programming interference by simultaneously carrying out the precharge operation on the bit line connected with the top of each memory string and the array common source connected with the bottom of each memory string in the precharge stage of the programming operation.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIGS. 1 and 2 are schematic diagrams of a programming sequence of a three-dimensional memory, respectively;
FIG. 3 is a schematic diagram of a control method of a three-dimensional memory;
FIG. 4 is a flowchart illustrating a method for controlling a three-dimensional memory according to an embodiment of the invention;
FIG. 5 is a diagram illustrating a method for controlling a three-dimensional memory according to an embodiment of the invention;
fig. 6 is a diagram of a three-dimensional memory according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
As the demand for storage capacity increases, the number of storage layers of a three-dimensional memory (e.g., 3D NAND) increases. Due to the limitation of the process etching, when the number of layers is increased, the shape consistency of the bottom storage layer unit is deteriorated. Fig. 1 and 2 are schematic diagrams of a programming sequence of a three-dimensional memory, respectively. Referring to fig. 1 and 2, in order to improve the memory characteristics of the bottom device, the reverse programming shown in fig. 2 is generally adopted, i.e., the programming is started from the top memory cell, and the programming is performed to the bottom memory cell step by step, so that the disturbance of the turn-on voltage of the bottom memory cell is reduced, and the like, and the memory characteristics are improved.
Fig. 3 is a schematic diagram of a control method of a three-dimensional memory. Referring to fig. 3, after reverse programming is adopted, one control method is to extract channel residual electrons by using a source side (array common source ACS) precharge operation (pre-charge), so as to increase a coupling potential during programming of a program Inhibit String (Inhibit String) channel, and reduce program disturb. In this case, when the memory cell connected to the topmost word line is programmed and the adjacent sub-level is programmed, the precharge operation from the bottom array common source cannot clear the residual electrons in the channel corresponding to the top dummy word line due to the topmost pinch-off state, thereby causing program disturb to the layer.
In view of the above problems, the following embodiments of the present invention provide a control method for a three-dimensional memory, which can clear channel residual electrons in a plurality of dummy memory cells located at the top of a plurality of memory strings and optimize program disturb.
The three-dimensional memory of the invention comprises a plurality of memory strings, each memory string comprising a plurality of memory cells connected in series. The control method of the three-dimensional memory comprises the following steps: simultaneously performing a precharge operation on a bit line connected to the top of each memory string and an array common source connected to the bottom of each memory string during a precharge phase of the program operation; wherein the precharge operation is for clearing channel residual electrons in the top dummy memory cells of the plurality of memory strings.
Fig. 4 is a flowchart of a method for controlling a three-dimensional memory according to an embodiment of the invention. Fig. 5 is a schematic diagram illustrating a control method of a three-dimensional memory according to an embodiment of the invention. The control method will be described below with reference to fig. 4 and 5. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Referring to fig. 4, the control method includes the steps of:
step S10, during the pre-charge phase of the program operation, simultaneously performing a pre-charge operation on the bit line connected to the top of each memory string and the array common source connected to the bottom of each memory string; wherein the precharge operation clears channel residual electrons in the top dummy memory cells of the plurality of memory strings.
In some examples, the three-dimensional memory may include a plurality of memory strings each including a plurality of memory cells connected in series from top to bottom, and a plurality of word lines each connected to the memory cells located at the same height in each of the memory strings.
Preferably, the three-dimensional memory may be a 3D NAND.
In one embodiment of the present invention, the programming may be reverse programming. It should be understood that reverse programming may refer to a top-down programming order, but the invention is not so limited.
This control method will be specifically described below with reference to fig. 5. In some embodiments, each memory string (not shown) may include a plurality of top select pipes, a plurality of dummy memory cells at the top, a plurality of memory cells, a plurality of dummy memory cells at the bottom, and a plurality of bottom select pipes connected in series from top to bottom.
Referring to fig. 5, a plurality of Top Select gates are connected to the Top Select Gates (TSG), a plurality of Top dummy memory cells are respectively connected to the dummy word lines (e.g., Top dummy word lines Top DMY) having a corresponding height, a plurality of Bottom dummy memory cells are respectively connected to the word lines (e.g., word lines WL) having a corresponding height, a plurality of Bottom dummy memory cells are respectively connected to the dummy word lines (e.g., Bottom dummy word lines Bottom DMY) having a corresponding height, and a plurality of Bottom Select gates are connected to the Bottom Select Gates (BSG).
During the precharge phase of the program operation, the Bit Line (BL) connected to the top of each memory string and the Array Common Source (ACS) connected to the bottom of each memory string may be precharged simultaneously. The precharge operation may remove the channel residual electrons in the Top dummy memory cells (i.e., the dummy memory cells connected to the Top dummy word lines Top DMY) in the memory strings.
It is understood that each bit line BL may connect one memory string, while the array common source ACS may connect the entire memory block (block).
Referring to fig. 5, in an embodiment of the present invention, a method for performing a precharge operation on a bit line BL includes: applying a floating voltage V to the bit line BLfloatingAnd a first turn-on voltage is applied to the top select gates TSG connected to the plurality of top select transistors of each memory string.
The bit line BL adopts a Floating scheme, which can prevent the memory cells corresponding to a part of the word lines from being in an erased state, and a "false pinch-off" state from occurring, which results in channel punch-through.
By applying a floating voltage V to the bit line BL connected to the top of each memory stringfloatingAnd applying a first turn-on voltage to the Top select gates TSG connected to the plurality of Top select transistors of each memory string to make the pinched-off memory cells have a voltage difference from the bit line BL to the dummy word line Top DMY, thereby facilitating the removal of the channel residual electrons in the dummy memory cells.
With continued reference to fig. 5, in an embodiment of the invention, a method of pre-charging an array common-source ACS includes: a bias voltage Vdd is applied to the array common source ACS and a second turn-on voltage is applied to the bottom select gates BSG connected to the plurality of bottom select transistors of each memory string.
Preferably, the first turn-on voltage and the second turn-on voltage have the same magnitude. For example, in the example shown in fig. 5, the first turn-on voltage and the second turn-on voltage are both turn-on voltages Vcc, but the invention is not limited thereto.
In one embodiment of the present invention, the bias voltage Vdd can be coupled to the floating voltage VfloatingAnd the consistency is maintained.
It should be understood that the bias voltage Vdd can be related to the floating voltage V through the "parallel plate capacitance principlefloatingCoupled to maintain the voltage of the two identical. The voltage coupling can effectively prevent the bit line BL from having a voltage difference with the array common source ACS to cause the active channel leakage current, thereby reducing the effect of the pre-charge operation.
In an embodiment of the invention, the bias voltage Vdd, the first turn-on voltage and the second turn-on voltage are adjustable voltages.
For example, the bias voltage Vdd applied to the array common-source ACS may be an adjustable voltage and may have a magnitude of 0 to 5V.
For example, the first and second turn-on voltages (e.g., the turn-on voltage Vcc shown in fig. 5) may be adjustable voltages, and have magnitudes of 0 to 5V, respectively.
In an embodiment of the invention, the above control method is performed when programming a memory cell near the top of the plurality of memory cells. For example, referring to fig. 5, the above control method may be performed when programming a memory cell near the top of the plurality of memory cells, but the invention is not limited thereto.
The control method of the three-dimensional memory effectively eliminates channel residual electrons in a plurality of dummy memory units positioned at the top in a plurality of memory strings and optimizes programming interference by simultaneously carrying out the precharge operation on the bit line connected with the top of each memory string and the array common source connected with the bottom of each memory string in the precharge stage of the programming operation.
The flowchart shown in fig. 4 is used herein to illustrate the steps/operations performed by the control method according to an embodiment of the present application. It should be understood that these steps/operations are not necessarily performed in the exact order in which they are performed. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
The above embodiments of the present invention provide a control method for a three-dimensional memory, which can remove channel residual electrons in a plurality of dummy memory cells located at the top of a plurality of memory strings and optimize program disturb.
Another aspect of the present invention is directed to a three-dimensional memory which can optimize program disturb by removing channel residual electrons from a plurality of dummy memory cells located at the top among a plurality of memory strings through a control circuit thereof.
Fig. 6 is a diagram of a three-dimensional memory according to an embodiment of the invention. The three-dimensional memory 600 will be described with reference to fig. 6. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
It should be noted that the above control method can be implemented in, for example, the three-dimensional memory 600 shown in fig. 6 or a variation thereof, but the invention is not limited thereto.
The three-dimensional memory 600 of the present invention includes a plurality of memory strings, each memory string including a plurality of memory cells connected in series. The three-dimensional memory 600 also includes a control circuit 610. The control circuit 610 is configured to simultaneously precharge the bit lines connected to the top of each memory string and the array common source connected to the bottom of each memory string during a precharge phase of the program operation. Wherein the precharge operation is for clearing channel residual electrons in the top dummy memory cells of the plurality of memory strings.
In one embodiment of the present invention, the programming may be reverse programming. It should be understood that reverse programming may refer to a top-down programming order, but the invention is not so limited.
Preferably, the three-dimensional memory 600 may be a 3D NAND.
Referring to fig. 5, in an embodiment of the invention, a method for the control circuit 610 to perform a precharge operation on the bit line BL includes: applying a floating voltage V to the bit line BLfloatingAnd a first turn-on voltage is applied to the top select gates TSG connected to the plurality of top select transistors of each memory string.
In an embodiment of the present invention, a method for performing a precharge operation on an array common-source ACS by the control circuit 610 includes: a bias voltage Vdd is applied to the array common source ACS and a second turn-on voltage is applied to the bottom select gates BSG connected to the plurality of bottom select transistors of each memory string.
Preferably, the first turn-on voltage and the second turn-on voltage have the same magnitude. For example, in the example shown in fig. 5, the first turn-on voltage and the second turn-on voltage are both turn-on voltages Vcc, but the invention is not limited thereto.
In one embodiment of the present invention, the bias voltage Vdd can be coupled to the floating voltage VfloatingAnd the consistency is maintained.
In an embodiment of the invention, the bias voltage Vdd, the first turn-on voltage and the second turn-on voltage are adjustable voltages.
For example, the bias voltage Vdd applied to the array common-source ACS may be an adjustable voltage and may have a magnitude of 0 to 5V.
For example, the first and second turn-on voltages (e.g., the turn-on voltage Vcc shown in fig. 5) may be adjustable voltages, and have magnitudes of 0 to 5V, respectively.
In an embodiment of the invention, the control circuit 610 may perform the above-mentioned control method when programming a memory cell near the top of the plurality of memory cells. For example, referring to fig. 5, the control circuit 610 may perform the above-mentioned control method when programming the top memory cell of the plurality of memory cells, but the invention is not limited thereto.
The three-dimensional memory (e.g., the three-dimensional memory 600) of the present invention can perform a precharge operation on the bit line connected to the top of each memory string and the array common source connected to the bottom of each memory string simultaneously through the control circuit (e.g., the control circuit 610) during a precharge phase of a program operation, thereby effectively eliminating channel residual electrons in the dummy memory cells at the top of the memory strings and optimizing program disturb.
Further implementation details of the three-dimensional memory of the present embodiment can refer to the embodiments described in fig. 4 and 5, and are not expanded herein. Those skilled in the art can make appropriate adjustments to the internal structure of the three-dimensional memory 600 according to actual needs, and the invention is not limited thereto.
The above embodiments of the present invention propose a three-dimensional memory which can optimize program disturb by eliminating channel residual electrons in the top dummy memory cells in a plurality of memory strings through its control circuit.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
The computer-readable storage media referred to in this application may include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD)), smart cards, and flash memory devices (e.g., electrically erasable programmable read-only memory (EPROM), card, stick, key drive). In addition, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media (and/or storage media) capable of storing, containing, and/or carrying code and/or instructions and/or data.
It should be understood that the above-described embodiments are illustrative only. The embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and/or other electronic units designed to perform the functions described herein, or a combination thereof.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (14)
1. A control method of a three-dimensional memory, the three-dimensional memory including a plurality of memory strings each including a plurality of memory cells connected in series, the control method comprising:
simultaneously performing a precharge operation on a bit line connected to the top of each of the memory strings and an array common source connected to the bottom of each of the memory strings during a precharge phase of a program operation;
wherein the precharge operation is to clear channel residual electrons in a top plurality of dummy memory cells of the plurality of memory strings.
2. The method of claim 1, wherein the method of performing the precharge operation on the bit line comprises: a floating voltage is applied to the bit lines, and a first turn-on voltage is applied to top select gates connected to a plurality of top select transistors of each of the memory strings.
3. The control method according to claim 2, wherein the method of performing the precharge operation on the array common source comprises: a bias voltage is applied to the array common source, and a second turn-on voltage is applied to the bottom select gates connected to the plurality of bottom select transistors of each of the memory strings.
4. The control method of claim 3, wherein the bias voltage is maintained consistent with the floating voltage by coupling.
5. The control method according to claim 3, wherein the first turn-on voltage and the second turn-on voltage are the same in magnitude.
6. The control method according to claim 3, wherein the magnitude of the bias voltage is 0 to 5V.
7. The control method according to claim 3, wherein the first and second turn-on voltages have magnitudes of 0 to 5V, respectively.
8. The control method of claim 3, wherein the bias voltage, the first turn-on voltage, and the second turn-on voltage are adjustable voltages.
9. The control method of claim 1, wherein the control method is performed when programming a top-near memory cell of the plurality of memory cells.
10. Control method according to claim 1, characterized in that the programming is a reverse programming.
11. A three-dimensional memory comprising a plurality of memory strings, each of the memory strings comprising a plurality of memory cells connected in series, the three-dimensional memory further comprising:
a control circuit configured to simultaneously precharge a bit line connected to a top of each of the memory strings and an array common source connected to a bottom of each of the memory strings during a precharge phase of a program operation;
wherein the precharge operation is to clear channel residual electrons in a top plurality of dummy memory cells of the plurality of memory strings.
12. The three-dimensional memory according to claim 11, wherein the method of the control circuit performing the precharge operation on the bit line comprises: a floating voltage is applied to the bit lines, and a first turn-on voltage is applied to top select gates connected to a plurality of top select transistors of each of the memory strings.
13. The three-dimensional memory according to claim 12, wherein the method for the control circuit to perform the precharge operation on the array common source comprises: a bias voltage is applied to the array common source, and a second turn-on voltage is applied to the bottom select gates connected to the plurality of bottom select transistors of each of the memory strings.
14. The three-dimensional memory according to claim 13, wherein the bias voltage is maintained in conformity with the floating voltage by coupling.
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