CN112631091B - Wafer alignment method in photoetching process - Google Patents

Wafer alignment method in photoetching process Download PDF

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Publication number
CN112631091B
CN112631091B CN202011462841.6A CN202011462841A CN112631091B CN 112631091 B CN112631091 B CN 112631091B CN 202011462841 A CN202011462841 A CN 202011462841A CN 112631091 B CN112631091 B CN 112631091B
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alignment
wafer
alignment mark
mark
lithography process
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CN112631091A (en
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王绪根
李玉华
吴长明
姚振海
陈骆
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7023—Aligning or positioning in direction perpendicular to substrate surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7049—Technique, e.g. interferometric
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7092—Signal processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The invention discloses a wafer alignment method in a photoetching process, wherein an alignment mark is arranged on a wafer, a grating pattern is arranged on the alignment mark, and the wafer alignment method comprises the following steps: scanning the whole section of alignment mark by using an alignment light source, and collecting diffraction light signals corresponding to the whole section of alignment mark to form a whole section of alignment signal. And step two, carrying out segmentation processing on the whole segment of alignment signals and forming each segment of alignment signals. And step three, respectively calculating the MCC value and the WQ value of each segmented alignment signal. And step four, calculating alignment points by adopting the segmented alignment signals with the best MCC value and WQ value so as to realize wafer alignment. The invention can reduce the failure rate of wafer rejection and improve the rotation ratio of the wafer.

Description

Wafer alignment method in photoetching process
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing process, and more particularly, to a wafer alignment method in a photolithography process.
Background
Integrated circuit fabrication mainly involves lithography, etching, deposition, thin film, Chemical Mechanical Polishing (CMP). Photolithography is among the most important pattern forming departments.
The pattern formation by photolithography is mainly gumming, exposure and development. Each step is important, and one step is not necessary.
The photolithography process tools are mainly a photoresist developer (Track) and an Exposure Tool (Exposure Tool).
In the photoetching process, the wafer is firstly coated with glue in a Track machine, then is exposed in an exposure machine, and then is developed in the Track machine after exposure is finished, and a photoresist pattern is formed after development.
The exposure machine mainly projects a pattern on the mask plate onto the photoresist of the wafer after the laser penetrates through the mask plate, so that the photoresist is exposed. The wafer often has multiple lithography layers with registration between the lithography layers.
In order to achieve good registration accuracy between the photolithography layers, alignment (alignment) is required to align a pattern on a reticle (reticle) with a wafer during exposure, which is mainly achieved through an alignment process. The Alignment process includes Reticle Alignment (RA), which requires the use of mask Alignment marks provided on the Reticle. Then, Coarse alignment (Coarse alignment) is performed on the wafer, and the full-field alignment mark is used. Then, in performing Fine Alignment (Fine Alignment) of the wafer, it is necessary to use a Fine Alignment mark.
The invention relates to accurate alignment of a wafer, wherein an alignment mark corresponding to the accurate alignment is provided with a grating structure, and the alignment of a fine structure is realized through diffraction of a grating, for example, the types of the grating structures corresponding to the accurate alignment mark adopted by a photoetching machine of Dutch ALSM company comprise CT-AH32, CT-AH53, CT-AH74 and CT-AH157-1, wherein a strip pattern forming a grating period is provided with a finer pattern:
as shown in FIG. 1A, it is a photograph of alignment mark CT-AH 32; the dashed box 101 corresponds to the undamaged alignment mark picture with the model of CT-AH32, and it can be seen that the strip pattern of the grating period has 2 strips and 1 interval, thus the light intensity of the 3 rd order diffracted light can be enhanced;
as shown in FIG. 1B, it is a photograph of the alignment mark with model CT-AH 53; the dashed box 102 corresponds to the undamaged photograph of the alignment mark with the model CT-AH53, and the stripe pattern of the grating period of CT-AH53 has 3 stripes and 2 spaces, so that the light intensity of the 5 th order diffracted light can be enhanced.
As shown in FIG. 1C, it is a photograph of the alignment mark with model CT-AH 74; the dotted frame 103 corresponds to an undamaged alignment mark photograph with the model CT-AH74, and the bar pattern of the grating period of CT-AH74 has 4 bars and 3 spaces, so that the light intensity of the 7 th order diffracted light can be enhanced.
When the wafer is aligned, the wafer is placed in an exposure machine, an alignment light source in the exposure machine is used for irradiating the alignment mark, then diffraction light signals of the alignment mark are collected and subjected to photoelectric conversion to form alignment signals, and alignment is carried out according to the alignment signals.
However, the alignment marks are fine in structure, and since the alignment marks are formed on the front layer patterns, the alignment marks are easily damaged after the film layer of the current photoetching layer grows, so that the collected alignment signals are distorted.
The dashed box 101A in fig. 1A corresponds to a photograph of a damaged alignment mark with the type CT-AH32, and it can be seen that there is a large defect in the alignment mark.
The dashed box 102a in fig. 1B corresponds to a photograph of a damaged alignment mark with the type CT-AH53, and it can be seen that there is a large defect in the alignment mark.
The dashed box 103a in fig. 1C corresponds to a photograph of a damaged alignment mark with the type CT-AH74, and it can be seen that there is a large defect in the alignment mark.
The ideal alignment signal conforms to the sine and cosine curve, but the distorted alignment signal does not conform to the sine and cosine curve. In the conventional method, the alignment signal of the entire alignment mark or the center of the alignment mark is calculated to realize alignment, when the alignment mark is damaged, the alignment signal of the entire alignment mark is definitely distorted, and the alignment signal of the center of the alignment mark is also easily distorted, so that an exposure machine directly rejects exposure to cause wafer reject (wafer reject), and thus a good wafer reject failure rate is generated. As shown in fig. 2A, the alignment mark with the model CT-AH53 corresponds to an ideal alignment signal curve 201, and the curve 201 conforms to the sine and cosine curve. As shown in fig. 2B, is the distortion versus bit signal curve 202 corresponding to fig. 2A; the curve 202 is much different from the curve 201 and will be rejected by the exposure tool.
In the conventional method, wafer reject failure often occurs due to the photolithography alignment mode, and particularly, the reject failure rate of a Power (Power) device product is very high during the photolithography exposure of a Top metal layer (Top metal), a Passivation layer (Passivation) and a polyimide layer (polyimide layer) in a back end of line (BEOL), so that rework is required, which results in a reduction of a wafer turn ratio (wafer turn rate), an increase of wafer cost, and even a risk of wafer rejection due to misjudgment. The wafer turn ratio represents the number of process stations the wafer has gone through a day.
Disclosure of Invention
The invention aims to provide a wafer alignment method in a photoetching process, which can reduce the failure rate of wafer rejection and improve the rotation ratio of the wafer.
In order to solve the above technical problem, in the wafer alignment method in the photolithography process provided by the present invention, the wafer has an alignment mark, and the alignment mark has a grating pattern thereon, and the wafer alignment method includes the following steps:
scanning the whole section of the alignment mark by using an alignment light source, and collecting diffraction light signals corresponding to the whole section of the alignment mark to form a whole section of alignment signals.
And step two, carrying out segmentation processing on the whole segment of alignment signals and forming each segment of alignment signals.
And step three, respectively calculating a Multiple Correlation Coefficient (MCC) value and a Wafer alignment Quality (WQ) value of each segmented alignment signal. The MCC value indicates the accuracy of the alignment signal, and the larger the MCC value is, the more accurate the alignment signal is. The WQ value is an index related to the wafer alignment intensity.
And fourthly, calculating alignment points by adopting the segmented alignment signals with the best MCC value and WQ value so as to realize wafer alignment.
The method further comprises the step of judging whether the appearance of the alignment mark is damaged or not before the step one, and if the appearance of the alignment mark is damaged, carrying out wafer alignment by adopting the starting step and the steps one to four.
The further improvement is that before the first step, if the shape of the alignment mark is judged to be intact, the whole segment of alignment signal or the alignment signal at the center of the alignment mark in the first step is directly adopted for alignment.
In a further improvement, if the wafer alignment is successful in the fourth step, the wafer is exposed.
And if the wafer alignment fails, rejecting the exposure of the wafer.
In a further improvement, the alignment mark is a front layer alignment mark corresponding to a lithography layer of the wafer.
In a further refinement, the semiconductor devices formed on the wafer include power devices.
In a further improvement, the lithography layer includes a top metal layer, a passivation layer and a polyimide layer.
In a further improvement, a higher-order diffraction light enhanced subdivision structure is also arranged in the grating period of the alignment mark.
In a further refinement, the orders of the enhanced diffracted light of the alignment marks include 3 rd order, 5 th order, or 7 th order.
In a further refinement, a grating period of the grating pattern of the alignment marks comprises 16 μm or 17.6 μm.
In a further refinement, the width of the alignment marks comprises 80 μm.
In a further improvement, the alignment mark is disposed on a scribe line of the wafer.
The wafer alignment method is further improved in that steps one to four of the wafer alignment method are arranged in a first exposure process menu, and if the morphology of the alignment mark is determined to be damaged before the step one, the first exposure process menu is directly called for processing.
The further improvement is that before the first step is carried out, the method also comprises the following steps:
carrying out photomask alignment;
and carrying out coarse alignment on the wafer.
In a further improvement, the wafer alignment method is completed in an exposure machine, and in the first step, the wafer is fixed on a chuck (chuck).
Because the existing method is to calculate the alignment signal of the whole alignment mark or the alignment signal of the center of the alignment mark to realize alignment, when the alignment mark has damage, the distortion generated by the damage can make the whole alignment signal not reach the standard and reject the signal, i.e. reject the subsequent exposure, and the alignment signal of the center of the alignment mark is also easy to reject; the invention carries out segmentation processing on the whole segment alignment signal and forms each segment alignment signal, then calculates the MCC value and the WQ value of each segment signal, and selects the segment alignment signal with the best MCC value and WQ value to calculate the alignment point so as to realize wafer alignment.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1A is a photograph of alignment marks of model CT-AH 32;
FIG. 1B is a photograph of alignment marks of model CT-AH 53;
FIG. 1C is a photograph of alignment marks of model CT-AH 74;
FIG. 2A is a graph of ideal alignment signals corresponding to alignment marks of model CT-AH 53;
FIG. 2B is a graph of distortion versus position signal corresponding to FIG. 2A;
FIG. 3 is a flowchart of a wafer alignment method in a photolithography process according to an embodiment of the present invention;
FIG. 4 is a layout of alignment marks of model CT-AH53 in an embodiment of the present invention;
FIG. 5 is a graph of a segmented alignment signal in an embodiment of the present invention.
Detailed Description
FIG. 3 is a flowchart illustrating a wafer alignment method in a photolithography process according to an embodiment of the present invention; FIG. 5 is a graph of the segmented alignment signals according to the embodiment of the present invention; in the wafer alignment method in the photoetching process, the wafer is provided with the alignment mark, and the alignment mark is provided with the grating pattern. The wafer alignment method comprises the following steps:
scanning the whole section of the alignment mark by using an alignment light source, and collecting diffraction light signals corresponding to the whole section of the alignment mark to form a whole section of alignment signal 1. Only a portion of the entire bit alignment signal 1 is shown in fig. 5.
And step two, carrying out segmentation processing on the whole segment of the alignment signals 1 and forming each segment of the alignment signals. Only 3 segment alignment signals are shown in fig. 5, labeled with the labels 1a, 1b and 1c, respectively.
And step three, respectively calculating the MCC value and the WQ value of each segmented para-position signal.
Thus, instead of calculating the MCC and WQ values of the entire bit alignment signal 1, the MCC and WQ values of the entire bit alignment signal 1 may be directly rejected by the exposure tool.
And fourthly, calculating alignment points by adopting the segmented alignment signals with the best MCC value and WQ value so as to realize wafer alignment.
In the embodiment of the present invention, the segment alignment signals 1a, 1b, and 1c respectively calculate the MCC value and the WQ value, so that the wafer alignment can be realized only if the MCC value and the WQ value corresponding to one segment of the 3 segments meet the requirements. And the wafer rejection failure rate can be reduced to the maximum extent by selecting the segmented alignment signals with the best MCC value and WQ value to calculate the alignment points.
In the embodiment of the invention, before the first step, whether the appearance of the alignment mark is damaged or not is further judged, and if the appearance of the alignment mark is damaged, the starting step is adopted and the first step to the fourth step are adopted to carry out wafer alignment. Before the first step, if the shape of the alignment mark is judged to be intact, the whole section of alignment signal 1 or the alignment signal at the center of the alignment mark in the first step is directly adopted for alignment. The judging step can adopt the existing method to carry out wafer alignment under the condition that the alignment surface is in good appearance, thus improving the wafer alignment efficiency.
And if the wafer is aligned successfully in the fourth step, exposing the wafer. Preferably, the first to fourth steps of the wafer alignment method are set in a first exposure process menu, and if it is determined that the feature of the alignment mark is damaged before the first step, the first exposure process menu is directly called for processing.
And if the wafer alignment fails, rejecting the exposure of the wafer.
In the embodiment of the present invention, before performing step one, the following steps are further included:
carrying out photomask alignment;
and carrying out coarse alignment on the wafer.
The wafer alignment method is completed in an exposure machine, and in the first step, the wafer is fixed on a chuck.
In the embodiment of the invention, the alignment mark is a front layer alignment mark corresponding to the photoetching layer of the wafer.
The semiconductor devices formed on the wafer include power devices.
The photoetching layer comprises a top metal layer, a passivation layer and a polyimide layer.
And a higher-order diffraction light enhanced subdivision structure is also arranged in the grating period of the alignment mark. The orders of the enhanced diffracted light of the alignment marks include 3 rd order, 5 th order, or 7 th order. The alignment marks are now further described with reference to fig. 4:
as shown in fig. 4, the embodiment of the present invention is an alignment mark layout with a model of CT-AH 53; the alignment mark 301 is a bar structure with a length 747 μm and a width 80 μm.
The alignment mark 301 has a grating pattern, and the grating period includes a bar pattern 304; the bar-shaped pattern 304 is shown with reference to the enlarged pattern 303 at the right part of the alignment mark 301, and the corresponding dimension is also marked in the enlarged pattern 303.
As can be seen from the enlarged pattern 302 of the central area of the alignment mark 301, there are also fine structures in the bar pattern 304, specifically, 3 bars 305 and 2 spaces, which can achieve the enhancement of the light intensity of the 5 th order diffracted light
The grating period of the alignment marked grating pattern comprises 16 μm or 17.6 μm.
The alignment mark is arranged on the scribing groove of the wafer.
Because the existing method is to calculate the alignment signal of the whole alignment mark or the alignment signal of the center of the alignment mark to realize alignment, when the alignment mark has damage, the distortion caused by the damage can cause the whole alignment signal 1 not to reach the standard and reject the signal, namely reject the subsequent exposure, and the alignment signal of the center of the alignment mark is also easy to reject the signal; in the embodiment of the invention, the whole segment alignment signal 1 is segmented to form each segment alignment signal, then the MCC value and the WQ value of each segment signal are calculated, and the segment alignment signal with the best MCC value and WQ value is selected to calculate the alignment point so as to realize wafer alignment.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A wafer alignment method in a photoetching process is characterized in that an alignment mark is arranged on a wafer, a grating pattern is arranged on the alignment mark, and the wafer alignment method comprises the following steps:
scanning the whole section of the alignment mark by using an alignment light source, and collecting diffraction light signals corresponding to the whole section of the alignment mark to form a whole section of alignment signals;
step two, carrying out segmentation processing on the whole segment of alignment signals and forming each segment of alignment signals;
respectively calculating the MCC value and the WQ value of each segmented alignment signal;
and fourthly, calculating alignment points by adopting the segmented alignment signals with the best MCC value and WQ value so as to realize wafer alignment.
2. The wafer alignment method in lithography process as claimed in claim 1, wherein: before the first step, judging whether the appearance of the alignment mark is damaged, if so, carrying out wafer alignment by adopting the first step to the fourth step together with the starting step.
3. The wafer alignment method in lithography process as claimed in claim 2, wherein: before the first step, if the shape of the alignment mark is judged to be intact, the whole section of alignment signal or the alignment signal at the center of the alignment mark in the first step is directly adopted for alignment.
4. The wafer alignment method in lithography process as claimed in claim 2, wherein: if the wafer is aligned successfully in the fourth step, exposing the wafer;
and if the wafer alignment fails, refusing to carry out the exposure of the wafer.
5. The method for aligning a wafer in a photolithography process according to claim 1, 2, 3 or 4, wherein: and the alignment mark is a front layer alignment mark corresponding to the photoetching layer of the wafer.
6. The wafer alignment method in lithography process as claimed in claim 5, wherein: the semiconductor devices formed on the wafer include power devices.
7. The wafer alignment method in lithography process as claimed in claim 6, wherein: the photoetching layer comprises a top metal layer, a passivation layer and a polyimide layer.
8. The wafer alignment method in lithography process as claimed in claim 1, wherein: and a higher-order diffraction light enhanced subdivision structure is also arranged in the grating period of the alignment mark.
9. The wafer alignment method in lithography process as claimed in claim 8, wherein: the orders of the enhanced diffracted light of the alignment marks include 3 rd order, 5 th order, or 7 th order.
10. The wafer alignment method in lithography process as claimed in claim 9, wherein: the grating period of the alignment marked grating pattern comprises 16 μm or 17.6 μm.
11. The wafer alignment method in lithography process as claimed in claim 10, wherein: the width of the alignment mark comprises 80 μm.
12. The wafer alignment method in lithography process as claimed in claim 1, wherein: the alignment mark is arranged on the scribing groove of the wafer.
13. The wafer alignment method in lithography process as claimed in claim 4, wherein: the first to fourth steps of the wafer alignment method are arranged in a first exposure process menu, and if the morphology of the alignment mark is determined to be damaged before the first step, the first exposure process menu is directly called for processing.
14. The wafer alignment method in lithography process as claimed in claim 1, wherein: before the first step is carried out, the method also comprises the following steps:
carrying out photomask alignment;
and carrying out coarse alignment on the wafer.
15. The wafer alignment method in lithography process as claimed in claim 1, wherein: the wafer alignment method is completed in an exposure machine, and in the first step, the wafer is fixed on a chuck.
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CN113608410B (en) * 2021-06-17 2024-02-27 广东省大湾区集成电路与系统应用研究院 Wafer alignment mask generation method and device, computer equipment and storage medium
CN114061452A (en) * 2021-11-04 2022-02-18 中国科学院微电子研究所 Method and system for evaluating effectiveness of calculation result of ultra-precise position detection photoelectric signal

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CN102117026A (en) * 2009-12-30 2011-07-06 上海微电子装备有限公司 Method for detecting and correcting period of alignment signal of lithography tool
CN105353592A (en) * 2015-11-25 2016-02-24 武汉新芯集成电路制造有限公司 Photoetching process alignment method
CN111007703A (en) * 2019-12-18 2020-04-14 华虹半导体(无锡)有限公司 Alignment method of photoetching machine

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CN101140424A (en) * 2007-09-20 2008-03-12 上海微电子装备有限公司 Subsection interleaving aligning mark combined and aligning thereof
CN102117026A (en) * 2009-12-30 2011-07-06 上海微电子装备有限公司 Method for detecting and correcting period of alignment signal of lithography tool
CN105353592A (en) * 2015-11-25 2016-02-24 武汉新芯集成电路制造有限公司 Photoetching process alignment method
CN111007703A (en) * 2019-12-18 2020-04-14 华虹半导体(无锡)有限公司 Alignment method of photoetching machine

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