CN112630762B - Radar sensing assembly - Google Patents
Radar sensing assembly Download PDFInfo
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- CN112630762B CN112630762B CN202011357512.5A CN202011357512A CN112630762B CN 112630762 B CN112630762 B CN 112630762B CN 202011357512 A CN202011357512 A CN 202011357512A CN 112630762 B CN112630762 B CN 112630762B
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- 238000000034 method Methods 0.000 claims abstract description 11
- 238000004458 analytical method Methods 0.000 claims description 23
- 238000012300 Sequence Analysis Methods 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 238000005070 sampling Methods 0.000 claims description 10
- 238000001914 filtration Methods 0.000 claims description 7
- 230000006698 induction Effects 0.000 claims description 4
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002537 cosmetic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/35—Details of non-pulse systems
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The embodiment of the disclosure provides a radar sensing assembly, which belongs to the technical field of signal processing, and particularly comprises a tentering module, wherein the input end of the tentering module is electrically connected with a mains interface, and the tentering module carries out tentering processing on a mains signal output by the mains interface to obtain and output a tentered reference signal; the radar sensor comprises a clock circuit, a transmitting circuit and a receiving circuit; the input end of the clock circuit is electrically connected with the output end of the amplitude reduction module and is used for receiving the reference signal and providing a clock signal based on the reference signal, and the frequency of the clock signal is an integer multiple of the power frequency; the transmitting circuit is used for transmitting radio frequency signals; the receiving circuit receives the reflected radio frequency signals and processes the reflected radio frequency signals based on the clock signals to obtain sensing results. By the processing scheme, the clock precision of the radar sensor is improved.
Description
Technical Field
The disclosure relates to the technical field of signal processing, and in particular relates to a radar sensing assembly.
Background
Along with the continuous development of technology and the continuous improvement of economic level, radar sensors are not only applied to military applications, but also are beginning to be applied to a plurality of daily fields such as automobile electronics, security, unmanned aerial vehicles, intelligent transportation and the like.
In the related art, the clock accuracy of the radar sensor is low due to the influence of process deviation and temperature variation.
Disclosure of Invention
Accordingly, embodiments of the present disclosure provide a radar sensing assembly, which at least partially solves the problems in the prior art.
In a first aspect, embodiments of the present disclosure provide a radar sensing assembly comprising:
the amplitude reduction module is electrically connected with the mains supply interface at the input end of the amplitude reduction module, and is used for carrying out amplitude reduction processing on the mains supply signal output by the mains supply interface to obtain and output a reference signal after amplitude reduction;
the radar sensor comprises a clock circuit, a transmitting circuit and a receiving circuit;
the input end of the clock circuit is electrically connected with the output end of the amplitude reduction module and is used for receiving the reference signal and providing a clock signal based on the reference signal, and the frequency of the clock signal is an integer multiple of the power frequency;
the transmitting circuit is used for transmitting radio frequency signals;
the receiving circuit receives the reflected radio frequency signals and processes the reflected radio frequency signals based on the clock signals to obtain sensing results.
According to a specific implementation manner of the embodiment of the disclosure, the amplitude reduction module comprises a voltage division circuit, an input end of the voltage division circuit is electrically connected with the mains interface, and an output end of the voltage division circuit is electrically connected with an input end of the clock circuit.
According to a specific implementation manner of the embodiment of the disclosure, the voltage dividing circuit includes a first impedance and a second impedance, a first end of the first impedance is electrically connected with the mains interface, a second end of the first impedance is electrically connected with a first end of the second impedance, a second end of the second impedance is electrically connected with a ground terminal, and a first end of the second impedance is electrically connected with an input end of the clock circuit.
According to a specific implementation manner of the embodiment of the disclosure, the reference signal is a sine wave signal; the clock circuit comprises a sine wave-to-square wave circuit and a frequency doubling circuit;
the input end of the sine wave-to-square wave circuit is electrically connected with the output end of the amplitude reduction module, and the sine wave-to-square wave circuit receives the reference signal and converts the reference signal into a square wave signal;
the input end of the frequency doubling circuit is electrically connected with the output end of the sine wave-to-square wave circuit, and the frequency doubling circuit receives the square wave signal and converts the square wave signal into the clock signal.
According to a specific implementation of an embodiment of the disclosure, the receiving circuit includes a radio frequency receiver, a modulation circuit, and a timing analysis circuit;
the radio frequency receiver receives and outputs the reflected radio frequency signals;
the input end of the modulation circuit is electrically connected with the output end of the radio frequency receiver, and the modulation circuit converts the reflected radio frequency signal to obtain a zero intermediate frequency signal;
the input end of the time sequence analysis circuit is electrically connected with the output end of the modulation circuit, the clock end of the time sequence analysis circuit is electrically connected with the clock circuit, and the time sequence analysis circuit obtains an induction result based on the zero intermediate frequency signal and the clock signal.
According to a specific implementation of an embodiment of the disclosure, the timing analysis circuit is a digital circuit; the receiving circuit further comprises an analog-to-digital conversion circuit, a clock end of the analog-to-digital conversion circuit is electrically connected with the clock circuit, an input end of the analog-to-digital conversion circuit is electrically connected with an output end of the modulation circuit, and an output end of the analog-to-digital conversion circuit is electrically connected with an input end of the time sequence analysis circuit.
According to a specific implementation of an embodiment of the disclosure, the receiving circuit further includes a filtering circuit;
the input end of the filter circuit is electrically connected with the output end of the modulation circuit, and the filter circuit filters the power frequency and the frequency multiplication thereof in the zero intermediate frequency signal to obtain a signal to be analyzed;
the input end of the time sequence analysis circuit is electrically connected with the output end of the filter circuit, and the time sequence analysis circuit obtains an induction result based on the signal to be analyzed and the clock signal.
According to a specific implementation of an embodiment of the disclosure, the filtering circuit includes a vanity downsampling filter;
the input end of the dressing down-sampling filter is electrically connected with the output end of the modulation circuit, and the output end of the dressing down-sampling filter is electrically connected with the input end of the time sequence analysis circuit.
According to a specific implementation of an embodiment of the disclosure, the filtering circuit further includes a digital trap;
the input end of the digital trap is electrically connected with the output end of the dressing down-sampling filter, and the output end of the digital trap is electrically connected with the input end of the time sequence analysis circuit.
According to a specific implementation manner of the embodiment of the disclosure, the modulation circuit includes a mixer, an input end of the mixer is electrically connected with an output end of the radio frequency receiver, and an output end of the mixer is electrically connected with an input end of the timing analysis circuit.
In the embodiment of the disclosure, a reference voltage is obtained by performing amplitude reduction processing on the commercial electric signal through an amplitude reduction module, a clock circuit obtains a clock signal based on the reference signal and provides the clock signal to a receiving circuit, and the frequency of the clock signal is an integer multiple of power frequency; in this way, the clock accuracy of the radar sensor can be ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a related art radar sensor;
FIG. 2 is a schematic diagram of a radar sensor assembly according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a radar sensing assembly according to another embodiment of the present invention.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
In the related art, as shown in fig. 1, a chip clock of a radar sensor is generated by a resistor-capacitor oscillator 110, and the accuracy of the chip clock is low due to the influence of process deviation and temperature variation.
An embodiment of the present disclosure provides a radar sensing assembly, as shown in fig. 2, including:
the amplitude reduction module 210, wherein the input end of the amplitude reduction module 210 is electrically connected with a mains supply interface, the amplitude reduction module 210 performs amplitude reduction processing on the mains supply signal output by the mains supply interface to obtain and output a reference signal after amplitude reduction;
a radar sensor 220 including a clock circuit 221, a transmitting circuit 222, and a receiving circuit 223;
the input end of the clock circuit 221 is electrically connected to the output end of the amplitude reduction module 210, and is configured to receive the reference signal and provide a clock signal based on the reference signal, where the frequency of the clock signal is an integer multiple of the power frequency;
the transmitting circuit 222 is configured to transmit a radio frequency signal;
the receiving circuit 223 receives the reflected rf signal, and processes the reflected rf signal based on the clock signal to obtain a sensing result.
In the embodiment of the disclosure, the amplitude reduction module 210 performs amplitude reduction processing on the commercial electric signal to obtain a reference voltage, and the clock circuit 221 obtains a clock signal based on the reference signal and provides the clock signal to the receiving circuit 223, wherein the frequency of the clock signal is an integer multiple of the power frequency; in this way, the clock accuracy of the radar sensor 220 can be ensured.
Each functional device in the radar sensor 220 may be driven by an operating voltage, which may be obtained by performing ac-dc conversion and voltage stabilization processing on an electric mains signal.
After the amplitude reduction module 210 receives the commercial power, the amplitude of the commercial power can be reduced by the amplitude reduction process, so as to obtain the reference signal after the amplitude reduction. The amplitude reduction module 210 may be a device capable of changing the waveform amplitude, such as an amplitude regulator and a voltage divider, and is not limited herein.
The reference signal may have an amplitude smaller than the amplitude of the commercial signal, and other parameters may be consistent with the parameters of the commercial signal.
The radar sensor 220 may be a microwave radar sensor chip, a millimeter wave radar sensor chip, a radio frequency radar sensor chip, or the like. The radar sensor 220 transmits a radio frequency signal through the transmitting circuit 222, and the receiving circuit 223 receives the radio frequency signal returned after the radio frequency signal is reflected by each object in the detection environment, so as to obtain the sensing result of the detection environment.
The input end of the clock circuit 221 is electrically connected to the output end of the amplitude reduction module 210, and is configured to receive the reference signal and obtain a clock signal based on the reference signal, where the frequency of the clock signal is an integer multiple of a power frequency, and the power frequency is the frequency of the commercial power signal. The clock signal may be obtained by performing a series of waveform processing on the reference signal, and specifically may be a sine wave-to-square wave, pulse width modulation, or other manners, which are not limited herein.
By using the clock circuit 221 as the clock of the receiving circuit 223 in the radar sensor 200, the clock accuracy of the radar sensor 220 is ensured, and the clock of the radar sensor 220 and the frequency of the commercial electric signal can have an integer relation. In this way, compared with the situation that the clock of the radar sensor 220 has no integer relation with the frequency of the commercial power signal, the method can greatly reduce the resources of the filter required by the receiving circuit 223 to filter the commercial power interference of the commercial power signal, and reduce the cost of the radar sensor 220; meanwhile, loss of signal bandwidth caused by the use of the filter can be reduced.
Further, the amplitude reduction module 210 includes a voltage division circuit, an input end of the voltage division circuit is electrically connected to the mains interface, and an output end of the voltage division circuit is electrically connected to an input end of the clock circuit 221.
In this embodiment, the voltage division circuit divides the commercial power signal to obtain the reference signal with the same frequency as the commercial power signal but a lower voltage, wherein the amplitude of the reference signal can be adjusted by the configuration of the voltage division circuit.
Specifically, as shown in fig. 3, the voltage divider circuit may include a first impedance R1 and a second impedance R2, where a first end of the first impedance R1 is electrically connected to the mains interface, a second end of the first impedance R1 is electrically connected to a first end of the second impedance R2, a second end of the second impedance R2 is electrically connected to the ground GND, and a first end of the second impedance R2 is electrically connected to an input end of the clock circuit 221.
Thus, the reference signal which has the same frequency as the mains voltage and has a voltage amplitude smaller than the mains voltage amplitude can be obtained at the second end of the first impedance R1 or the first end of the second impedance R2. The amplitude of the reference signal may be changed by changing the magnitude relation between the first impedance R1 and the second impedance R2, taking the first impedance and the second impedance as resistors as examples: voltage value of reference signal=r2/(r1+r2).
Further, the reference signal is a sine wave signal; the clock circuit 221 includes a sine wave-to-square wave circuit 2211 and a frequency doubling circuit 2212;
the input end of the sine wave-to-square wave circuit 2211 is electrically connected with the output end of the amplitude reduction module 210, and the sine wave-to-square wave circuit 2211 receives the reference signal and converts the reference signal into a square wave signal;
the input end of the frequency doubling circuit 2212 is electrically connected to the output end of the sine wave to square wave circuit 2211, and the frequency doubling circuit 2212 receives the square wave signal and converts the square wave signal into the clock signal.
In this embodiment, the sine wave-to-square wave circuit 2211 converts the sine wave signal into a square wave signal with the same frequency. Specifically, when the reference signal is a 50Hz sine wave signal, the sine wave to square wave circuit 2211 receives the reference signal and outputs a 50Hz square wave signal.
The frequency doubling circuit 2212 is used for doubling the square wave signal to a suitable frequency. In particular, the frequency doubling circuit 2212 may be a phase-locked loop or a frequency-locked loop. The clock signal obtained by multiplying the frequency of the square wave signal by the frequency multiplier circuit 2212 may be used as the clock of the receiving circuit 223.
The Phase-Locked Loop (PLL) is a feedback control circuit, and uses an externally input reference signal to control the frequency and Phase of an oscillation signal inside the Loop. In the working process of the phase-locked loop, when the frequency of the output signal is equal to the frequency of the input signal, the phase difference value between the output voltage and the input voltage is kept fixed, namely the phases of the output voltage and the input voltage are locked.
The frequency locked loop is an automatic control loop, and is an automatic frequency trimming circuit for dynamic application, and the locking process can allow a voltage-controlled oscillator (VCO-controlled oscillator) to have small steady-state frequency error with a synchronous signal.
Further, as shown in fig. 2, the receiving circuit 223 includes a radio frequency receiver 2231, a modulating circuit 2232, and a timing analysis circuit 2233;
the rf receiver 2231 receives and outputs a reflected rf signal;
an input end of the modulation circuit 2232 is electrically connected to an output end of the radio frequency receiver 2231, and the modulation circuit 2232 converts the reflected radio frequency signal to obtain a zero intermediate frequency signal;
an input terminal of the timing analysis circuit 2233 is electrically connected to an output terminal of the modulation circuit 2232, a clock terminal of the timing analysis circuit 2233 is electrically connected to the clock circuit 221, and the timing analysis circuit obtains a sensing result based on the zero intermediate frequency signal and the clock signal.
The transmitting circuit 222 transmits radio frequency signals to detect objects in a detection environment. The radio frequency signal is a high-frequency alternating current variable electromagnetic wave, and the electromagnetic frequency range which can be radiated to the space is between 300KHz and 300 GHz. In particular, the transmit circuit 222 may include a radio frequency transmitter that resonates through an antenna to a detection space.
The rf receiver 2231 receives rf signals reflected back in the detection space through an antenna. The modulation circuit 2232 directly converts the rf signal received by the rf receiver 2231 into a baseband without intermediate frequency modulation and demodulation, thereby obtaining a zero intermediate frequency signal. The timing analysis circuit 2233 performs time domain analysis based on the zero intermediate frequency signal and the clock signal, thereby obtaining a sensing result.
Further, as shown in fig. 2, the timing analysis circuit 2233 is a digital circuit; the receiving circuit 223 further includes an analog-to-digital conversion circuit 2234, a clock terminal of the analog-to-digital conversion circuit 2234 is electrically connected to an output terminal of the clock circuit 221, an input terminal of the analog-to-digital conversion circuit 2234 is electrically connected to an output terminal of the modulation circuit 2232, and an output terminal of the analog-to-digital conversion circuit 2234 is electrically connected to an input terminal of the timing analysis circuit 2233.
The analog-to-digital conversion circuit 2234 converts the zero intermediate frequency signal, which is originally an analog signal, into a digital signal based on the clock signal, so that the timing analysis circuit 2233 can perform time-domain analysis based on the zero intermediate frequency signal smoothly.
Further, as shown in fig. 2, the receiving circuit 223 further includes a filtering circuit 2235;
the input end of the filter circuit 2235 is electrically connected with the output end of the modulation circuit 2232, and the filter circuit 2235 filters the power frequency and the frequency multiplication thereof in the zero intermediate frequency signal to obtain a signal to be analyzed;
an input terminal of the timing analysis circuit 2233 is electrically connected to an output terminal of the filter circuit 2235, and the timing analysis circuit 2233 obtains a sensing result based on the signal to be analyzed and the clock signal.
In this embodiment, before the time-domain analysis of the zero intermediate frequency signal by the time-sequence analysis circuit 2233, the power frequency and the frequency multiplication thereof in the zero intermediate frequency signal are filtered by the filter circuit, so that the influence of the power frequency and the frequency multiplication of the commercial power signal on the time-sequence analysis can be reduced, and the sensing accuracy of the radar sensor is improved.
Wherein, as shown in fig. 3, the filter circuit 2235 includes a comb downsampling filter 22351;
an input of the dressing-down-sampling filter 22351 is electrically connected to an output of the modulation circuit 2232, and an output of the dressing-down-sampling filter 22351 is electrically connected to an input of the timing analysis circuit 2233.
The dressing-down sampling filter 22351 is configured to reduce the signal sampling rate, reduce the processing difficulty of the zero intermediate frequency signal by the timing analysis circuit 2233, and ensure the rapidity of the sensing result obtained by the radar sensor.
In addition, as shown in fig. 3, the filter circuit 2235 may also include a digital trap 22352;
an input of the digital trap 22352 is electrically connected to an output of the cosmetic downsampling filter 22351, and an output of the digital trap 22352 is electrically connected to an input of the timing analysis circuit 2233.
The digital wave trap 22352 can rapidly attenuate an input signal at a certain frequency point to achieve the purpose of filtering clutter in zero intermediate frequency signals in a mode of blocking the frequency signal from passing, so that influence of clutter on time sequence analysis is eliminated, and the sensing accuracy of the radar sensor is improved.
Further, the modulation circuit 2232 includes a mixer, an input terminal of which is electrically connected to an output terminal of the radio frequency receiver, and an output terminal of which is electrically connected to an input terminal of the timing analysis circuit 2233.
In this embodiment, an input end of the mixer is electrically connected to an output end of the radio frequency receiver, and an input signal thereof is a radio frequency signal; the input signal received by the other input end of the mixer is a baseband signal, and the mixer directly obtains a zero intermediate frequency signal by mixing the reflected radio frequency signal with the baseband signal.
Of course, in other embodiments of the present disclosure, modulation circuit 2232 may also convert the reflected radio frequency signal to a zero intermediate frequency signal in other ways, without limitation.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A radar sensing assembly, comprising:
the amplitude reduction module is electrically connected with the mains supply interface at the input end of the amplitude reduction module, and is used for carrying out amplitude reduction processing on the mains supply signal output by the mains supply interface to obtain and output a reference signal after amplitude reduction;
the radar sensor comprises a clock circuit, a transmitting circuit and a receiving circuit;
the input end of the clock circuit is electrically connected with the output end of the amplitude reduction module and is used for receiving the reference signal and providing a clock signal based on the reference signal, and the frequency of the clock signal is an integer multiple of the power frequency;
the reference signal is a sine wave signal; the clock circuit comprises a sine wave-to-square wave circuit and a frequency doubling circuit;
the input end of the sine wave-to-square wave circuit is electrically connected with the output end of the amplitude reduction module, and the sine wave-to-square wave circuit receives the reference signal and converts the reference signal into a square wave signal;
the input end of the frequency doubling circuit is electrically connected with the output end of the sine wave-to-square wave circuit, and the frequency doubling circuit receives the square wave signal and converts the square wave signal into the clock signal;
the transmitting circuit is used for transmitting radio frequency signals;
the receiving circuit receives the reflected radio frequency signals and processes the reflected radio frequency signals based on the clock signals to obtain sensing results.
2. The radar sensing assembly of claim 1, wherein the amplitude reduction module comprises a voltage divider circuit, an input of the voltage divider circuit is electrically connected to the mains interface, and an output of the voltage divider circuit is electrically connected to an input of the clock circuit.
3. The radar sensing assembly of claim 2, wherein the voltage divider circuit comprises a first impedance and a second impedance, a first end of the first impedance being electrically connected to the mains interface, a second end of the first impedance being electrically connected to a first end of the second impedance, a second end of the second impedance being electrically connected to ground, and a first end of the second impedance being electrically connected to an input of the clock circuit.
4. The radar sensing assembly of claim 1, wherein the receive circuit comprises a radio frequency receiver, a modulation circuit, and a timing analysis circuit;
the radio frequency receiver receives and outputs the reflected radio frequency signals;
the input end of the modulation circuit is electrically connected with the output end of the radio frequency receiver, and the modulation circuit converts the reflected radio frequency signal to obtain a zero intermediate frequency signal;
the input end of the time sequence analysis circuit is electrically connected with the output end of the modulation circuit, the clock end of the time sequence analysis circuit is electrically connected with the output end of the clock circuit, and the time sequence analysis circuit obtains an induction result based on the zero intermediate frequency signal and the clock signal.
5. The radar sensing assembly of claim 4, wherein the timing analysis circuit is a digital circuit; the receiving circuit further comprises an analog-to-digital conversion circuit, a clock end of the analog-to-digital conversion circuit is electrically connected with an output end of the clock circuit, an input end of the analog-to-digital conversion circuit is electrically connected with an output end of the modulation circuit, and an output end of the analog-to-digital conversion circuit is electrically connected with an input end of the time sequence analysis circuit.
6. The radar sensing assembly of claim 4, wherein the receive circuit further comprises a filter circuit;
the input end of the filter circuit is electrically connected with the output end of the modulation circuit, and the filter circuit filters the power frequency and the frequency multiplication thereof in the zero intermediate frequency signal to obtain a signal to be analyzed;
the input end of the time sequence analysis circuit is electrically connected with the output end of the filter circuit, and the time sequence analysis circuit obtains an induction result based on the signal to be analyzed and the clock signal.
7. The radar sensing assembly of claim 6, wherein the filtering circuit includes a vanity downsampling filter;
the input end of the dressing down-sampling filter is electrically connected with the output end of the modulation circuit, and the output end of the dressing down-sampling filter is electrically connected with the input end of the time sequence analysis circuit.
8. The radar sensing assembly of claim 7, wherein the filtering circuit further comprises a digital trap;
the input end of the digital trap is electrically connected with the output end of the dressing down-sampling filter, and the output end of the digital trap is electrically connected with the input end of the time sequence analysis circuit.
9. The radar sensing assembly of claim 4, wherein the modulation circuit comprises a mixer, an input of the mixer being electrically connected to an output of the radio frequency receiver, an output of the mixer being electrically connected to an input of the timing analysis circuit.
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| CN202011357512.5A CN112630762B (en) | 2020-11-27 | 2020-11-27 | Radar sensing assembly |
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| CN202011357512.5A CN112630762B (en) | 2020-11-27 | 2020-11-27 | Radar sensing assembly |
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| CN112630762A CN112630762A (en) | 2021-04-09 |
| CN112630762B true CN112630762B (en) | 2024-03-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102457467B1 (en) * | 2017-12-12 | 2022-10-21 | 한국전자통신연구원 | Radar device |
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| FR1423950A (en) * | 1964-11-26 | 1966-01-07 | Automatisme Ind L | Clock with power reserve, in particular for time switches and time switches comprising such a clock |
| CN2541911Y (en) * | 2002-05-18 | 2003-03-26 | 宁静 | Multifunctional radar anti-theft warner |
| CN208175049U (en) * | 2018-05-03 | 2018-11-30 | 新和（绍兴）绿色照明有限公司 | A kind of linear constant current LED light with radar inducing function |
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