CN112614833A - Groove type capacitor device and preparation method thereof - Google Patents
Groove type capacitor device and preparation method thereof Download PDFInfo
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- CN112614833A CN112614833A CN202011504842.2A CN202011504842A CN112614833A CN 112614833 A CN112614833 A CN 112614833A CN 202011504842 A CN202011504842 A CN 202011504842A CN 112614833 A CN112614833 A CN 112614833A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 112
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims abstract description 51
- 230000000149 penetrating effect Effects 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 16
- 238000011049 filling Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 338
- 238000000034 method Methods 0.000 claims description 83
- 230000008569 process Effects 0.000 claims description 75
- 239000011241 protective layer Substances 0.000 claims description 43
- 238000002955 isolation Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 150000002736 metal compounds Chemical class 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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Abstract
The invention provides a preparation method of a groove-type capacitor device, which comprises a plurality of first grooves and a capacitor structure which is positioned on a first dielectric layer and fills the first grooves, wherein the first grooves penetrate through the first dielectric layer and are terminated at a first metal interconnection layer; a second trench penetrating the first dielectric layer and terminating at a second metal interconnect layer; an electrode interconnect layer on the capacitive structure; the capacitor structure is provided with an opening and a second dielectric layer positioned on the upper electrode layer, wherein the opening penetrates through the second dielectric layer and is terminated at the upper electrode layer; the electrode interconnection layer is located on the second dielectric layer, fills the opening and the second trench, and is electrically connected with the upper electrode layer and the second metal interconnection layer. The invention does not need extra BARC filling and reverse etching, and does not need to carry out independent photoetching and etching on the lower electrode layer, thereby having remarkable significance.
Description
Technical Field
The invention relates to the field of semiconductor passive device manufacturing, in particular to a trench capacitor device and a preparation method thereof.
Background
The capacitor is a passive device for energy storage, and is widely applied to semiconductor circuits such as coupling, filtering, resonance, integration and compensation. The number of photoetching layers of the trench capacitor device in the prior art is more than that of a flat plate capacitor, so that the manufacturing process cost is increased, and fig. 1 shows the process flow of the trench capacitor device in the prior art, which comprises 5 times of photoetching of a capacitor trench, photoetching of a lower electrode plate, photoetching of a capacitor dielectric layer/an upper electrode plate, photoetching of a capacitor through hole and photoetching of interconnection metal. And before the lower plate is photoetched, coating and back etching of a bottom anti-reflection layer (BARC) are required to be carried out in the capacitor groove, namely, the photoetching of the lower electrode layer can be carried out after the planarization is finished.
Fig. 2 is a cross-sectional view of a trench capacitor device after a lower electrode layer is etched in the prior art, a dry or wet photoresist removing process is usually used to remove BARC and photoresist filled in a trench, and plasma is likely to cause plasma damage to the lower electrode layer during the dry process. In addition, in order to increase the capacitance per unit area, the depth of the trench capacitor device is increased while the trench opening is reduced, so that the BARC and the photoresist in the trench are difficult to remove, BARC residues and photoresist residues in the trench are easy to form, and the reliability and the yield of the trench capacitor device are influenced finally.
Therefore, there is a need to find a method for fabricating a trench capacitor device with a small number of photolithography layers without the need for BARC fill and removal.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art, and a first aspect of the present invention provides a trench capacitor device, including:
the circuit comprises a substrate, a first circuit area and a second circuit area, wherein the substrate is provided with the first circuit area and the second circuit area;
the circuit comprises an isolation medium structure positioned on the surface of the substrate and a metal interconnection layer positioned in the isolation medium structure, wherein the metal interconnection layer comprises a first metal interconnection layer and a second metal interconnection layer, the first metal interconnection layer is electrically connected with the first circuit area, and the second metal interconnection layer is electrically connected with the second circuit area;
the first dielectric layer is positioned on the surface of the isolation dielectric structure;
the groove capacitor area is positioned on the first metal interconnection layer and comprises a plurality of first grooves and a capacitor structure which is positioned on the first dielectric layer and fills the first grooves, and the first grooves penetrate through the first dielectric layer and are terminated at the first metal interconnection layer;
a second trench extending through the first dielectric layer and terminating at the second metal interconnect layer;
an electrode interconnect layer on the capacitive structure; wherein,
the capacitor structure is provided with an opening and comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, wherein the lower electrode layer is positioned on the surface of the first dielectric layer and covers the bottom and the side wall of the first groove, the capacitor dielectric layer is positioned on the surface of the lower electrode layer, the upper electrode layer is positioned on the surface of the capacitor dielectric layer and fills the first groove, and the lower electrode layer is electrically connected with the first metal interconnection layer; a second dielectric layer on the upper electrode layer, the opening penetrating the second dielectric layer and terminating at the upper electrode layer; the electrode interconnection layer is located on the second dielectric layer, fills the opening and the second trench, and is electrically connected with the upper electrode layer and the second metal interconnection layer.
Preferably, the opening penetrates through the second dielectric layer and extends into the upper electrode layer.
Preferably, the capacitor structure further comprises a protective layer located on the surface of the second dielectric layer, the protective layer further extends to cover the surface of the sidewall of the capacitor structure located on the first dielectric layer, the opening penetrates through the protective layer, and the electrode interconnection layer covers a part of the surface of the protective layer.
Preferably, the first circuit region includes a first transistor, the second circuit region includes a second transistor, the first metal interconnection layer is electrically connected to the first circuit region through a first through hole in the isolation dielectric structure, and the second metal interconnection layer is electrically connected to the second circuit region through a second through hole in the isolation dielectric structure.
The second aspect of the present invention provides a method for manufacturing a trench capacitor device, including:
forming a first circuit area and a second circuit area on a substrate by adopting a front manufacturing process, and then forming an isolation medium structure and a metal interconnection layer positioned in the isolation medium structure on the surface of the substrate by adopting a rear manufacturing process, wherein the metal interconnection layer comprises a first metal interconnection layer electrically connected with the first circuit area and a second metal interconnection layer electrically connected with the second circuit area;
forming a first dielectric layer on the surface of the isolation dielectric structure;
forming a first groove penetrating through the first dielectric layer;
depositing a lower electrode layer, a capacitance dielectric layer and an upper electrode layer on the first dielectric layer and on the side wall and the surface of the first groove in sequence, wherein the upper electrode layer fills the first groove;
depositing a second dielectric layer on the upper electrode layer;
coating photoresist on the second dielectric layer, and defining a capacitor pattern through a photoetching process;
etching the second dielectric layer, the upper electrode layer, the capacitor dielectric layer and the lower electrode layer by taking the capacitor pattern as a mask;
removing the photoresist on the second dielectric layer, and forming an initial capacitor structure on the first circuit region;
forming a protective layer on the first dielectric layer and the initial capacitor structure;
coating photoresist on the protective layer, and defining an opening pattern and a second groove pattern through a photoetching process;
etching the protective layer and the first dielectric layer by taking the opening pattern and the second groove pattern as masks to form a capacitor structure with an opening and a second groove;
removing the photoresist on the protective layer;
forming an electrode interconnection layer filling the opening and the second trench on the protective layer.
Preferably, the material of the second dielectric layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide and nitrogen-containing silicon carbide; the material of the lower electrode layer and the upper electrode layer comprises a metal compound and a metal material, wherein the metal compound comprises one or two of titanium nitride and tantalum nitride; the metal material comprises one or more of aluminum, tungsten and copper; the capacitor dielectric layer is made of one or more of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide and aluminum oxide; the material of the protective layer comprises one or more of silicon dioxide, silicon oxynitride and silicon nitride.
Preferably, the thickness ratio between the first dielectric layer and the second dielectric layer is equal to the etching rate ratio.
Preferably, the thickness of the first dielectric layer is 800nm, and the thickness of the second dielectric layer is 100 nm; the etching rate ratio of the first dielectric layer to the second dielectric layer is 8: 1.
Preferably, the process of forming the opening and the second trench includes: etching the protective layer by using the opening pattern and the second groove pattern as masks and adopting a first etching process to form an initial opening and an initial second groove which penetrate through the protective layer; and etching the second dielectric layer at the bottom of the initial opening and the first dielectric layer at the bottom of the initial second groove by adopting a second etching process to form an opening penetrating through the second dielectric layer and a second groove penetrating through the first dielectric layer.
Preferably, the first etching process and the second etching process include a dry etching process.
The invention does not need extra BARC filling and reverse etching, and does not need to carry out independent photoetching and etching on the lower electrode layer, thereby avoiding the plasma damage of the lower electrode layer in the BARC removing process and simultaneously preventing the residue of the BARC in the first groove. In addition, the protective layer is formed on the side wall of the capacitor structure, so that short circuit of the upper electrode layer and the lower electrode layer is further prevented, the purpose of improving the performance and the reliability of the device is achieved, and the capacitor structure has obvious significance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a process flow of a prior art trench capacitor device
FIG. 2 is a cross-sectional view of a trench capacitor device after completion of lower electrode layer photolithography in accordance with the prior art
FIG. 3 is a schematic diagram of a trench capacitor device according to a preferred embodiment of the present invention
FIGS. 4 to 15 are schematic structural diagrams illustrating a manufacturing process of a trench capacitor device according to a preferred embodiment of the invention
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, referring to fig. 3, fig. 3 is a schematic structural diagram of a trench capacitor device according to a preferred embodiment of the present invention, including:
the substrate 100 is provided with a first circuit area and a second circuit area, and the substrate 100 is further provided with an isolation area which isolates the first circuit area from the second circuit area. The semiconductor device includes an isolation dielectric structure 110 on a surface of the substrate 100 and metal interconnection layers in the isolation dielectric structure 110, where the metal interconnection layers include a first metal interconnection layer 111 and a second metal interconnection layer 112, the first metal interconnection layer 111 is electrically connected to the first circuit region, and the second metal interconnection layer 112 is electrically connected to the second circuit region, in this embodiment, the first circuit region includes a first transistor 101, the second circuit region includes a second transistor 102, the first metal interconnection layer 111 is electrically connected to the first transistor 101 through a first via hole in the isolation dielectric structure 110, and the second metal interconnection layer 112 is electrically connected to the second transistor 102 through a second via hole in the isolation dielectric structure 110. In this embodiment, the surface of the isolation dielectric structure 110, the surface of the first metal interconnection layer 111, and the surface of the second metal interconnection layer 112 are flush. A first dielectric layer 120 located on the surface of the isolation dielectric structure 110, wherein the first dielectric layer 120 covers the first metal interconnection layer 111, the second metal interconnection layer 112 and the surface of the isolation dielectric structure 110; the trench capacitor area on the first circuit area includes a plurality of first trenches penetrating through the first dielectric layer 120 and a capacitor structure 150 on the first dielectric layer 120 and filling the first trenches, where the first trenches terminate on the surface of the first metal interconnection layer 111 or within the first metal interconnection layer 111.
The capacitor structure 150 includes a lower electrode layer located on the surface of the first dielectric layer 120 and covering the bottom and the sidewall of the first trench, a capacitor dielectric layer located on the surface of the lower electrode layer, and an upper electrode layer located on the surface of the capacitor dielectric layer, where the upper electrode layer fills the first trench, and the lower electrode layer is electrically connected to the first circuit region; the capacitor structure further comprises a second dielectric layer positioned on the upper electrode layer, wherein the second dielectric layer is provided with an opening, the bottom of the opening exposes part of the upper electrode layer, and the opening penetrates through the second dielectric layer and is terminated on the surface of the upper electrode layer or in the upper electrode layer; a second trench on the second circuit region, the second trench penetrating through the first dielectric layer 120 and terminating at a surface of the second metal interconnect layer 112 or within the second metal interconnect layer 112; an electrode interconnect layer 160 on the capacitor structure 150, the electrode interconnect layer 160 filling the second trench and filling the opening, the electrode interconnect layer 160 connecting the upper electrode layer and the second metal interconnect layer 112, the capacitor structure electrically connecting the second circuit region through the electrode interconnect layer 160. The total thickness of the lower electrode layer, the capacitor dielectric layer and the upper electrode layer included in the capacitor structure 150 of the invention is enough to fill the first trench, therefore, extra BARC is not needed to fill the first trench and the etching back process is not needed, the damage of plasma to the lower electrode layer in the BARC removing process in the prior art is avoided, and the reduction of capacitor reliability and yield caused by the residue of the BARC in the first trench is also avoided; meanwhile, the lower electrode layer, the capacitor dielectric layer and the upper electrode layer are etched simultaneously, so that the process steps are simplified.
The trench capacitor device of the present invention may further include a protection layer 131 located on the surface of the second dielectric layer, wherein the protection layer 131 further extends to cover the sidewall surface of the capacitor structure located on the first dielectric layer 120, and the opening penetrates through the protection layer; the electrode interconnection layer 160 covers a portion of the surface of the protective layer 131, and electrically connects the upper electrode layer and the second metal interconnection layer 112 across the protective layer 131. By covering the sidewall of the capacitor structure 150 with the protection layer 131, a short circuit between the upper electrode layer and the lower electrode layer of the capacitor structure 150 is prevented.
In order to make the objects, technical solutions and advantages of the present invention more clear, the following further shows a schematic structural diagram of a manufacturing process of a trench capacitor device according to an embodiment of the present invention with reference to fig. 4 to fig. 15.
Firstly, a first circuit area and a second circuit area are formed on a substrate 100 by adopting a front-end manufacturing process, and then an isolation medium structure 110 and a metal interconnection layer positioned in the isolation medium structure 110 are formed on the surface of the substrate 100 by adopting a rear-end manufacturing process, wherein the metal interconnection layer comprises a first metal interconnection layer 111 electrically connected with the first circuit area and a second metal interconnection layer 112 electrically connected with the second circuit area.
As shown in fig. 4, a substrate 100 is provided, the substrate 100 includes one of an N-type or P-type silicon substrate, a first transistor and a second transistor are respectively formed on the substrate 100 by depositing, photolithography and etching a polysilicon material on the substrate 100 by using a previous manufacturing process, and then an isolation dielectric structure 110 is deposited on the substrate 100, where the isolation dielectric structure 110 may be a multi-layer ONO stack, a multi-layer OSiO stack, an oxide or a nitride.
Then, a first metal interconnection layer 111 and a second metal interconnection layer 112 are respectively formed in the isolation dielectric structure 110, the first metal interconnection layer 111 electrically connects the first transistor, and the second metal interconnection layer 112 electrically connects the second transistor. The formation processes of the isolation dielectric structure 110, the first metal interconnection layer 111, and the second metal interconnection layer 112 are conventional processes in the art, and are not described herein.
As shown in fig. 5, a first dielectric layer 120 is formed on the surface of the isolation dielectric structure 110.
The forming process of the first dielectric layer 120 includes one of a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, or an epitaxial growth process.
Next, a first trench penetrating the first dielectric layer 120 is formed.
Referring to fig. 6, in the present embodiment, a photoresist layer is coated on the first dielectric layer 120, the photoresist layer is patterned by a photolithography process, the patterned photoresist layer is used as a mask, the first dielectric layer 120 is etched to form a first trench, and then the photoresist layer is removed. In this embodiment, in order to further reduce the area of a capacitor structure to be formed later and increase the capacitance value per unit area, the cross section of the first trench is preferably a long strip with four straight sides. As an alternative embodiment of the present invention, the four sides of the strip may also be curved or broken lines, which can achieve the purpose of the present invention and belong to the protection scope of the present invention. In at least one embodiment, a rounded first trench layout is used that eliminates sharp corners, and the first trenches have a width of about 0.5 μm to 3 μm, and are spaced apart by about 0.3 μm to 1.5 μm. The depth of the first trench, which may extend through the first dielectric layer 120 and terminate at the surface of the first metal interconnect layer 111 or within the first metal interconnect layer 111, may be deeper or shallower as required by the application and is suitable for the parameters of the process into which the capacitor is integrated.
Referring to fig. 7, then, a lower electrode layer 121, a capacitor dielectric layer 122 and an upper electrode layer 123 are sequentially deposited on the first dielectric layer 120 and the sidewall and the surface of the first trench, and the upper electrode layer 123 fills the first trench; thereafter, a second dielectric layer 124 is deposited on the upper electrode layer 123.
The material of the lower electrode layer 121 and the upper electrode layer 123 comprises a metal compound and a metal material, wherein the metal compound comprises one or two of titanium nitride and tantalum nitride; the metal material comprises one or more of aluminum, tungsten and copper. The material of the lower electrode layer 121 and the material of the upper electrode layer 123 may be the same or different, and are determined by the process conditions, and are not limited herein. The material of the capacitor dielectric layer 122 includes one or more of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, and aluminum oxide. The capacitor dielectric layer 122 may be an oxide-nitride-oxide (ONO) layer stack or a multi-layer OSiO stack. The forming process of the capacitor dielectric layer 122 includes one or more of atomic layer deposition process, chemical vapor deposition process (CVD), and physical vapor deposition Process (PVD). In order to ensure the deposition uniformity of the sidewalls and bottom of the first trench, the formation process of the lower electrode layer 121 and the upper electrode layer 123 is preferably an atomic layer deposition process, and the deposition process of the capacitor dielectric layer 122 is preferably a Chemical Vapor Deposition (CVD) process. The material of the second dielectric layer 124 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and nitrogen-containing silicon carbide, and the deposition process of the second dielectric layer 124 includes one of LPCVD, RTCVD, and ALD. The thickness ratio between the first dielectric layer 120 and the second dielectric layer 124 is equal to or close to the etching rate ratio, in this embodiment, the thickness ratio between the first dielectric layer 120 and the second dielectric layer 124 is equal to the etching rate ratio, for example, the etching rate ratio between the first dielectric layer 120 and the second dielectric layer 124 is 8:1, the thickness of the first dielectric layer 120 is 800nm, and the thickness of the second dielectric layer 124 is 100 nm. The total thickness of the lower electrode layer 121, the capacitor dielectric layer 122 and the upper electrode layer 123 in this embodiment is sufficient to fill the first trench, so that additional BARC filling and etch-back processes are not required, damage of plasma to the lower electrode layer in the BARC removing process in the prior art is avoided, and reduction of capacitor reliability and yield caused by residual BARC in the first trench is also avoided.
As shown in fig. 8, a photoresist is then coated on the second dielectric layer 124, and a capacitor pattern 125 is defined through a photolithography process.
In this embodiment, the lower electrode layer 121, the capacitor dielectric layer 122, the upper electrode layer 123 and the second dielectric layer 124 are simultaneously etched by an etching process, which simplifies the process steps. The etching process comprises an anisotropic dry etching process.
Referring to fig. 9, the second dielectric layer, the upper electrode layer, the capacitor dielectric layer and the lower electrode layer are etched using the capacitor pattern (not shown) as a mask; then, the photoresist on the second dielectric layer is removed, and an initial capacitor structure 130 is formed on the first circuit region.
Referring to fig. 10, a protection layer 131 is formed on the first dielectric layer 120 and the initial capacitor structure 130.
The protective layer 131 entirely covers the surface and the sidewalls of the initial capacitor structure 130, and the material of the protective layer 131 includes one or more of silicon dioxide, silicon oxynitride, and silicon nitride. The formation process of the protective layer 131 includes one or more combinations of LPCVD, RTCVD, or ALD. In one embodiment, the protection layer 131 may include a silicon oxide layer derived from Tetraethoxysilane (TEOS). TEOS deposition for non-plasma deposition processes may include low pressure cvd (lpcvd) at a pressure of about 300mTorr and a temperature of about 700 ℃. The protective layer 131 may also include organosilicate glass (OSG), low-k dielectrics (i.e., smaller dielectric constants relative to silicon dioxide), doped dielectric layers such as fluorine doped quartz glass (FSG).
Referring to fig. 11, a photoresist is coated on the protection layer 131, and an opening pattern and a second trench pattern are defined through a photolithography process.
The opening pattern is used for forming an opening in the second dielectric layer of the initial capacitor structure 130 in a subsequent step, and the bottom of the opening exposes the upper electrode layer; the second trench pattern is used to form a second trench in the first dielectric layer 120, and the bottom of the second trench exposes the second metal interconnection layer 112 and the second metal interconnection layer 112. The specific photolithography process is performed in the prior art and will not be described in detail herein.
And then, etching the protective layer and the first dielectric layer by taking the opening pattern and the second groove pattern as masks to form an opening and a second groove. In this embodiment, the process of forming the opening and the second trench includes: etching the protective layer by using the opening pattern and the second groove pattern as masks and adopting a first etching process to form an initial opening and an initial second groove which penetrate through the protective layer; and etching the second dielectric layer at the bottom of the initial opening and the first dielectric layer at the bottom of the initial second groove by adopting a second etching process to form an opening penetrating through the second dielectric layer and a second groove penetrating through the first dielectric layer.
As shown in fig. 12, the opening pattern and the second trench pattern are used as masks, and the protective layer 131 is etched by using a first etching process to form an initial opening and an initial second trench penetrating through the protective layer 131.
The first etching process comprises an anisotropic dry etching process, the protective layer 131 on the initial capacitor structure is etched through the first etching process to form an initial opening, and a part of the second dielectric layer of the initial capacitor structure is exposed from the bottom of the initial opening; the first etching process further etches the protective layer 131 on the second metal interconnection layer 112 to form the initial second trench, and the bottom of the initial second trench exposes a portion of the first dielectric layer on the second metal interconnection layer 112.
Then, as shown in fig. 13, a second etching process is used to etch the second dielectric layer at the bottom of the initial opening and the first dielectric layer at the bottom of the initial second trench, so as to form an opening 151 penetrating through the second dielectric layer and a second trench 152 penetrating through the first dielectric layer.
The opening 151 penetrates through the protective layer 131 and the second dielectric layer on the upper electrode layer, the second etching process includes an anisotropic dry etching process, the thickness ratio between the first dielectric layer 120 and the second dielectric layer 124 is equal to or close to an etching rate ratio, and the opening and the second trench can be formed simultaneously by one-time etching through the second etching process, so that the process steps are simplified, and the process stability is improved. The first etching process and the second etching process are both dry etching processes, so that a miniaturized capacitor structure is facilitated, and the integration level of a device is improved. In the process of forming the second trench 152, the protective layer 131 on the surface of the first dielectric layer 120 also covers the sidewall of the capacitor structure, so as to avoid short circuit between the upper electrode layer and the lower electrode layer.
Next, as shown in fig. 14, the photoresist on the protective layer is removed.
The forming process of the capacitor structure 150 in the invention only includes 4 times of photoetching and etching processes, which respectively correspond to the formation of the first trench, the formation of the initial capacitor structure, the formation of the initial opening and the initial second trench, and the formation of the opening and the second trench, compared with the prior art, the process flow is greatly simplified, and the process stability is better.
Finally, as shown in fig. 15, an electrode interconnection layer 160 filling the opening and the second trench is formed on the protective layer 131.
The electrode interconnection layer 160 may use a metal material such as aluminum or tungsten, and the forming process, the photolithography process, and the etching process of the metal material are all the prior art and are not described herein again. The preparation process of the capacitor structure formed by the invention is completely the same as the preparation process of a Complementary Metal Oxide Semiconductor (CMOS), not only can be completely fused with the CMOS process, but also has mature process, high reliability and low manufacturing cost.
The capacitor structure comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, wherein the lower electrode layer is positioned on the surface of a first dielectric layer and covers the bottom and the side wall of a first groove; the second dielectric layer is positioned on the upper electrode layer and provided with an opening, and the bottom of the opening is exposed out of part of the upper electrode layer; and the electrode interconnection layer fills the opening and a second groove positioned in a second circuit region and is electrically connected with the upper electrode layer and the second circuit region. The invention can finish the formation of the capacitor structure by only using 4 times of photoetching, thereby simplifying the process steps and saving the process manufacturing cost. In addition, the invention does not need extra BARC filling and back etching, and does not need to carry out separate photoetching and etching on the lower electrode layer, thereby avoiding the plasma damage of the lower electrode layer in the BARC removing process, and simultaneously preventing the residue of the BARC in the first groove. In addition, the protective layer is formed on the side wall of the capacitor structure, so that short circuit of the upper electrode layer and the lower electrode layer is further prevented, the purpose of improving the performance and the reliability of the device is achieved, and the capacitor structure has obvious significance.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A trench capacitor device, comprising:
the circuit comprises a substrate, a first circuit area and a second circuit area, wherein the substrate is provided with the first circuit area and the second circuit area;
the circuit comprises an isolation medium structure positioned on the surface of the substrate and a metal interconnection layer positioned in the isolation medium structure, wherein the metal interconnection layer comprises a first metal interconnection layer and a second metal interconnection layer, the first metal interconnection layer is electrically connected with the first circuit area, and the second metal interconnection layer is electrically connected with the second circuit area;
the first dielectric layer is positioned on the surface of the isolation dielectric structure;
the groove capacitor area is positioned on the first metal interconnection layer and comprises a plurality of first grooves and a capacitor structure which is positioned on the first dielectric layer and fills the first grooves, and the first grooves penetrate through the first dielectric layer and are terminated at the first metal interconnection layer;
a second trench extending through the first dielectric layer and terminating at the second metal interconnect layer;
an electrode interconnect layer on the capacitive structure; wherein,
the capacitor structure is provided with an opening and comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, wherein the lower electrode layer is positioned on the surface of the first dielectric layer and covers the bottom and the side wall of the first groove, the capacitor dielectric layer is positioned on the surface of the lower electrode layer, the upper electrode layer is positioned on the surface of the capacitor dielectric layer and fills the first groove, and the lower electrode layer is electrically connected with the first metal interconnection layer; a second dielectric layer on the upper electrode layer, the opening penetrating the second dielectric layer and terminating at the upper electrode layer; the electrode interconnection layer is located on the second dielectric layer, fills the opening and the second trench, and is electrically connected with the upper electrode layer and the second metal interconnection layer.
2. The trench capacitor device of claim 1 wherein the opening extends through the second dielectric layer and into the upper electrode layer.
3. The trench capacitor device of claim 1 further comprising a protective layer on a surface of the second dielectric layer, the protective layer further extending to cover a sidewall surface of the capacitor structure on the first dielectric layer, the opening extending through the protective layer, the electrode interconnect layer covering a portion of a surface of the protective layer.
4. The trench capacitor device of claim 1 wherein the first circuit region includes a first transistor and the second circuit region includes a second transistor, the first metal interconnect layer being electrically connected to the first circuit region through a first via in the isolation dielectric structure and the second metal interconnect layer being electrically connected to the second circuit region through a second via in the isolation dielectric structure.
5. A method for manufacturing a trench capacitor device, comprising:
forming a first circuit area and a second circuit area on a substrate by adopting a front manufacturing process, and then forming an isolation medium structure and a metal interconnection layer positioned in the isolation medium structure on the surface of the substrate by adopting a rear manufacturing process, wherein the metal interconnection layer comprises a first metal interconnection layer electrically connected with the first circuit area and a second metal interconnection layer electrically connected with the second circuit area;
forming a first dielectric layer on the surface of the isolation dielectric structure;
forming a first groove penetrating through the first dielectric layer;
depositing a lower electrode layer, a capacitance dielectric layer and an upper electrode layer on the first dielectric layer and on the side wall and the surface of the first groove in sequence, wherein the upper electrode layer fills the first groove;
depositing a second dielectric layer on the upper electrode layer;
coating photoresist on the second dielectric layer, and defining a capacitor pattern through a photoetching process;
etching the second dielectric layer, the upper electrode layer, the capacitor dielectric layer and the lower electrode layer by taking the capacitor pattern as a mask;
removing the photoresist on the second dielectric layer, and forming an initial capacitor structure on the first circuit region;
forming a protective layer on the first dielectric layer and the initial capacitor structure;
coating photoresist on the protective layer, and defining an opening pattern and a second groove pattern through a photoetching process;
etching the protective layer and the first dielectric layer by taking the opening pattern and the second groove pattern as masks to form a capacitor structure with an opening and a second groove;
removing the photoresist on the protective layer;
forming an electrode interconnection layer filling the opening and the second trench on the protective layer.
6. The method for manufacturing a trench capacitor device as claimed in claim 5, wherein the material of the second dielectric layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, and nitrogen-containing silicon carbide; the material of the lower electrode layer and the upper electrode layer comprises a metal compound and a metal material, wherein the metal compound comprises one or two of titanium nitride and tantalum nitride; the metal material comprises one or more of aluminum, tungsten and copper; the capacitor dielectric layer is made of one or more of silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide and aluminum oxide; the material of the protective layer comprises one or more of silicon dioxide, silicon oxynitride and silicon nitride.
7. The method of making a trench capacitor device of claim 5 wherein the thickness ratio between the first dielectric layer and the second dielectric layer is equal to the etch rate ratio.
8. The method of manufacturing a trench capacitor device as set forth in claim 7, wherein the thickness of the first dielectric layer is 800nm and the thickness of the second dielectric layer is 100 nm; the etching rate ratio of the first dielectric layer to the second dielectric layer is 8: 1.
9. The method of manufacturing a trench capacitor device as set forth in claim 8, wherein the process of forming the opening and the second trench comprises: etching the protective layer by using the opening pattern and the second groove pattern as masks and adopting a first etching process to form an initial opening and an initial second groove which penetrate through the protective layer; and etching the second dielectric layer at the bottom of the initial opening and the first dielectric layer at the bottom of the initial second groove by adopting a second etching process to form an opening penetrating through the second dielectric layer and a second groove penetrating through the first dielectric layer.
10. The method of manufacturing a trench capacitor device as set forth in claim 8, wherein said first etching process and said second etching process comprise a dry etching process.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112510012A (en) * | 2020-12-24 | 2021-03-16 | 上海集成电路装备材料产业创新中心有限公司 | Groove type capacitor device and preparation method thereof |
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| US20090200637A1 (en) * | 2008-02-12 | 2009-08-13 | Byron Lovell Williams | Methods and devices for a high-k stacked capacitor |
| US20100032803A1 (en) * | 2008-08-08 | 2010-02-11 | Texas Instruments Incorporated | Capacitor contact formed concurrently with bond pad metallization |
| US20100032801A1 (en) * | 2008-08-08 | 2010-02-11 | Texas Instruments Incorporated | Capacitor formed in interlevel dielectric layer |
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| US20090200637A1 (en) * | 2008-02-12 | 2009-08-13 | Byron Lovell Williams | Methods and devices for a high-k stacked capacitor |
| US20100032803A1 (en) * | 2008-08-08 | 2010-02-11 | Texas Instruments Incorporated | Capacitor contact formed concurrently with bond pad metallization |
| US20100032801A1 (en) * | 2008-08-08 | 2010-02-11 | Texas Instruments Incorporated | Capacitor formed in interlevel dielectric layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112510012A (en) * | 2020-12-24 | 2021-03-16 | 上海集成电路装备材料产业创新中心有限公司 | Groove type capacitor device and preparation method thereof |
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