CN112614814A - Power chip heat dissipation packaging structure and manufacturing method thereof - Google Patents
Power chip heat dissipation packaging structure and manufacturing method thereof Download PDFInfo
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- CN112614814A CN112614814A CN202011476154.XA CN202011476154A CN112614814A CN 112614814 A CN112614814 A CN 112614814A CN 202011476154 A CN202011476154 A CN 202011476154A CN 112614814 A CN112614814 A CN 112614814A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
Abstract
The invention provides a power chip heat dissipation packaging structure and a manufacturing method thereof, wherein the power chip heat dissipation packaging structure comprises the following steps: a power chip package module configured to accommodate a power chip and a heat dissipation package module; a PCB motherboard configured to carry one or more power chip package modules; a heat insulation packaging module configured to be connected between the power chip packaging module and the PCB motherboard and cut off a heat conduction path of the power chip packaging module and the PCB motherboard; the heat dissipation packaging module is arranged on one side, opposite to the PCB motherboard, of the power chip packaging module and conducts heat of the power chip packaging module to other structures or spaces.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a power chip heat dissipation packaging structure and a manufacturing method thereof.
Background
In the power chip package, a short circuit occurs when the power chip operates due to a process defect, so that an instantaneous current is increased, and a heat generation amount is increased rapidly. The heat generated by the power chip is not in time to be conducted out, so that the packaging body is burnt, and finally, the heat is spread to the PCB motherboard to cause damage to the PCB motherboard. Due to the high cost of PCB motherboard manufacture, protection is required in the event of such failures (acceptable power chip package burn-out, unacceptable PCB motherboard burn-out).
Most of the power chip packaging structures in the market at present are separated packaging structures, and the chips are fixed on the frame carrier plate through a welding layer, so that a heat dissipation channel of the power chips is constructed. The advanced Packaging technology of the power chip includes an AT & S ECP (Embedded Component Packaging) technology, and the power chip and its components are Embedded in a package body, so that the chip can be efficiently cooled by designing a reasonable heat conduction channel. However, most of ECP packaging bodies are simple in structure, a large amount of heat can be generated by some high-power chips during working, particularly, when the chips are short-circuited, the heat generated by overload can be increased rapidly, a heat dissipation channel is constructed only through structural design, the heat generated by the power chips cannot be led out in time, the performance of the chips can be affected, and the packaging bodies can be burnt out.
Disclosure of Invention
The invention aims to provide a power chip heat dissipation packaging structure and a manufacturing method thereof, which aim to solve the problem that the packaging body is burnt and even a PCB motherboard is damaged due to the fact that heat generated by the conventional power chip is not led out in time.
In order to solve the above technical problem, the present invention provides a power chip heat dissipation package structure, including:
a power chip package module configured to accommodate a power chip and a heat dissipation package module;
a PCB motherboard configured to carry one or more power chip package modules;
a heat insulation packaging module configured to be connected between the power chip packaging module and the PCB motherboard and cut off a heat conduction path of the power chip packaging module and the PCB motherboard;
the heat dissipation packaging module is arranged on one side, opposite to the PCB motherboard, of the power chip packaging module and conducts heat of the power chip packaging module to other structures or spaces.
Optionally, in the power chip heat dissipation package structure, the power chip package module is electrically connected to the PCB motherboard through solder balls, and the heat insulation package module wraps the solder balls;
and one or more of a capacitor, a resistor and an interconnection line are also accommodated in the power chip packaging module.
Optionally, in the power chip heat dissipation package structure, the heat dissipation package module includes a heat conduction ceramic sheet, a copper pillar, and a first surface bonding pad;
the heat conductivity of the heat-conducting ceramic plate is more than 200W/m.k, and the heat-conducting ceramic plate is made of AlN;
the copper column and the first surface bonding pad are manufactured in the heat-conducting ceramic chip through a ceramic substrate wiring process, and the copper column and the first surface bonding pad conduct heat generated when the power chip works or is in short circuit.
Optionally, in the power chip heat dissipation package structure, a surface-mounted inductor is disposed on a surface of the heat dissipation package module opposite to the power chip package module, and the heat dissipation package module transfers heat of the power chip package module to the surface-mounted inductor;
the surface-mounted inductor is electrically connected with the power chip packaging module through the interconnection line.
Optionally, in the power chip heat dissipation package structure, the heat insulation package module is a ceramic coating, the ceramic coating is an yttrium-stabilized zirconia material or a rare earth zirconate, and the thermal conductivity of the ceramic coating is 1.5W/m · k at 1400 ℃;
and forming the ceramic coating by adopting a spraying or printing mode in air, and curing and forming at low temperature.
The invention also provides a heat dissipation packaging method of the power chip, which comprises the following steps:
manufacturing a power chip packaging module, and accommodating the power chip and the heat dissipation packaging module in the power chip packaging module so as to conduct the heat of the power chip packaging module to other structures or spaces; wherein:
the heat dissipation packaging module is arranged at one side of the power chip packaging module, and the other side of the power chip packaging module is welded to the PCB motherboard;
and manufacturing a heat insulation packaging module between the power chip packaging module and the PCB motherboard to cut off a heat conduction path between the power chip packaging module and the PCB motherboard.
Optionally, in the method for heat dissipation and packaging of a power chip, the method further includes:
slotting on a substrate of the power chip packaging module;
placing the power chip in the groove and filling to form a first dielectric layer;
forming a first electrical interconnection structure on the first dielectric layer, the first electrical interconnection structure being electrically connected with the power chip;
mounting the heat dissipation packaging module on the power chip;
pressing the substrate to form a second dielectric layer;
forming a second electrical interconnect structure on the second dielectric layer, the second electrical interconnect structure being in electrical connection with the first electrical interconnect structure;
connecting-a second electrical interconnect structure to the surface mount inductor;
and connecting the second electrical interconnection structure on the other side of the power chip packaging module to the PCB motherboard.
Optionally, in the method for heat dissipation packaging of a power chip, forming the first electrical interconnection structure and the second electrical interconnection structure includes:
through holes are manufactured on the first dielectric layer or the second dielectric layer in a mechanical drilling or laser etching mode, and blind holes are manufactured in a laser etching mode until the power chip, the capacitor, the resistor, the first surface bonding pad or the second surface bonding pad electrically connected with the first electrical interconnection structure are exposed;
and forming a seed layer in the through hole, the blind hole, the first dielectric layer or the through hole, the blind hole and the surface of the second dielectric layer by chemical deposition or sputtering, defining a pattern of the second surface pad or the third surface pad by photoetching, filling the through hole and the blind hole by electroplating copper, forming the second surface pad or the third surface pad, and finishing the filling of the hole and the interconnection and conduction of the surface circuit.
Optionally, in the method for heat dissipation and packaging of a power chip, the method further includes:
the first dielectric layer and the second dielectric layer are made of prepreg dielectric materials or ABF dielectric materials;
after the second electrical interconnection structure is completed, attaching a green oil solder mask layer on the surface of the power chip packaging module and windowing the solder mask layer to expose the second electrical interconnection structure;
and manufacturing solder balls on the second electrical interconnection structure, wherein the solder balls are used for connecting a PCB motherboard.
Optionally, in the method for heat dissipation and packaging of a power chip, the method further includes:
and manufacturing a ceramic coating around the solder balls between the power chip packaging module and the PCB motherboard by adopting an air spraying or printing mode, and curing and molding at the temperature of 150 ℃.
In the power chip heat dissipation packaging structure and the manufacturing method thereof provided by the invention, the power chip and the heat dissipation packaging module are accommodated in the power chip packaging module, the heat dissipation packaging module is arranged at one side of the power chip packaging module, the other side of the power chip packaging module is welded on the PCB motherboard, and the heat insulation packaging module is manufactured between the power chip packaging module and the PCB motherboard, so that the power chip is embedded in the power chip packaging module, the heat dissipation packaging module conducts the heat of the power chip packaging module to other structures or spaces, and the heat insulation packaging module cuts off the heat conduction path of the power chip packaging module and the PCB motherboard, thereby achieving the technical effects of respectively forming a heat insulation barrier and a heat dissipation channel at the bottom and the top of the power chip packaging module, realizing that the heat dissipation channel improves the upward heat dissipation capability of the power chip packaging module, the heat insulation channel isolates heat conducted downwards from the power chip packaging module to the PCB motherboard, and the technical effect of the PCB motherboard is protected.
Furthermore, the heat insulation barrier and the heat dissipation channel are both constructed by adopting ceramic materials; the heat-conducting ceramic chip is integrated by adopting a mounting process, and the heat-insulating ceramic coating is formed by adopting an air spraying process, so that the process is simple and the cost is lower.
The invention provides a power chip packaging framework combining heat dissipation and heat insulation, which can lead out heat generated after a power chip is short-circuited at high efficiency in time on one hand, and can prevent the heat generated after the power chip is short-circuited from being conducted to a PCB motherboard to protect the PCB motherboard on the other hand; the heat dissipation structure adopts a high-heat-conductivity ceramic chip and is attached to the top of the power chip to play a role in high-efficiency heat dissipation; the heat insulation structure adopts a low-heat-conductivity ceramic coating, is manufactured between the power chip packaging module and the PCB motherboard, isolates heat conducted to the PCB motherboard after the power chip is short-circuited, and plays a role in protecting the PCB motherboard; the ceramic chip structure with the heat dissipation rate is integrated by adopting a mounting process, and the ceramic chip with the heat insulation structure is formed by adopting an air spraying process, so that the process is simple and the cost is lower.
Drawings
Fig. 1 is a schematic diagram of a heat dissipation package structure of a power chip according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a substrate slot for a heat dissipation package method of a power chip according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a power chip mounted by the heat dissipation packaging method of the power chip according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating a first dielectric layer of a heat dissipation package method for a power chip according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first electrical interconnection structure formed by a heat dissipation packaging method for a power chip according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a heat-dissipating package module formed by the heat-dissipating packaging method for a power chip according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a second dielectric layer formed by the heat dissipation packaging method for a power chip according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a second electrical interconnection structure formed by the heat dissipation packaging method for a power chip according to an embodiment of the invention;
FIG. 9 is a schematic diagram of a solder mask formed by the heat dissipation packaging method for power chips according to an embodiment of the invention;
FIG. 10 is a schematic diagram of a surface mount inductor for a power chip heat dissipation package method according to an embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating a method for heat-dissipating packaging of a power chip and a PCB motherboard according to an embodiment of the present invention;
FIG. 12 is a schematic view of a heat-shielding package module formed by the heat-dissipating packaging method for a power chip according to an embodiment of the present invention;
shown in the figure: 1-a power chip package module; 2-heat dissipation packaging module; 21-heat conducting ceramic plate; 22-copper columns; 23-first surface pads; 3-a heat insulation packaging module; 4-PCB mother board; 5-solder balls; 6-surface mounting of an inductor; 7-a substrate; 8-a power chip; 9-a first dielectric layer; 10-a second dielectric layer; 11 — a first electrical interconnect structure; 12-a second electrical interconnect structure; 13-a through hole; 14-blind holes; 15-second surface pads; 16-a solder mask layer; 17-third surface pads.
Detailed Description
The power chip heat dissipation package structure and the manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Furthermore, features from different embodiments of the invention may be combined with each other, unless otherwise indicated. For example, a feature of the second embodiment may be substituted for a corresponding or functionally equivalent or similar feature of the first embodiment, and the resulting embodiments are likewise within the scope of the disclosure or recitation of the present application.
The core idea of the invention is to provide a power chip heat dissipation packaging structure and a manufacturing method thereof, so as to solve the problem that the packaging body is burnt and even the PCB motherboard is damaged due to the fact that the heat generated by the conventional power chip is not led out in time.
In an actual working condition, a short circuit occurs when the power chip works due to a defect in the process, so that instantaneous current is increased, and the heat productivity is increased rapidly. The heat generated by the chip is not in time to be led out, so that the packaging body is burnt, and finally, the heat is spread to the PCB motherboard to cause damage to the PCB motherboard. Due to the high cost of PCB motherboard manufacture, protection is required in the event of such failures. Because, this technical scheme mainly realizes exporting in time the heat that produces after the short circuit of power chip, isolated simultaneously by the heat conduction of power chip production to the heat of PCB motherboard, the protection PCB motherboard is not damaged.
The proposal aims at the problem that the PCB motherboard is burnt when the power chip is short-circuited, and in ECP packaging, if no good thermal isolation measure is provided, the heat generated after the chip is short-circuited can be conducted to the PCB motherboard to cause the damage of the expensive PCB motherboard. According to the scheme, two paths of heat insulation and heat dissipation are designed in the power chip packaging structure, so that the problem that a PCB motherboard is burnt due to rapid heating after a power chip is short-circuited is solved.
In order to realize the idea, the invention provides a power chip heat dissipation packaging structure and a manufacturing method thereof, wherein the power chip heat dissipation packaging structure comprises the following steps: manufacturing a power chip packaging module, and accommodating the power chip and the heat dissipation packaging module in the power chip packaging module so as to conduct the heat of the power chip packaging module to other structures or spaces; wherein: the heat dissipation packaging module is arranged at one side of the power chip packaging module, and the other side of the power chip packaging module is welded to the PCB motherboard; and manufacturing a heat insulation packaging module between the power chip packaging module and the PCB motherboard to cut off a heat conduction path between the power chip packaging module and the PCB motherboard.
The present embodiment provides a power chip heat dissipation package structure, as shown in fig. 1, including: a power chip package module 1 configured to accommodate a power chip 8 and a heat dissipation package module 2; a PCB motherboard 4 configured to carry one or more power chip package modules 1; a heat insulation package module 3 configured to be connected between the power chip package module 1 and the PCB motherboard 4, cutting off a heat conduction path of the power chip package module 1 and the PCB motherboard 4; the heat dissipation package module 2 is arranged on the side of the power chip package module 1 opposite to the PCB motherboard 4, and conducts heat of the power chip package module 1 to other structures or spaces.
In an embodiment of the present invention, in the power chip heat dissipation package structure, the power chip package module 1 and the PCB motherboard 4 are electrically connected through solder balls 5, and the heat insulation package module 3 wraps the solder balls 5; the power chip packaging module 1 also contains one or more of a capacitor C, a resistor R and an interconnection line.
In an embodiment of the present invention, in the power chip heat dissipation package structure, the heat dissipation package module 2 includes a heat conductive ceramic sheet 21, a copper pillar 22, and a first surface pad 23; the heat conductivity of the heat-conducting ceramic plate 21 is more than 200W/m.k, and the heat-conducting ceramic plate 21 is made of AlN; and manufacturing a copper column 22 and a first surface bonding pad 23 in the heat-conducting ceramic sheet 21 through a ceramic substrate wiring process, wherein the copper column 22 and the first surface bonding pad 23 conduct heat generated when the power chip 8 works or is in short circuit.
In an embodiment of the present invention, in the power chip heat dissipation package structure, a surface-mounted inductor 6 is disposed on a surface of the heat dissipation package module 2 opposite to the power chip package module 1, and the heat dissipation package module 2 conducts heat of the power chip package module 1 to the surface-mounted inductor 6; the surface-mounted inductor 6 is electrically connected with the power chip package module 1 through-interconnection lines on two sides (including a first electrical interconnection structure and a second electrical interconnection structure).
In one embodiment of the invention, in the power chip heat dissipation packaging structure, the heat insulation packaging module 3 is a ceramic coating, the ceramic coating is an yttrium-stabilized zirconia material or a rare earth zirconate, and the thermal conductivity of the ceramic coating is 1.5W/m-k at 1400 ℃; and forming the ceramic coating by adopting a spraying or printing mode in air, and curing and forming at low temperature.
The invention also provides a heat dissipation packaging method of the power chip, which comprises the following steps: as shown in fig. 2 to 12, a power chip package module 1 is manufactured, and a power chip 8 and a heat dissipation package module 2 are accommodated in the power chip package module 1 to conduct heat of the power chip package module 1 to other structures or spaces; wherein: the heat dissipation packaging module 2 is arranged at one side of the power chip packaging module 1, and the other side of the power chip packaging module 1 is welded to the PCB motherboard 4; as shown in fig. 12, the heat insulation package module 3 is fabricated between the power chip package module 1 and the PCB motherboard 4 to cut off a heat conduction path of the power chip package module 1 and the PCB motherboard 4.
In an embodiment of the present invention, in the method for heat dissipation packaging of a power chip, the method further includes: as shown in fig. 2, a groove is formed on the substrate 7 of the power chip package module 1; as shown in fig. 3, the power chip 8 is placed in the groove and filled to form a first dielectric layer 9; as shown in fig. 4 to 5, a first electrical interconnection structure 11 is formed on the first dielectric layer 9, and the first electrical interconnection structure 11 is electrically connected with the power chip 8; as shown in fig. 6, the heat dissipation package module 2 is mounted on the power chip 8; as shown in fig. 7, a second dielectric layer 10 is formed on the substrate 7 by pressing; as shown in fig. 8, a second electrical interconnection structure 12 is formed on the second dielectric layer 10, and the second electrical interconnection structure 12 is electrically connected to the first electrical interconnection structure 11 or the heat dissipation package module 2; as shown in fig. 10, the second electrical interconnection structure 12 electrically connected to the heat dissipation package module 2 is connected to the surface-mounted inductor 6; as shown in fig. 11, the second electrical interconnect structure 12 on the other side of the power chip package module 1 is connected to the PCB motherboard 4.
In an embodiment of the present invention, in the method for heat dissipation packaging of a power chip, forming the first electrical interconnection structure 11 includes: through holes 13 are formed in the first dielectric layer 9 in a mechanical drilling or laser etching mode, and blind holes 14 are formed in a laser etching mode until the power chip 8, the capacitor C and the resistor R are exposed; and forming a seed layer in the through hole 13, the blind hole 14 and the surface of the first dielectric layer 9 through chemical deposition or sputtering, defining the pattern of the second surface bonding pad 15 through photoetching, filling the through hole 13 and the blind hole 14 with electroplated copper, forming the second surface bonding pad 15, and completing the filling of the hole and the interconnection and conduction of the surface circuit.
In an embodiment of the present invention, in the method for heat dissipation packaging of a power chip, forming the second electrical interconnection structure 12 includes: through holes 13 are formed in the second dielectric layer 10 in a mechanical drilling or laser etching mode, and blind holes 14 are formed in a laser etching mode until the first surface bonding pads 23 or the second surface bonding pads 15 electrically connected with the first electrical interconnection structures 11 are exposed; and forming a seed layer in the through hole 13, the blind hole 14 and the surface of the second dielectric layer 10 by chemical deposition or sputtering, defining the pattern of the third surface pad 17 by photoetching, filling the through hole 13 and the blind hole 14 with electroplated copper, forming the third surface pad 17, and completing the filling of the hole and the interconnection and conduction of the surface circuit.
In an embodiment of the present invention, in the method for heat dissipation packaging of a power chip, the method further includes: the first dielectric layer 9 and the second dielectric layer 10 are made of prepreg dielectric materials or ABF dielectric materials; after the second electrical interconnection structure 12 is completed, attaching a green oil solder mask layer 16 on the surface of the power chip package module 1 and opening a window on the solder mask layer 16 to expose the second electrical interconnection structure 12 as shown in fig. 9; and manufacturing solder balls 5 on the second electric interconnection structures 12, wherein the solder balls 5 are used for connecting the PCB motherboard 4.
In an embodiment of the present invention, in the method for heat dissipation packaging of a power chip, the method further includes: and manufacturing a ceramic coating around the solder balls 5 between the power chip packaging module 1 and the PCB motherboard 4 by adopting an air spraying or printing mode, and curing and molding at the temperature of 150 ℃.
In the power chip heat dissipation packaging structure and the manufacturing method thereof provided by the invention, the power chip 8 and the heat dissipation packaging module 2 are accommodated in the power chip packaging module 1, the heat dissipation packaging module 2 is arranged at one side of the power chip packaging module 1, the other side of the power chip packaging module 1 is welded on the PCB motherboard 4, and the heat insulation packaging module 3 is manufactured between the power chip packaging module 1 and the PCB motherboard 4, so that the power chip 8 can be embedded in the power chip packaging module 1, the heat dissipation packaging module 2 conducts the heat of the power chip packaging module 1 to other structures or spaces, and the heat insulation packaging module 3 cuts off the heat conduction path of the power chip packaging module 1 and the PCB motherboard 4, thereby achieving the technical effect of respectively forming a heat insulation barrier and a heat dissipation channel at the bottom and the top of the power chip packaging module 1, realizing that the heat dissipation channel improves the upward heat dissipation capability of the power chip packaging module 1, the heat insulation channel insulates heat conducted from the power chip package module 1 to the PCB motherboard 4 downward, and protects the technical effect of the PCB motherboard 4.
Furthermore, the heat insulation barrier and the heat dissipation channel are both constructed by adopting ceramic materials; the heat-conducting ceramic sheet 21 is integrated by adopting a mounting process, and the heat-insulating ceramic coating is formed by adopting an air spraying process, so that the process is simple and the cost is lower.
The invention provides a power chip packaging framework combining heat dissipation and heat insulation, which can lead out heat generated after a power chip is short-circuited at high efficiency in time on one hand, and can prevent the heat generated after the power chip is short-circuited from being conducted to a PCB mother board 4 on the other hand, so that the PCB mother board 4 is protected; the heat dissipation structure adopts a high-heat-conductivity ceramic chip 21 and is attached to the top of the power chip to play a role in high-efficiency heat dissipation; the heat insulation structure adopts a low-heat-conductivity ceramic coating, is manufactured between the power chip packaging module 1 and the PCB mother board 4, isolates heat conducted to the PCB mother board 4 after the power chip is short-circuited, and plays a role in protecting the PCB mother board 4; the structure of the ceramic sheet 21 with the heat dissipation rate is integrated by adopting a mounting process, and the ceramic sheet 21 with the heat insulation structure is formed by adopting an air spraying process, so that the process is simple and the cost is lower.
The invention provides a heat insulation and heat dissipation packaging structure for a power chip for protecting a mainboard (burn-out prevention), which mainly comprises a mainboard (PCB motherboard 4), an ECP packaging body (power chip packaging module 1) and a surface-mounted inductor 6, as shown in figure 1. The ECP packaging body is connected with the mainboard through balls (welded balls 5), and electric signal conduction is achieved. The ECP package includes a Power Die 8(Power Die), a capacitor (C), a resistor (R), a thermally conductive ceramic plate 21, and an interconnection. A heat-conducting ceramic plate 21 is pasted on the top of the power chip 8, the material is AlN high heat conductivity material (more than or equal to 200W/m.k), a copper column 22 and a first surface bonding pad 23 are manufactured in the ceramic plate 21 through a ceramic substrate wiring process, and therefore a large amount of heat generated when the power chip 8 works or is in short circuit can be conducted. A ceramic coating is made between the ECP packaging body 1 and the main board 4, the ceramic coating is made of yttrium stabilized zirconia material (YSZ), rare earth zirconate and the like, has excellent heat insulation performance and low heat conductivity (approximately equal to 1.5W/m.k, 1400 ℃), is widely applied to the field of thermal barrier coatings of aeroengines, can be sprayed or printed in the air, and is cured and formed at low temperature (150 ℃), so that heat conducted from the ECP packaging body to the main board can be isolated, and the main board is prevented from being burnt.
According to the invention, by constructing a double structure of heat insulation and heat conduction, the heat insulation ceramic coating with low heat conductivity is used between the ECP packaging body 1 and the PCB motherboard 4, so that the heat conducted from the power chip 8 to the PCB motherboard 4 can be isolated, the ceramic sheet 21 with high heat conductivity is pasted on the top of the power chip 8, the heat generated by the power chip 8 can be timely led out, the heat transferred to the PCB motherboard 4 is reduced, and the purpose of protecting the PCB motherboard 4 is achieved.
The manufacturing method of the invention is as follows: 1) and (5) etching the copper plate. The copper plate is grooved by laser or mechanical means. 2) The device is buried. Devices or elements such as a Power Die, a capacitor (C), a resistor (R) and the like are placed in the copper plate with the groove, and the devices are fixed by pressing the first dielectric layer 9. The first dielectric Layer 9 is generally a Prepreg dielectric material, ABF (Ajinomote Build-up Layer) dielectric material. 3) And manufacturing a through hole 13 and a blind hole 14. And a through hole 13 is formed in the first dielectric layer 9 in a mechanical drilling or laser etching mode, a blind hole 14 is formed in a laser etching mode, and the blind hole is butted to a second surface bonding pad 15 of the power chip 8, the capacitor C and the resistor R. 4) And (4) hole metallization. And forming a seed layer in the through hole 13, the blind hole 14 and the surface of the first dielectric layer through chemical deposition or sputtering, defining a pad pattern through photoetching, filling the hole by electroplating copper, forming a second surface pad 15, and completing the filling of the hole and the interconnection and conduction of the surface circuit. 5) And the ceramic sheet 21 is mounted. The surface of the power chip 8 is pasted with a heat conduction ceramic wafer 21, the ceramic wafer 21 is made of high thermal conductivity materials (more than or equal to 200W/m.k) such as AlN, and the internal copper pillar 22 and the first surface bonding pad 23 can be manufactured through a ceramic substrate wiring process. The heat conductive ceramic sheet 21 is attached to the upper portion of the power chip 8 to conduct heat generated when the power chip 8 operates or is short-circuited. The projected area of the ceramic plate 21 on the power chip 8 should cover the projected area of the power chip 8. 6) And pressing the second dielectric layer 10. And laminating second dielectric layers 10 on the front and back surfaces of the substrate 7, wherein the second dielectric layers 10 are generally a Prepreg dielectric material and an ABF (Ajinomote Build-up Layer) dielectric material. 7) Laser drilling and hole metallization. And manufacturing blind holes 14 on the upper and lower second dielectric layers 10 in a laser etching mode, and butting the blind holes to the second surface bonding pads 15 of the inner layer. The hole filling and the third surface pad fabrication are accomplished by chemical deposition or sputtering to form a seed layer, photolithographically define the pad pattern, copper electroplating to fill the holes and form the third surface pad 17. 8) The solder mask 16 is made and windowed. Green oil solder resist is attached to both the front and back surfaces of the substrate 7, and the substrate is windowed and exposed to the soldering position. 9) And mounting a surface-mounted Inductor 6(Inductor), and manufacturing a solder ball 5 at the bottom. And a surface-mounted inductor 6 is mounted on the surface of the substrate 7, and the first surface bonding pad 23 and the surface-mounted inductor 6 form metal connection to form a heat conduction channel. Solder balls 5 are formed on the bottom of the substrate 7. 10) And mounting with a PCB motherboard 4. The substrate 7 is attached to a PCB motherboard 4(Main Board) to form electrical interconnection. 11) And manufacturing a heat-insulating ceramic layer. A ceramic coating is made between the package substrate 7 and the PCB motherboard 4 (around the solder balls 5). The ceramic coating is made of materials such as Yttrium Stabilized Zirconia (YSZ), rare earth zirconate and the like, has excellent heat insulation performance and low thermal conductivity (approximately equal to 1.5W/m.k, 1400 ℃) and is widely applied to the field of thermal barrier coatings of aero-engines, the ceramic coating can be sprayed or printed in the air and then cured and formed at low temperature (150 ℃), and the power chip packaging module 1 conducts heat to a mainboard, so that the mainboard is prevented from being burnt.
Through constructing the double framework of heat insulation and heat conduction, the heat insulation ceramic coating with low heat conductivity is used between the power chip packaging module 1 and the PCB mother board 4, the heat conducted to the PCB mother board 4 by the power chip can be isolated, the ceramic sheet 21 with high heat conductivity is pasted on the top surface of the power chip, the heat generated by the power chip can be timely led out, so that the heat transmitted to the PCB mother board 4 is reduced, and the purpose of protecting the PCB mother board 4 is achieved.
In summary, the above embodiments have described the power chip heat dissipation package structure and the manufacturing method thereof in detail, and it is needless to say that the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications made on the configurations provided in the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A power chip heat dissipation package structure, comprising:
a power chip package module configured to accommodate a power chip and a heat dissipation package module;
a PCB motherboard configured to carry one or more power chip package modules;
a heat insulation packaging module configured to be connected between the power chip packaging module and the PCB motherboard and cut off a heat conduction path of the power chip packaging module and the PCB motherboard;
the heat dissipation packaging module is arranged on one side, opposite to the PCB motherboard, of the power chip packaging module and conducts heat of the power chip packaging module to other structures or spaces.
2. The power chip heat dissipation package structure of claim 1, wherein the power chip package module is electrically connected to the PCB motherboard by solder balls, and the thermal insulation package module wraps the solder balls;
and one or more of a capacitor, a resistor and an interconnection line are also accommodated in the power chip packaging module.
3. The power chip heat dissipation package structure of claim 2, wherein the heat dissipation package module comprises a thermally conductive ceramic sheet, a copper pillar, and a first surface pad;
the heat conductivity of the heat-conducting ceramic plate is more than 200W/m.k, and the heat-conducting ceramic plate is made of AlN;
the copper column and the first surface bonding pad are manufactured in the heat-conducting ceramic chip through a ceramic substrate wiring process, and the copper column and the first surface bonding pad conduct heat generated when the power chip works or is in short circuit.
4. The power chip heat dissipation package structure of claim 3, wherein a surface-mounted inductor is disposed on a side of the heat dissipation package module opposite to the power chip package module, and the heat dissipation package module conducts heat of the power chip package module to the surface-mounted inductor;
the surface-mounted inductor is electrically connected with the power chip packaging module through the interconnection line.
5. The power chip heat dissipation package structure of claim 1, wherein the heat insulating package module is a ceramic coating, the ceramic coating is a yttrium stabilized zirconia material or a rare earth zirconate, and the thermal conductivity of the ceramic coating is 1.5W/m-k at 1400 ℃;
and forming the ceramic coating by adopting a spraying or printing mode in air, and curing and forming at low temperature.
6. A heat dissipation packaging method for a power chip is characterized by comprising the following steps:
manufacturing a power chip packaging module, and accommodating the power chip and the heat dissipation packaging module in the power chip packaging module so as to conduct the heat of the power chip packaging module to other structures or spaces; wherein:
the heat dissipation packaging module is arranged at one side of the power chip packaging module, and the other side of the power chip packaging module is welded to the PCB motherboard;
and manufacturing a heat insulation packaging module between the power chip packaging module and the PCB motherboard to cut off a heat conduction path between the power chip packaging module and the PCB motherboard.
7. The method for heat sinking packaging of power chips as claimed in claim 6, further comprising:
slotting on a substrate of the power chip packaging module;
placing the power chip in the groove and filling to form a first dielectric layer;
forming a first electrical interconnection structure on the first dielectric layer, the first electrical interconnection structure being electrically connected with the power chip;
mounting the heat dissipation packaging module on the power chip;
pressing the substrate to form a second dielectric layer;
forming a second electrical interconnect structure on the second dielectric layer, the second electrical interconnect structure being electrically connected to the first electrical interconnect structure;
connecting a second electrical interconnect structure to the surface mount inductor;
and connecting the second electrical interconnection structure on the other side of the power chip packaging module to the PCB motherboard.
8. The method of claim 7, wherein forming the first and second electrical interconnect structures comprises:
through holes are manufactured on the first dielectric layer or the second dielectric layer in a mechanical drilling or laser etching mode, and blind holes are manufactured in a laser etching mode until the power chip, the capacitor, the resistor, the first surface bonding pad or the second surface bonding pad are exposed;
and forming a seed layer in the through hole, the blind hole, the first dielectric layer or the through hole, the blind hole and the surface of the second dielectric layer by chemical deposition or sputtering, defining a pattern of the second surface pad or the third surface pad by photoetching, filling the through hole and the blind hole by electroplating copper, forming the second surface pad or the third surface pad, and finishing the filling of the hole and the interconnection and conduction of the surface circuit.
9. The method for heat sinking packaging of power chips as claimed in claim 7, further comprising:
the first dielectric layer and the second dielectric layer are made of prepreg dielectric materials or ABF dielectric materials;
after the second electrical interconnection structure is completed, attaching a green oil solder mask layer on the surface of the power chip packaging module and windowing the solder mask layer to expose the second electrical interconnection structure;
and manufacturing solder balls on the second electrical interconnection structure, wherein the solder balls are used for connecting a PCB motherboard.
10. The method for heat sinking packaging of power chips as claimed in claim 7, further comprising:
and manufacturing a ceramic coating around the solder balls between the power chip packaging module and the PCB motherboard by adopting an air spraying or printing mode, and curing and molding at the temperature of 150 ℃.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011476154.XA CN112614814B (en) | 2020-12-15 | 2020-12-15 | Power chip heat dissipation packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011476154.XA CN112614814B (en) | 2020-12-15 | 2020-12-15 | Power chip heat dissipation packaging structure and manufacturing method thereof |
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| CN112614814A true CN112614814A (en) | 2021-04-06 |
| CN112614814B CN112614814B (en) | 2022-06-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022261947A1 (en) * | 2021-06-18 | 2022-12-22 | 华为技术有限公司 | Die package structure and preparation therefor, and package system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180190617A1 (en) * | 2016-12-31 | 2018-07-05 | Intel Corporation | Heat removal between top and bottom die interface |
| CN111106017A (en) * | 2019-11-28 | 2020-05-05 | 徐州顺意半导体科技有限公司 | Power module and preparation method thereof |
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2020
- 2020-12-15 CN CN202011476154.XA patent/CN112614814B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180190617A1 (en) * | 2016-12-31 | 2018-07-05 | Intel Corporation | Heat removal between top and bottom die interface |
| CN111106017A (en) * | 2019-11-28 | 2020-05-05 | 徐州顺意半导体科技有限公司 | Power module and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022261947A1 (en) * | 2021-06-18 | 2022-12-22 | 华为技术有限公司 | Die package structure and preparation therefor, and package system |
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| CN112614814B (en) | 2022-06-28 |
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