CN112614530A - Three-dimensional memory and control method thereof - Google Patents
Three-dimensional memory and control method thereof Download PDFInfo
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- CN112614530A CN112614530A CN202110004636.3A CN202110004636A CN112614530A CN 112614530 A CN112614530 A CN 112614530A CN 202110004636 A CN202110004636 A CN 202110004636A CN 112614530 A CN112614530 A CN 112614530A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The invention relates to a control method of a three-dimensional memory, the three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, each memory string comprises a plurality of memory units which are sequentially connected in series from top to bottom, each word line is connected with the memory units which are positioned at the same height in each memory string, and the method comprises the following steps: determining a target word line for verifying operation and reading operation; respectively applying a verification voltage and a read voltage to a target word line in a verification operation and a read operation; applying a first turn-on voltage to a first word line group adjacent to a target word line in a verify operation and a read operation; applying a second conduction voltage to at least one part of word lines in a second word line group adjacent to the target word line during verification operation and reading operation, wherein the memory cells connected with the target word line are connected between the memory cells connected with the first word line group and the second word line group; the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second conduction voltage is smaller than the first conduction voltage.
Description
Technical Field
The invention relates to a control method of a three-dimensional memory, which can effectively improve the reading interference of the three-dimensional memory.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
As market demands for memory density continue to increase, programming methods with more programming states are being developed so that each physical memory cell (cell) can represent more bits (bit) of information. However, the implementation of more programmed states has higher requirements on the formation process of a single memory cell and the distribution uniformity among multiple memory cells. Therefore, how to increase the storage density of the memory cells and improve the performance of the three-dimensional memory is a technical problem to be solved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a control method of a three-dimensional memory, which can effectively improve the reading interference of the three-dimensional memory.
The present invention provides a method for controlling a three-dimensional memory to solve the above technical problem, where the three-dimensional memory includes a plurality of memory strings and a plurality of word lines, each memory string includes a plurality of memory cells connected in series from top to bottom, and each word line is connected to a memory cell in the same height in each memory string, and the method includes: determining a target word line for verifying operation and reading operation; applying a verify voltage and a read voltage to the target word line at the time of the verify operation and the read operation, respectively; applying a first turn-on voltage to a first group of word lines adjacent to the target word line at the time of the verify operation and the read operation; applying a second turn-on voltage to at least a part of word lines in a second word line group adjacent to the target word line during the verifying operation and the reading operation, wherein the memory cells connected with the target word line are connected between the memory cells connected with the first word line group and the second word line group; the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second on-voltage is smaller than the first on-voltage.
In an embodiment of the invention, when the second turn-on voltage is applied to only a part of the word lines in the second word line group, the first turn-on voltage is applied to the word lines in the second word line group to which the second turn-on voltage is not applied.
In an embodiment of the invention, the number of the word lines in the second word line group to which the second turn-on voltage is applied is 80% to 100% of the total number of the word lines in the second word line group.
In an embodiment of the invention, the word lines in the second word line group to which the second turn-on voltage is applied are consecutive word lines.
In an embodiment of the invention, the first turn-on voltage is applied to at least one word line in the second word line group close to the target word line.
In an embodiment of the invention, the first turn-on voltage is 6V to 8V.
In an embodiment of the invention, the second turn-on voltage is 5V to 7V.
In an embodiment of the invention, the magnitude of the second turn-on voltage is 85% to 100% of the magnitude of the first turn-on voltage.
In one embodiment of the present invention, the programming is either forward programming or reverse programming.
Another aspect of the present invention provides a three-dimensional memory, including a plurality of memory strings and a plurality of word lines, each of the memory strings including a plurality of memory cells connected in series from top to bottom, each of the word lines being connected to the memory cells in each of the memory strings at the same height, the three-dimensional memory further including: a control circuit configured to determine a target word line for performing a verify operation and a read operation; applying a verify voltage and a read voltage to the target word line at the time of the verify operation and the read operation, respectively; applying a first turn-on voltage to a first group of word lines adjacent to the target word line at the time of the verify operation and the read operation; applying a second turn-on voltage to at least a part of word lines in a second word line group adjacent to the target word line during the verifying operation and the reading operation, wherein the memory cells connected with the target word line are connected between the memory cells connected with the first word line group and the second word line group; the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second on-voltage is smaller than the first on-voltage.
In an embodiment of the invention, the number of the word lines in the second word line group to which the second turn-on voltage is applied is 80% to 100% of the total number of the word lines in the second word line group.
In an embodiment of the invention, the magnitude of the second turn-on voltage is 85% to 100% of the magnitude of the first turn-on voltage.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
the control method of the three-dimensional memory effectively improves the reading interference of the three-dimensional memory by applying the verification voltage and the reading voltage to the target word line respectively during the verification operation and the reading operation, applying the first conduction voltage to the unprogrammed first word line group adjacent to the target word line during the verification operation and the reading operation, and applying the second conduction voltage which is smaller than the first conduction voltage to at least one part of the programmed second word lines in the programmed second word line group adjacent to the target word line.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIGS. 1 and 2 are schematic diagrams of a control method of a three-dimensional memory;
FIG. 3 is a flowchart illustrating a method for controlling a three-dimensional memory according to an embodiment of the invention;
FIGS. 4 and 5 are schematic diagrams illustrating a control method of a three-dimensional memory according to an embodiment of the invention;
FIGS. 6 and 7 are schematic diagrams of another control method of a three-dimensional memory according to an embodiment of the invention;
fig. 8 is a diagram of a three-dimensional memory according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
Fig. 1 and 2 are schematic diagrams of a control method of a three-dimensional memory. Referring to fig. 1 and 2, in a current three-dimensional memory (e.g., 3D NAND flash), in a process of performing a read operation, one method is to apply a read voltage VRD to a selected layer word line (gate) and a pass voltage Vpass to a non-selected layer gate when reading data of a certain memory cell. Typically, the pass voltage Vpass reaches 6V or more, which causes a significant increase in threshold voltage after ten thousand read operations, especially for the erased state (L0) and the low programmed state, resulting in read errors. This is the read disturb/read disturb due to the turn-on voltage.
Experiments show that the read disturb is positively correlated with the voltage causing the read disturb, and the larger the voltage of the pass voltage Vpass is, the more serious the read disturb is. Therefore, the turn-on voltage needs to be lowered to suppress read disturb. However, lowering the turn-on voltage will make the back-pattern effect (back-pattern effect) more serious, and further cause the threshold voltage distribution to be widened, resulting in the loss of the read window (margin).
With continued reference to fig. 1 and 2, the back-mode effect is mainly caused by the different programming states of the memory cells above the memory cell corresponding to the word line of the selected middle layer during the verify operation and the read operation. For example, when performing a program verify operation on a word line WLn, memory cells corresponding to word lines WLn +1 and above are in an erased state, and when performing a read operation on the word line WLn, the memory cells corresponding to the word lines WLn +1 and above are already in a random pattern (random pattern) programmed state, which results in a significant increase in string resistance of the memory cells corresponding to the word lines WLn +1 and above during reading, thereby increasing a threshold voltage during reading and widening a threshold voltage distribution. At this time, if the read-time turn-on voltage is further lowered, the back-mode effect becomes more serious.
In view of the above problems, the following embodiments of the present invention provide a method for controlling a three-dimensional memory, which can effectively improve read disturb of the three-dimensional memory.
The three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, wherein each memory string comprises a plurality of memory cells which are sequentially connected in series from top to bottom, and each word line is connected with the memory cells which are positioned at the same height in each memory string. The control method of the three-dimensional memory comprises the following steps: determining a target word line for verifying operation and reading operation; respectively applying a verification voltage and a read voltage to a target word line in a verification operation and a read operation; applying a first turn-on voltage to a first word line group adjacent to a target word line in a verify operation and a read operation; and applying a second turn-on voltage to at least a portion of the word lines in a second word line group adjacent to the target word line during the verify operation and the read operation; the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second conduction voltage is smaller than the first conduction voltage.
Fig. 3 is a flowchart of a method for controlling a three-dimensional memory according to an embodiment of the invention. This control method will be described below with reference to fig. 3. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Referring to fig. 3, the method includes the steps of:
in step S10, the target word line for the verify operation and the read operation is determined.
In some examples, the three-dimensional memory may include a plurality of memory strings each including a plurality of memory cells connected in series from top to bottom, and a plurality of word lines each connected to the memory cells located at the same height in each of the memory strings.
Preferably, the three-dimensional memory may be a 3D NAND.
In one embodiment of the present invention, the programming may be forward programming or reverse programming. For example, forward programming may refer to a bottom-up programming order and reverse programming may refer to a top-down programming order, but the invention is not limited thereto.
Fig. 4 and 5 are schematic diagrams illustrating a control method of a three-dimensional memory according to an embodiment of the invention. In one example shown in fig. 4 and 5, the programming order of this programming is forward programming.
Fig. 6 and 7 are schematic diagrams of another control method of a three-dimensional memory according to an embodiment of the invention. In one example shown in fig. 6 and 7, the programming order of this programming is reverse programming.
Referring to fig. 4 to 7, a target word line WLn for performing a verify operation and a read operation is determined.
In step S20, a verify voltage and a read voltage are applied to the target word line in the verify operation and the read operation, respectively.
Referring to fig. 4 and 5, in an embodiment of the present invention, when programming is forward programming, a verify voltage Vpv and a read voltage VRD may be applied to a target word line WLn at the time of a verify operation and a read operation, respectively.
Referring to fig. 6 and 7, in another embodiment of the present invention, when programming is reverse programming, a verify voltage Vpv and a read voltage VRD may be applied to a target word line WLn at the time of a verify operation and a read operation, respectively.
Illustratively, the magnitude of the read voltage may be-2V to 4V, but the invention is not limited thereto.
In step S30, a first turn-on voltage is applied to a first word line group adjacent to a target word line during a verify operation and a read operation.
The memory cells connected to the word lines in the first word line group are in an unprogrammed state.
Referring to fig. 4 and 5, in an embodiment of the present invention, when programming is forward programming, a first pass voltage Vpass1 may be applied to a first word line group (i.e., word lines WLn +1 and above) adjacent to a target word line WLn at the time of a verify operation and a read operation. The memory cells connected to the word lines in the first word line group are in an unprogrammed state.
Referring to fig. 6 and 7, in another embodiment of the present invention, when programming is reverse programming, a first pass voltage Vpass1 may be applied to a first word line group (i.e., word lines WLn +1 and below) adjacent to a target word line WLn at the time of a verify operation and a read operation. The memory cells connected to the word lines in the first word line group are in an unprogrammed state.
In an embodiment of the invention, the magnitude of the first pass voltage Vpass1 may be 6V to 8V.
It should be understood that the size of the first pass voltage Vpass1 can be adjusted according to actual needs by those skilled in the art, and the invention is not limited thereto.
In step S40, a second turn-on voltage is applied to at least a portion of the second word lines in the second word line group adjacent to the target word line during the verify operation and the read operation.
The memory cells connected with the word lines in the second word line group are in a programmed state, and the second turn-on voltage is smaller than the first turn-on voltage.
Referring to fig. 4 and 5, in an embodiment of the present invention, when the programming is the forward programming, a second pass voltage Vpass2 may be applied to at least a portion of the second word line group (i.e., word lines WLn-1 and below) adjacent to the target word line WLn in the verifying operation and the reading operation. Wherein the memory cells connected to the word lines in the second word line group are in a programmed state.
It will be appreciated that the memory cells to which the target word line WLn is connected are connected between the memory cells to which the first set of word lines (i.e., word lines WLn +1 and above) and the second set of word lines (i.e., word lines WLn 1 and below) are connected.
Referring to fig. 6 and 7, in another embodiment of the present invention, when programming is reverse programming, a second pass voltage Vpass2 may be applied to at least a portion of a second word line group (i.e., word lines WLn-1 and above) adjacent to a target word line WLn at the time of a verify operation and a read operation. Wherein the memory cells connected to the word lines in the second word line group are in a programmed state.
The magnitude of the second pass voltage Vpass2 should be less than the first pass voltage Vpass1, i.e.:
Vpass2＝Vpass1-ΔVpass。
in an embodiment of the invention, the magnitude of the second pass voltage Vpass2 is 85% to 100% of the magnitude of the first pass voltage Vpass 1.
Preferably, the magnitude of the second pass voltage Vpass2 may be 5V to 7V.
It should be understood that the size of the second pass voltage Vpass2 can be adjusted according to actual needs by those skilled in the art, and the invention is not limited thereto.
Illustratively, referring to FIGS. 4 and 5, in one embodiment of the present invention, when programming is forward programming, the second set of word lines adjacent to the target word line WLn are word lines of word line WLn 1 and below. Here, the second pass voltage Vpass2 may be applied to only a portion of the word lines in the second word line group, or the second pass voltage Vpass2 may be applied to all the word lines in the second word line group.
Illustratively, referring to FIGS. 6 and 7, in another embodiment of the present invention, the second set of word lines adjacent to the target word line WLn are word lines of word line WLn 1 and above when programming is reverse programming. Here, the second pass voltage Vpass2 may be applied to only a portion of the word lines in the second word line group, or the second pass voltage Vpass2 may be applied to all the word lines in the second word line group.
Preferably, in the above embodiments of the present invention, the word lines of the second word line group to which the second pass voltage Vpass2 is applied are consecutive word lines.
In one example shown in FIGS. 4 and 5, the second pass voltage Vpass2 can be applied to both word lines WLn 1 and below, the second pass voltage Vpass2 can be applied to only word lines WLn 2 and below, or the second pass voltage Vpass2 can be applied to only word lines WLn 3 and below, and so on.
In one example shown in FIGS. 6 and 7, the second pass voltage Vpass2 can be applied to all word lines WLn 1 and above, the second pass voltage Vpass2 can be applied only to word lines WLn 2 and above, or the second pass voltage Vpass2 can be applied only to word lines WLn 3 and above, and so on.
In an embodiment of the present invention, when the second pass voltage Vpass2 is applied to only a portion of the word lines in the second word line group, the first pass voltage Vpass1 is applied to the word lines in the second word line group to which the second pass voltage Vpass2 is not applied.
For example, in one example shown in FIGS. 4 and 5, when the second pass voltage Vpass2 is applied only to word lines WLn 2 and below, the first pass voltage Vpass1 may be applied to word line WLn 1 at the same time; when the second pass voltage Vpass2 is applied only to word lines WLn 3 and below, the first pass voltage Vpass1 can be applied to word line WLn 1 and word line WLn 2 at the same time, and so on.
For another example, in one example shown in FIGS. 6 and 7, when the second pass voltage Vpass2 is applied only to word lines WLn 2 and above, the first pass voltage Vpass1 may be applied to word line WLn 1 at the same time; when the second pass voltage Vpass2 is applied only to word lines WLn 3 and above, the first pass voltage Vpass1 can be applied to word line WLn 1 and word line WLn 2 at the same time, and so on.
In some embodiments of the present invention, the first pass voltage Vpass1 may be applied to at least one word line in the second word line group close to the target word line WLn.
In an embodiment of the present invention, the number of word lines in the second word line group to which the second pass voltage Vpass2 is applied is 80% to 100% of the total number of word lines in the second word line group.
The control method of the three-dimensional memory of the invention applies the verification voltage Vpv and the read voltage VRD to the target word line WLn respectively during the verification operation and the read operation, applies the first conduction voltage Vpass1 to the unprogrammed first word line group adjacent to the target word line WLn during the verification operation and the read operation, and applies the second conduction voltage Vpass2 smaller than the first conduction voltage Vpass1 to at least a part of the programmed second word line group adjacent to the target word line WLn during the verification operation and the read operation, thereby effectively improving the read interference of the three-dimensional memory while ensuring that the back model effect is not deteriorated.
The flowchart shown in fig. 3 is used herein to illustrate the steps/operations performed by the control method according to an embodiment of the present application. It should be understood that these steps/operations are not necessarily performed in the exact order in which they are performed. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
The above embodiments of the present invention provide a method for controlling a three-dimensional memory, which can effectively improve the read interference of the three-dimensional memory.
Another aspect of the present invention is to provide a three-dimensional memory having less read disturb.
Fig. 8 is a diagram of a three-dimensional memory according to an embodiment of the invention. The three-dimensional memory will be described with reference to fig. 8. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
It should be noted that the above control method of the present invention can be implemented in, for example, the three-dimensional memory 800 shown in fig. 8 or a variation thereof, but the present invention is not limited thereto.
The three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, wherein each memory string comprises a plurality of memory cells which are sequentially connected in series from top to bottom, and each word line is connected with the memory cells which are positioned at the same height in each memory string. The three-dimensional memory also includes a control circuit 810.
Wherein the control circuit 810 is configured to: determining a target word line for verifying operation and reading operation; respectively applying a verification voltage and a read voltage to a target word line in a verification operation and a read operation; applying a first turn-on voltage to a first word line group adjacent to a target word line in a verify operation and a read operation; and applying a second turn-on voltage to at least a portion of the word lines in a second word line group adjacent to the target word line during the verify operation and the read operation; the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second conduction voltage is smaller than the first conduction voltage.
Preferably, the three-dimensional memory may be a 3D NAND.
In one embodiment of the present invention, the programming may be forward programming or reverse programming. For example, forward programming may refer to a bottom-up programming order and reverse programming may refer to a top-down programming order, but the invention is not limited thereto.
Referring to fig. 4 and 5, in an embodiment of the invention, when programming in the forward direction, the control circuit 810 may be configured to: determining a target word line WLn for verifying operation and reading operation; applying a verify voltage Vpv and a read voltage VRD to a target word line WLn at the time of a verify operation and a read operation, respectively; applying a first pass voltage Vpass1 to a first word line group (i.e., word lines WLn +1 and above) adjacent to a target word line WLn in which memory cells connected to the word lines in the first word line group are in an unprogrammed state at the time of a verify operation and a read operation; a second pass voltage Vpass2 is applied to at least a portion of the second word line group (i.e., word lines WLn-1 and below) adjacent to the target word line WLn in the verify operation and the read operation, wherein memory cells connected to the word lines in the second word line group are in a programmed state, and the second pass voltage Vpass2 is less than the first pass voltage Vpass 1.
Referring to fig. 6 and 7, in another embodiment of the present invention, when programmed to reverse programming, the control circuit 810 may be configured to: determining a target word line WLn for verifying operation and reading operation; applying a verify voltage Vpv and a read voltage VRD to a target word line WLn at the time of a verify operation and a read operation, respectively; applying a first pass voltage Vpass1 to a first word line group adjacent to a target word line WLn (i.e., word lines WLn +1 and below) at the time of a verify operation and a read operation, wherein memory cells connected to the word lines in the first word line group are in an unprogrammed state; a second pass voltage Vpass2 is applied to at least a portion of the second word line group (i.e., word lines WLn-1 and above) adjacent to the target word line WLn in the verify operation and the read operation, wherein memory cells connected to the word lines in the second word line group are in a programmed state, and the second pass voltage Vpass2 is less than the first pass voltage Vpass 1.
In an embodiment of the present invention, the number of word lines in the second word line group to which the second pass voltage Vpass2 is applied is 80% to 100% of the total number of word lines in the second word line group.
In an embodiment of the invention, the magnitude of the second pass voltage Vpass2 is 85% to 100% of the magnitude of the first pass voltage Vpass 1.
Other implementation details of the three-dimensional memory 800 of the present embodiment can refer to the embodiments described in fig. 3 to 7, and are not expanded herein. Those skilled in the art can make appropriate adjustments to the internal structure of the three-dimensional memory 800 according to actual needs, and the invention is not limited thereto.
The three-dimensional memory 800 of the present invention can reduce read disturbance to the three-dimensional memory 800 while ensuring no degradation of the back model effect by configuring the control circuit 810 to apply the verify voltage Vpv and the read voltage VRD to the target word line WLn, respectively, and to apply the first pass voltage Vpass1 to the unprogrammed first word line group adjacent to the target word line WLn and to apply the second pass voltage Vpass2 smaller than the first pass voltage Vpass1 to at least a part of the programmed second word line group adjacent to the target word line WLn in the verify operation and the read operation.
The above embodiments of the present invention propose a three-dimensional memory whose read disturb is less.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
The computer-readable storage media referred to in this application may include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD)), smart cards, and flash memory devices (e.g., electrically erasable programmable read-only memory (EPROM), card, stick, key drive). In addition, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media (and/or storage media) capable of storing, containing, and/or carrying code and/or instructions and/or data.
It should be understood that the above-described embodiments are illustrative only. The embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and/or other electronic units designed to perform the functions described herein, or a combination thereof.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (12)
1. A control method of a three-dimensional memory, wherein the three-dimensional memory comprises a plurality of memory strings and a plurality of word lines, each memory string comprises a plurality of memory cells which are sequentially connected in series from top to bottom, each word line is connected with the memory cells which are positioned at the same height in each memory string, and the method comprises the following steps:
determining a target word line for verifying operation and reading operation;
applying a verify voltage and a read voltage to the target word line at the time of the verify operation and the read operation, respectively;
applying a first turn-on voltage to a first group of word lines adjacent to the target word line at the time of the verify operation and the read operation; and
applying a second turn-on voltage to at least a part of word lines in a second word line group adjacent to the target word line during the verifying operation and the reading operation, wherein the memory cells connected to the target word line are connected between the memory cells connected to the first word line group and the second word line group;
the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second on-voltage is smaller than the first on-voltage.
2. The control method according to claim 1, wherein when the second turn-on voltage is applied to only a part of the word lines in the second word line group, the first turn-on voltage is applied to the word lines in the second word line group to which the second turn-on voltage is not applied.
3. The control method according to claim 1, wherein the number of word lines in the second word line group to which the second turn-on voltage is applied is 80% to 100% of the total number of word lines in the second word line group.
4. The control method according to claim 1, wherein the word lines of the second word line group to which the second turn-on voltage is applied are consecutive word lines.
5. The control method according to claim 1, wherein the first turn-on voltage is applied to at least one word line in the second word line group that is close to the target word line.
6. The control method according to claim 1, wherein the first turn-on voltage has a magnitude of 6V to 8V.
7. The control method according to claim 1, wherein the second turn-on voltage has a magnitude of 5V to 7V.
8. The control method according to claim 1, wherein the magnitude of the second turn-on voltage is 85% to 100% of the magnitude of the first turn-on voltage.
9. Control method according to claim 1, characterized in that the programming is a forward programming or a reverse programming.
10. A three-dimensional memory, comprising a plurality of memory strings and a plurality of word lines, wherein each memory string comprises a plurality of memory cells connected in series from top to bottom, each word line is connected to a memory cell at the same height in each memory string, and the three-dimensional memory further comprises:
a control circuit configured to determine a target word line for performing a verify operation and a read operation; applying a verify voltage and a read voltage to the target word line at the time of the verify operation and the read operation, respectively; applying a first turn-on voltage to a first group of word lines adjacent to the target word line at the time of the verify operation and the read operation; applying a second turn-on voltage to at least a part of word lines in a second word line group adjacent to the target word line during the verifying operation and the reading operation, wherein the memory cells connected with the target word line are connected between the memory cells connected with the first word line group and the second word line group;
the memory cells connected with the word lines in the first word line group are in an unprogrammed state, the memory cells connected with the word lines in the second word line group are in a programmed state, and the second on-voltage is smaller than the first on-voltage.
11. The three-dimensional memory according to claim 10, wherein the number of word lines in the second word line group to which the second turn-on voltage is applied is 80% to 100% of the total number of word lines in the second word line group.
12. The three-dimensional memory according to claim 10, wherein the magnitude of the second turn-on voltage is 85% to 100% of the magnitude of the first turn-on voltage.
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