CN112613261A - Method for determining clock domain of block port - Google Patents
Method for determining clock domain of block port Download PDFInfo
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- CN112613261A CN112613261A CN202011553801.2A CN202011553801A CN112613261A CN 112613261 A CN112613261 A CN 112613261A CN 202011553801 A CN202011553801 A CN 202011553801A CN 112613261 A CN112613261 A CN 112613261A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
Abstract
The invention provides a method for determining a clock domain of a block port, which comprises the following steps: s1, obtaining timing report of each port in the STA tool; and S2, analyzing the obtained timing report in batches. The invention has the following beneficial effects: a method for determining clock domain of block port includes the steps of firstly, carrying out necessary setting on an STA tool, reading in a design netlist, and outputting timing report after analysis of the STA tool; and then, carrying out batch processing on the timing report to obtain the clock domain to which each port belongs, wherein the batch processing method can be written into an automatically executed script so as to be convenient for quick calling, and meanwhile, the method for automatically extracting the clock domain information of the ports by combining an STA tool and a script tool has universality, high efficiency and accuracy.
Description
Technical Field
The invention belongs to the technical field of static time sequence analysis of digital circuits, and particularly relates to a method for determining a clock domain of a block port.
Background
Digital integrated circuit products have penetrated the aspects of our daily lives, ranging from simple electric toys, street lamp control and the like to complex applications such as pos machines, smart phones, computers and the like, and the application scenes of the integrated circuits are very different, and the complexity of the integrated circuits is also very different. For complex application scenarios, the integration level of the integrated circuit is very high, for example, 153 hundred million transistors are integrated in the 5nm mobile phone processor kylin 9000. In the face of such a complex integrated circuit, hundreds of people may be needed to develop and develop a module design, the design process needs to adopt a modular design, the complex design is decomposed into a plurality of relatively simple functional modules, then the functional modules are designed and completed by different designers respectively, and then all the modules are integrated into a complete chip at the top layer. On the other hand, it is not practical for the EDA tool and the server running the EDA tool to directly perform chip-level design, and the entire complex design needs to be decomposed into relatively simple modules for computer-aided design.
In addition, the modular design has other advantages, such as the reuse of modules is facilitated, the development period is shortened, and the development cost is saved. It follows that modular design is a very important approach in complex chip design.
In the whole chip development process, a timing analysis (STA) is an important part, and directly determines whether the final chip can work normally. Performing timing analysis requires first determining the clock domain corresponding to each port. For modular designs, the clock domain to which the ports of the module belong needs to be provided to the synthesis and timing analyst by the designer. Designers typically extract manually through their own knowledge of the design, and this manual approach may be subject to errors. On the other hand, for IP obtained from other approaches, clock domain information of a port may not be provided or related information is not complete, which needs to be extracted by STA personnel themselves.
Summary of the invention
In view of this, the present invention provides a method for determining a clock domain of a block port, which automatically extracts port clock domain information by using an STA tool in combination with a script tool, and has universality, high efficiency and accuracy. Firstly, performing necessary setting on an STA tool, reading in a design netlist, and outputting a timing report after analysis by the STA tool; and then, carrying out batch processing on the timing report to obtain the clock domain to which each report belongs, wherein the batch processing method can be written into an automatically executed script so as to be convenient for quick calling.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a method of determining a block port clock domain, comprising the steps of:
s1, obtaining timing report of each port in the STA tool;
and S2, analyzing the obtained timing report in batches.
Further, step S1 is executed for obtaining the following information:
a1, all input and output ports except the clock port;
a2, timing report from each port to each clock domain;
when the information described in a2 is acquired, all clock groups, case analysis, disable timing, input delay, and output delay need to be removed in advance.
Further, when the information described in a2 is obtained, a temporary virtual clock, V _ TMP _ ADDED _ CLK, needs to be created after all clock groups, case analysis, disable timing, input delay, and output delay are removed, then an input delay on the V _ TMP _ ADDED _ CLK clock is set for all input ports, and an output delay on the V _ TMP _ ADDED _ CLK clock is set for all output ports, where the input delay and the output delay may be arbitrary values.
Further, when the information described in a2 is obtained, its timing to each clock domain is reported for each input port and its timing report is saved to a text i2clk _ timing.log, while its timing from each clock domain is reported for each output port and its timing report is saved to a text clk2o _ timing.log.
Further, the processing method for analyzing the obtained timing report in batches in step S2 includes:
b1, setting the delay value of each clock domain;
b2, preprocessing the texts i2clk _ timing.log and clk2o _ timing.log;
b3, generating sdc files of input delay and output delay;
b4, finally checking whether all the ports have a delay value set, and if any port has no delay value set, automatically setting a default value.
Further, the method for obtaining timing report of each port in the STA tool in step S1 includes:
c1, saving the output result of all _ inputs-exception _ clock _ ports into a file;
c2, remove clock group, case analysis, disable timing, input delay, output delay;
c3, creating a temporary virtual clock;
c4, setting input delay and output delay for the created virtual clock;
c5, reporting the timing of each input port to each clock domain, and the timing of each clock domain to each output port, and respectively storing the results in a file.
Further, the method for analyzing the obtained timing report in batch in step S2 includes:
d1, setting the delay value of each clock domain;
d2, analyzing the timing report output in the step S1 to find the path startpoint and endpoint;
d3, judging whether the rows of startpoint and endpoint contain clock at the same time, if so, performing the step D4, otherwise, extracting the row and the next row and then performing the step D5;
d4, only extracting the line, and changing the clock of the line to facilitate subsequent processing;
d5, extracting relevant information from the extracted rows to generate sdc;
d6, judging that all input ports and output ports are set with delay, if yes, ending, otherwise, executing step D7;
d7, setting delay for the unset ports separately, and ending.
Compared with the prior art, the method for determining the clock domain of the block port has the following advantages that:
(1) the method for determining the clock domain of the block port, which is created by the invention, is a method for automatically extracting the port clock domain information by combining an STA tool with a script tool, and has universality, high efficiency and accuracy.
(2) The method for determining the clock domain of the block port is characterized by comprising the steps of firstly, carrying out necessary setting on an STA tool, reading in a design netlist, and outputting a timing report after analysis by the STA tool; and then, carrying out batch processing on the timing report to obtain the clock domain to which each report belongs, wherein the batch processing method can be written into an automatically executed script so as to be convenient for quick calling.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the invention without limitation. In the drawings:
fig. 1 is a schematic diagram of a method for determining a clock domain of a block port according to an embodiment of the present invention;
fig. 2 is a schematic diagram of obtaining timing report of each port in the STA tool according to the embodiment of the present invention;
fig. 3 is a schematic diagram of batch analysis processing on the obtained timing report according to the embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
The invention will be described in detail with reference to the following embodiments with reference to the attached drawings.
As shown in fig. 1 to fig. 3, the present invention provides a method for automatically extracting port clock domain information by using an STA tool in combination with a script tool, which has versatility, efficiency, and accuracy. Firstly, performing necessary setting on an STA tool, reading in a design netlist, and outputting a timing report after analysis by the STA tool; and then carrying out batch processing on the timing report to obtain the clock domain to which each port belongs. Batch processing methods can be written as an automatically executed script to facilitate quick invocation.
The solution of the invention is as follows: the whole system comprises two stages, wherein in the stage 1, timing report of each port needs to be analyzed in an STA tool; in the phase 2, batch analysis processing needs to be performed on the timing ports obtained in the phase 1, so as to obtain the clock domains to which the ports belong.
For the clock domain information of the port extracted by the designer, whether the extracted information is wrong or not can be checked by the method. For the IP without port clock domain information, corresponding information can be extracted by the method.
In the stage 1, all non-clock inputs and outputs need to be obtained through an STA tool, and the STA tool is used for checking whether all inputs have input delay and all outputs have output delay values in the stage 2.
In phase 1, timing report from each port to each clock domain needs to be obtained through an STA tool, and this information is used for phase 2 batch analysis processing. For timing report of input2clock, clock of path's startpoint, endpoint and endpoint is used to extract the clock domain to which each input port belongs. For timing report of clock2output, the path's startpoint, startpoint's clock and endpoint are used to extract the clock domain to which each output port belongs.
Batch processing at stage 2 is an analysis based on stage 1 STA output information. Setting the delay value for each clock domain may be used to generate the delay constraints for all ports. Preprocessing the texts i2clk _ timing.log and clk2o _ timing.log has the function of formatting the useful information in timing report, namely startpoint and its clock, endpoint and its clock, and outputting the formatted information to an intermediate file for later use. When sdc of input delay and output delay is generated, an intermediate file needs to be read in and a formatted startpoint and a clock thereof, endpoint and a clock thereof are analyzed, so that delay constraint from each input port to all relevant clock domains is obtained. Checking if all ports have a delay value set is because paths for some input2output are not available through the above analysis, and input delay, output delay need to be set separately.
A method of determining a block port clock domain, comprising the steps of:
s1, obtaining timing report of each port in the STA tool;
and S2, analyzing the obtained timing report in batches.
Step S1 is executed for acquiring the following information:
a1, all input and output ports except the clock port;
a2, timing report from each port to each clock domain;
when the information described in a2 is acquired, all clock groups, case analysis, disable timing, input delay, and output delay need to be removed in advance.
When the information described in a2 is obtained, a temporary virtual clock, V _ TMP _ ADDED _ CLK, needs to be created after all clock groups, case analysis, disable timing, input delay, and output delay are removed, then an input delay on the V _ TMP _ ADDED _ CLK clock is set for all input ports, and an output delay on the V _ TMP _ ADDED _ CLK clock is set for all output ports, where the input delay and the output delay may be any values.
When the information described in a2 is obtained, for each input port, its timing to each clock domain is reported and its timing report is saved to a text i2clk _ timing.log, while for each output port, its timing from each clock domain is reported and its timing report is saved to a text clk2o _ timing.log.
The processing method for analyzing and processing the obtained timing report in batch in step S2 includes:
b1, setting the delay value of each clock domain;
b2, preprocessing the texts i2clk _ timing.log and clk2o _ timing.log;
b3, generating sdc files of input delay and output delay;
b4, finally checking whether all the ports have a delay value set, and if any port has no delay value set, automatically setting a default value.
The method for obtaining timing report of each port in the STA tool in step S1 includes:
c1, saving the output result of all _ inputs-exception _ clock _ ports into a file;
c2, remove clock group, case analysis, disable timing, input delay, output delay;
c3, creating a temporary virtual clock;
c4, setting input delay and output delay for the created virtual clock;
c5, reporting the timing of each input port to each clock domain, and the timing of each clock domain to each output port, and respectively storing the results in a file.
The method for analyzing and processing the obtained timing report in batch in step S2 includes:
d1, setting the delay value of each clock domain;
d2, analyzing the timing report output in the step S1 to find the path startpoint and endpoint;
d3, judging whether the rows of startpoint and endpoint contain clock at the same time, if so, performing the step D4, otherwise, extracting the row and the next row and then performing the step D5;
d4, only extracting the line, and changing the clock of the line to facilitate subsequent processing;
d5, extracting relevant information from the extracted rows to generate sdc;
d6, judging that all input ports and output ports are set with delay, if yes, ending, otherwise, executing step D7;
d7, setting delay for the unset ports separately, and ending.
In the specific implementation process, the invention integrally comprises two stages: in the stage 1, timing reports between all ports and all clock domains need to be obtained in an STA tool, and in the stage 2, batch analysis processing needs to be performed on the timing reports obtained in the stage 1, as shown in fig. 1.
In phase 1, the STA tool is used to perform the following operations (taking synopsys tool PrimeTime as an example):
1. obtaining all input ports and output ports except clock;
2. remove all clock groups, case analysis, disable timing, input delay, output delay;
3. creating a temporary virtual clock-V _ TMP _ ADDED _ CLK;
4. setting an input delay on one V _ TMP _ ADDED _ CLK clock for all input ports and an output delay on one V _ TMP _ ADDED _ CLK clock for all output ports;
5. for each input port its timing to each clock domain is reported and the timing report is saved into one text i2clk _ timing. Reporting its timing from each clock domain for each output port and saving the timing report into one text clk2o _ timing.
Phase 2, in turn, performs the following operations (which may be scripted):
1. the delay value for each clock domain is set to generate the delay constraints for all ports.
2. Preprocessing the texts i2clk _ timing.log and clk2o _ timing.log, wherein the preprocessing flow is as follows
3. when generating an input delay, the name of the input port needs to be extracted according to the startpoint keyword, and the clock domain to which the input port belongs is extracted according to the keyword in endpoint. Each time an input port is fetched, it needs to be compared with all the ports that have been fetched before (stored in a queue input _ ports _ ary), so as to determine which ports belong to multiple clock domains, and then the currently fetched port is also put into the input _ ports _ ary. And finally, generating sdc of the input delay according to the extracted input port and end clock. When generating output delay, it needs to extract the name of input clock according to startpoint keyword, and extract output port according to keyword in endpoint. After each output port is extracted, it needs to be compared with all ports (stored in a queue output _ ports _ ary) extracted before, so as to determine which ports belong to multiple clock domains, and then the currently extracted port is also put into output _ ports _ ary. And finally, generating sdc of output delay according to the extracted input clock and the endpoint port.
4. It is checked whether all ports have a delay value set. Since the path for input2output is not available through the above analysis, it is necessary to separately set input delay and output delay. All ports FOR which no delay value is set are set to one V _ AUTO _ FOR _ IODELAY _ CLK in this step.
The following are descriptions of specific terms involved in the present invention:
block: and (5) modules. In the integrated circuit design, only the whole chip design stage is divided into a plurality of parts which are respectively designed, and each part is a block.
port: a port. The external interfaces of the block and the external interfaces of the top layer of the whole chip are all ports.
STA: static Timing Analysis. Static timing analysis, a step in the design of integrated circuits, analyzes whether the timing of the circuit violates a rule.
timing report: and reporting the time sequence. The STA tool analyzes the report output after the timing sequence is ended.
input port: an input signal port of the module.
output port: an output signal port of the module.
clock _ group: one of the constraints required by the STA analysis tool.
case _ analysis: one of the constraints required by the STA analysis tool.
disable _ timing: one of the constraints required by the STA analysis tool.
virtual clock: virtual clock, one of the constraints required by the STA analysis tool.
scdc: synopsys designs, Synopsys corporation synthesis/STA/P & R tool constraint file.
EDA (electronic design automation): electronic design automation, Electronic design automation.
In the several embodiments provided in the present application, it should be understood that the disclosed method and system may be implemented in other ways. For example, the above described division of elements is merely a logical division, and other divisions may be realized, for example, multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not executed. The units may or may not be physically separate, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the invention, so that any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present invention, should be included in the scope of the present invention.
Claims (7)
1. A method of determining a block port clock domain, comprising the steps of:
s1, obtaining timing report of each port in the STA tool;
and S2, analyzing the obtained timing report in batches.
2. The method of determining a block port clock domain of claim 1, wherein step S1 is performed to obtain the following information:
a1, all input and output ports except the clock port;
a2, timing report from each port to each clock domain;
when the information described in a2 is acquired, all clock groups, case analysis, disable timing, input delay, and output delay need to be removed in advance.
3. The method of determining a block port clock domain of claim 2, wherein: when the information described in a2 is obtained, a temporary virtual clock, V _ TMP _ ADDED _ CLK, needs to be created after all clock groups, case analysis, disable timing, input delay, and output delay are removed, then an input delay on the V _ TMP _ ADDED _ CLK clock is set for all input ports, and an output delay on the V _ TMP _ ADDED _ CLK clock is set for all output ports, where the input delay and the output delay may be any values.
4. A method of determining a block port clock domain according to claim 3, wherein: when the information described in a2 is obtained, for each input port, its timing to each clock domain is reported and its timing report is saved to a text i2clk _ timing.log, while for each output port, its timing from each clock domain is reported and its timing report is saved to a text clk2o _ timing.log.
5. The method of claim 1, wherein the processing method for performing batch analysis processing on the obtained timing report in step S2 comprises:
b1, setting the delay value of each clock domain;
b2, preprocessing the texts i2clk _ timing.log and clk2o _ timing.log;
b3, generating sdc files of input delay and output delay;
b4, finally checking whether all the ports have a delay value set, and if any port has no delay value set, automatically setting a default value.
6. The method of claim 1, wherein the step S1 of obtaining timing report of each port in the STA tool comprises:
c1, saving the output result of all _ inputs-exception _ clock _ ports into a file;
c2, remove clock group, case analysis, disable timing, input delay, output delay;
c3, creating a temporary virtual clock;
c4, setting input delay and output delay for the created virtual clock;
c5, reporting the timing of each input port to each clock domain, and the timing of each clock domain to each output port, and respectively storing the results in a file.
7. The method of claim 1, wherein the step S2 of analyzing the obtained timing ports in batch comprises:
d1, setting the delay value of each clock domain;
d2, analyzing the timing report output in the step S1 to find the path startpoint and endpoint; d3, judging whether the rows of startpoint and endpoint contain clock at the same time, if so, performing the step D4, otherwise, extracting the row and the next row and then performing the step D5;
d4, only extracting the line, and changing the clock of the line to facilitate subsequent processing;
d5, extracting relevant information from the extracted rows to generate sdc;
d6, judging that all input ports and output ports are set with delay, if yes, ending, otherwise, executing step D7;
d7, setting delay for the unset ports separately, and ending.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050039094A1 (en) * | 2003-08-12 | 2005-02-17 | Lsi Logic Corporation | Static timing analysis approach for multi-clock domain designs |
| CN102169515A (en) * | 2010-02-26 | 2011-08-31 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
| CN106682285A (en) * | 2016-12-09 | 2017-05-17 | 深圳市紫光同创电子有限公司 | Static timing analysis method and device |
| CN109948221A (en) * | 2019-03-12 | 2019-06-28 | 天津芯海创科技有限公司 | A kind of method of top layer exact constraint block port timing |
| US10467365B1 (en) * | 2017-04-10 | 2019-11-05 | Cadence Design Systems, Inc. | Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050039094A1 (en) * | 2003-08-12 | 2005-02-17 | Lsi Logic Corporation | Static timing analysis approach for multi-clock domain designs |
| CN102169515A (en) * | 2010-02-26 | 2011-08-31 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
| CN106682285A (en) * | 2016-12-09 | 2017-05-17 | 深圳市紫光同创电子有限公司 | Static timing analysis method and device |
| US10467365B1 (en) * | 2017-04-10 | 2019-11-05 | Cadence Design Systems, Inc. | Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design |
| CN109948221A (en) * | 2019-03-12 | 2019-06-28 | 天津芯海创科技有限公司 | A kind of method of top layer exact constraint block port timing |
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