CN112612500A

CN112612500A - Method and device for upgrading BMC, electronic equipment and storage medium

Info

Publication number: CN112612500A
Application number: CN202011603618.9A
Authority: CN
Inventors: 林志捷
Original assignee: Ruijie Networks Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-04-06

Abstract

The embodiment of the invention provides a method and a device for upgrading BMC, electronic equipment and a storage medium. The method comprises the following steps: opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB; and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register. According to the method for upgrading BMC provided by the embodiment of the invention, the channel from LPC to AHB is opened, so that the register on BMC to be upgraded is controlled by the AHB to finish BMC upgrading operation, and the time for upgrading BMC from a CPU side is shortened.

Description

Method and device for upgrading BMC, electronic equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a method and a device for upgrading BMC, electronic equipment and a storage medium.

Background

The BMC (Board Management Controller) is a device monitoring system, and mainly monitors the state of a device through various basic interfaces, such as the temperature, voltage, power supply, and the like of a CPU, and performs corresponding adjustment work when system hardware is abnormal, so as to ensure that the device is in a healthy state.

At present, a firmware program of the BMC is stored in a flash on a motherboard, a socflash program provided by an advanced peripheral equipment (asped) is used for upgrading the BMC from a Central Processing Unit (CPU) side, a certain block address of the flash is erased and then programmed, read-back verification is performed after programming is completed, and then the next block address of the flash is erased until the whole flash programming verification is completed, however, the time for upgrading the BMC is long, and generally about 16-20 minutes is required. And since soclash is a third party tool, it cannot be optimized.

Disclosure of Invention

Aiming at the defects in the prior art, the embodiment of the invention provides a method and a device for upgrading BMC, electronic equipment and a storage medium.

In a first aspect, an embodiment of the present invention provides a method for upgrading a BMC, including:

opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB;

and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register.

As in the foregoing method, optionally, the register on the BMC to be upgraded includes: a register of FMC on the BMC to be upgraded;

correspondingly, the sending of the upgrade instruction to the register on the BMC to be upgraded controls the BMC to be upgraded to complete the upgrade process through the register, including:

sending an erasing instruction to a register on the FMC, and controlling the BMC to be upgraded to erase an original program in the flash through the register;

after the erasure is finished, sending a programming instruction to a register on the FMC, and writing an upgrading program into the flash through the register;

and after the writing is finished, sending a checking instruction to a register on the FMC, and controlling the BMC to be upgraded to finish upgrading checking through the register.

As in the foregoing method, optionally, the register on the BMC to be upgraded further includes: the register of the SCU on the BMC to be upgraded;

correspondingly, before sending the erasing instruction to the register on the FMC, the method further includes:

and controlling a register of the SCU on the BMC to be upgraded so as to close the CPU enable on the BMC to be upgraded.

As in the foregoing method, optionally, before the sending the erasure instruction to the register on the FMC, the method further includes:

controlling a first register of the FMC to turn on FMC write enable.

As above, optionally, after the FMC write enable is turned on, the method further includes:

and controlling a second register of the FMC so that the FMC can generate a first SPI writing instruction according to the second register and send the first SPI writing instruction to the flash to enable the flash to start flash writing.

As above, optionally, after the starting of the flash write enable, the method further includes:

controlling a second register of the FMC so that the FMC can generate a first SPI reading instruction according to the second register and send the first SPI reading instruction to a flash;

and verifying the write enable of the flash according to the first value returned by the flash.

Optionally, in the foregoing method, the sending an erase instruction to a register on the FMC, and controlling the BMC to be upgraded to erase an original program in the flash through the register includes:

controlling a second register of the FMC so that the FMC can generate an SPI erasing instruction according to the second register and send the SPI erasing instruction to a flash so as to erase an original program in the flash;

controlling a second register of the FMC so that the FMC can generate a second SPI reading instruction according to the second register and send the second SPI reading instruction to a flash;

and verifying the writing process flag bit and the erasing success flag bit of the register of the flash according to the second numerical value returned by the flash, and judging whether the erasing is successful.

As in the above method, optionally, after the erasing is completed and before the writing instruction is sent to the register on the FMC, the method further includes:

and controlling a second register of the FMC to modify the programming mode of the flash into a user mode.

As in the above method, optionally, the sending a write instruction to a register on the FMC includes:

controlling a second register of the FMC so that the FMC can generate a second SPI writing instruction according to the second register, and writing a program to be upgraded into the flash through the second SPI writing instruction;

and checking the writing process flag bit and the programming success flag bit of the flash register, and judging whether programming is successful or not.

As in the foregoing method, optionally, the controlling a second register of the FMC so that the FMC generates a second SPI write instruction according to the second register, and writing the program to be upgraded into the flash by using the second SPI write instruction includes:

modifying the value of a second register of the FMC so that the FMC can determine an SPI instruction to be sent as a write instruction according to the value of the second register;

sending a program to be upgraded to a second register of the FMC through a data line of the AHB;

and sending an address to be written into a flash to a second register of the FMC through a data line of the AHB, so that the FMC can generate a second SPI writing instruction according to the program to be upgraded and the address and send the second SPI writing instruction to the flash.

As for the foregoing method, optionally, the sending a check instruction to a register on the FMC, and controlling the BMC to be upgraded through the register to complete upgrade check includes:

controlling a second register of the FMC so that the FMC can generate a third SPI reading instruction according to the second register and send the third SPI reading instruction to a flash;

and judging whether the programming program returned by the flash is the same as the program to be upgraded, and if so, successfully verifying.

As above, optionally, after the BMC to be upgraded is controlled by the register to complete the upgrade process, the method further includes:

and restarting the BMC.

As above method, optionally, after the opening the LPC to AHB channel, the method further includes:

closing a watchdog program of the BMC;

accordingly, the rebooting the BMC includes:

restarting a watchdog program of the BMC so as to restart the BMC.

As above, optionally, after the restarting of the BMC, the method further includes:

and controlling a register of the SCU on the BMC so as to start the CPU enable on the BMC to be upgraded.

As above, optionally, after the restarting the watchdog program of the BMC, the method further includes:

the LPC to AHB channel is closed.

In a second aspect, an embodiment of the present invention provides an apparatus for upgrading a BMC, including:

the starting module is used for starting a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB;

and the sending module is used for sending an upgrading instruction to a register on the BMC to be upgraded and controlling the BMC to be upgraded to finish the upgrading process through the register.

As with the foregoing device, optionally, the register on the BMC to be upgraded includes: a register of FMC on the BMC to be upgraded;

accordingly, the sending module comprises:

the erasing unit is used for sending an erasing instruction to a register on the FMC and controlling the BMC to be upgraded to erase an original program in the flash through the register;

the programming unit is used for sending a programming instruction to a register on the FMC after the erasing is finished, and writing an upgrading program into the flash through the register;

and the checking unit is used for sending a checking instruction to a register on the FMC after the writing is finished, and controlling the BMC to be upgraded to finish upgrading checking through the register.

As with the above apparatus, optionally, the register on the BMC to be upgraded further includes: the register of the SCU on the BMC to be upgraded;

correspondingly, the device further comprises:

and the first control module is used for controlling the register of the SCU on the BMC to be upgraded before sending an erasing instruction to the register on the FMC so as to close the CPU enabling on the BMC to be upgraded.

The above apparatus, optionally, further comprises:

and the second control module is used for controlling the first register of the FMC before sending an erasing instruction to the register on the FMC so as to start FMC write enabling.

The above apparatus, optionally, further comprises:

and the third control module is used for controlling a second register of the FMC after the FMC is started to write the enable, so that the FMC can generate a first SPI writing instruction according to the second register and send the first SPI writing instruction to the flash, and the flash can start the flash to write the enable.

As in the above device, optionally, the third control module is further configured to:

after the flash write enable is started, controlling a second register of the FMC so that the FMC can generate a first SPI reading instruction according to the second register and send the first SPI reading instruction to the flash;

As with the apparatus described above, optionally, the erasing unit is specifically configured to:

and after the erasing is finished and before a programming instruction is sent to the register on the FMC, controlling a second register of the FMC to modify the programming mode of the flash into a user mode.

As with the device above, optionally, the programming unit specifically includes:

the instruction generation subunit is used for controlling a second register of the FMC, so that the FMC can generate a second SPI writing instruction according to the second register, and a program to be upgraded is written into the flash through the second SPI writing instruction;

and the verifying subunit is used for verifying the writing process flag bit and the programming success flag bit of the flash register and judging whether programming is successful or not.

Optionally, in the foregoing apparatus, the instruction generating subunit is specifically configured to:

Optionally, as with the apparatus above, the verification unit is specifically configured to:

The above apparatus, optionally, further comprises:

and the restarting module is used for restarting the BMC after controlling the BMC to be upgraded to finish the upgrading process through the register.

The above apparatus, optionally, further comprises:

the closing module is used for closing the watchdog program of the BMC after opening the channel from the LPC to the AHB;

correspondingly, the restart module is specifically configured to:

restarting a watchdog program of the BMC so as to restart the BMC.

The above apparatus, optionally, further comprises:

and the starting module is used for controlling a register of the SCU on the BMC after the BMC is restarted so as to start the CPU enable on the BMC to be upgraded.

As with the apparatus above, optionally, the shutdown module is further configured to:

and after restarting the watchdog program of the BMC, closing the passage from the LPC to the AHB.

In a third aspect, an embodiment of the present invention provides an electronic device, including:

the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform a method comprising: opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB; and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register.

In a fourth aspect, an embodiment of the present invention provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following method: opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB; and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register.

According to the method for upgrading BMC provided by the embodiment of the invention, the channel from LPC to AHB is opened, so that the register on BMC to be upgraded is controlled by the AHB to finish BMC upgrading operation, and the time for upgrading BMC from a CPU side is shortened.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

Fig. 1 is a schematic flow chart of a method for upgrading a BMC according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for upgrading a BMC according to another embodiment of the invention;

fig. 3 is a schematic structural diagram of a device for upgrading a BMC according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic flow chart of a method for upgrading a BMC according to an embodiment of the present invention, and as shown in fig. 1, the method includes:

step S11, opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB;

and step S12, sending an upgrade instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to finish the upgrade process through the register.

Specifically, in the electronic device, the BMC is configured to monitor a CPU parameter, and meanwhile, the BMC may also be upgraded by using the CPU, in order to shorten the time for upgrading the BMC from the CPU side, an embodiment of the present invention provides a method for upgrading the BMC, which is applied to the CPU side, the CPU may be an X86D 15XX series, the operating system may be an Open network operating System (SONIC) system, and the SONIC is an Open source network operating system based on Linux, and is capable of adapting to switching devices from different manufacturers and providing rich network functions.

To upgrade the BMC from the CPU side, first, the LPC (Low pin count Bus) is started to control the Advanced High performance Bus (AHB), and then all registers of the BMC side can be operated. The AHB Bus protocol is part of the AMBA (Advanced Microcontroller Bus Architecture) protocol, and an AHB Bus system includes: AHB master, AHB slave, arbiter and decoder. The master of the AHB is able to initiate read and write operations to the slaves, and the slaves return the results (success or failure) of the operations to the master. The AHB arbiter ensures that only one host can initiate a command request at a time to prevent collisions. The decoder can decode according to the transmitted address and then generate a corresponding slave chip selection signal, and the AHB bus is connected with the CPU and the slave equipment under the BMC, so that the AHB is controlled to read and write the registers of the slave equipment at the BMC end from the CPU end, namely the register of the BMC is an AHB slave.

Specifically, a channel from the CPU side to the LPC to the AHB is opened by setting bit [0] of a register 30 of the SuperIO to 1 mainly through the LPC of the CPU, the LPC is the CPU side, the SuperIO is the BMC side, and the local device0D in the SuperIO function of the LPC interface and the BMC: the iLPC2AHB (LPC to AHB bridge) may implement read/write operations to all registers inside the BMC.

And then the CPU can send an upgrading instruction to a register on the BMC to be upgraded through the AHB, specifically, the CPU can modify the value of the corresponding register through the AHB by referring to each register parameter table of the BMC to realize the corresponding function, so that the BMC to be upgraded is controlled through the register to complete the upgrading process.

On the basis of the above embodiment, further, the register on the BMC to be upgraded includes: a register of FMC on the BMC to be upgraded;

Specifically, an FMC (firmware SPI Memory controller) is an SPI (Serial Peripheral Interface) controller of BMC firmware and is a slave under an AHB bus, so that an address line and a data line of the FMC are the address line and the data line of the AHB, the FMC is mainly used for controlling a flash Memory flash of the BMC, and after starting a channel from LPC to AHB, the FMC is used as the slave of the AHB and can control a register of the FMC by sending an instruction to the AHB bus, thereby controlling the FMC to implement a corresponding function. In the embodiment of the invention, an erasing instruction is sent to a register on an FMC through an AHB, and the BMC to be upgraded is controlled through the register to erase an original program in a flash, wherein the flash is a preset flash which is specially used for storing a BMC upgrading program, or is set by a user. After the erasure is finished, sending a programming instruction to a register on the FMC, and writing an upgrading program into the flash through the register; and after the writing is finished, sending a checking instruction to a register on the FMC, and controlling the BMC to be upgraded to finish upgrading checking through the register. Different from the modes of block erasing, programming and checking of the socflash in the prior art, the embodiment of the invention carries out checking operation after the flash programming of the BMC is finished, and checks the comparison between the flash content and the upgrading program after the upgrading program is written into the flash, thereby shortening the upgrading time of the BMC.

On the basis of the foregoing embodiments, further, the register on the BMC to be upgraded further includes: the register of the SCU on the BMC to be upgraded;

Specifically, in order to prevent the BMC from operating the flash to cause data confusion, all operations of the CPU at the BMC need to be masked, so before the upgrade, a register of a System Control Unit (SCU) on the BMC to be upgraded needs to be controlled so as to close the CPU enable on the BMC to be upgraded, the SCU is a controller on the BMC and is also a slave of the AHB, the slave under the AHB is a data and address line, addresses of the slaves are different, and a chip selection function is realized through a decoder built in the AHB, which is not described herein again. The SCU is mainly used for controlling the BMC system, and specifically, bit [0] of a 0x70 register of the SCU is set to be 1 to close CPU enabling on the BMC to be upgraded.

On the basis of the foregoing embodiments, further before sending the erasure instruction to the register on the FMC, the method further includes:

controlling a first register of the FMC to turn on FMC write enable.

Specifically, before sending the erasure instruction to the register on the FMC, the write enable of the FMC to the flash needs to be started, so that the instruction can be sent to the flash through the FMC. When writing enable of the FMC is started, firstly writing address filtering control of the FMC is enabled to unlock writing enable protection of the FMC, specifically, a 0xA4 register of the FMC is set to be 0x2aa, then writing enable of the FMC to the flash is enabled, specifically, bit [18:16] of a 0x00 register of the FMC is set to be 0x7, writing enable of the FMC to the flash is started, filtering of writing addresses is not required to be started in an actual upgrading process, writing enable is started only for starting writing enable of the FMC, the writing enable can be operated only under the condition that the writing address filtering is started, therefore, after the writing enable is started, writing enable protection of the FMC also needs to be closed, namely, the 0xA4 register of the FMC is set to be 0.

In practical application, after the FMC write enable is turned on, the flag bits of the address protection and the illegal command are also cleared, and specifically, the bit10 and the bit9 of the FMC08 register are written as 0 to clear the flag bits of the address protection and the illegal command. In addition, the data mode needs to be changed into four bytes, specifically, the value of the FMC0C register is set to 0 to configure the SPI of the FMC to be 4bytes mode, and the 0x00000007 is written in the 0x1E620004 register of the FMC to configure the SPI of Flash to be 4bytes mode. Therefore, the FMC can send instructions to the flash, and the flash is operated.

On the basis of the foregoing embodiments, further, after the starting of FMC write enable, the method further includes:

Specifically, after the FMC enable is started, the write enable of the flash needs to be started through the FMC, so that the flash can be operated to erase or write, specifically, the FMC sends an SPI instruction to the flash to control the flash, and the SPI instruction format is as follows: the method comprises the steps of commanding CMD, ADDRESS and DATA DATA, namely | CMD | ADDRESS | DATA |, wherein CMD is a specific command, ADDRESS is an ADDRESS of a flash in a write operation, DATA is written DATA, and when FMC controls the flash to start write enabling, specific DATA do not need to be written. Specifically, first, the FMC0C register is written into the DATA line and ADDRESS line of FF-off SPI by AHB, and then bit [1:0] of FMC10 register is set to 02 by AHB, so that the FMC command is in write mode, wherein set to 01 is read mode, set to 11 user mode, and the subsequent upgrade process will be used. The flash write enables block erasing by writing 0xD8 into the flash and whole erasing by writing 0x60 into the flash, commands of different manufacturers may be different, and the flash write enables adjustment according to actual conditions. Therefore, when flash write enable needs to be started, an instruction 0xD8 or 0x60 needs to be written into bit [23:16] of an FMC10 register through an AHB, then an SPI write instruction is generated by the FMC register and recorded as a first SPI write instruction, the first SPI write instruction is sent to the flash, and after the flash receives the first SPI write instruction, the flash write enable is started according to CMD in the instruction. Finally, the FMC0C register is written to the DATA line and ADDRESS line of 00 turn-on SPI by AHB. It should be noted that, in the normal read/write mode, the DATA line and ADDRESS line of the SPI need to be turned off before the read/write command is sent, and the DATA line and ADDRESS line of the SPI need to be turned on after the command is sent, which is not described in detail later.

On the basis of the foregoing embodiments, further, after the flash write enable is started, the method further includes:

Specifically, after flash write enable is started, whether the write enable is started successfully needs to be checked, firstly, bit [1:0] of an FMC10 register is set to be 01 through an AHB, an FMC instruction is in a read mode, an instruction 0x05 needs to be written into bit [23:16] of an FMC10 register through the AHB, then the FMC register generates an SPI read instruction which is recorded as a first SPI read instruction, the first SPI read instruction is sent to a flash, after the flash receives the first SPI read instruction, the value of a write enable check bit WEL can be read according to CMD in the instruction, the CPU reads DATA returned by the flash from a DATA line of the AHB, the bit1 numerical value of the returned DATA is checked, and if the value is 1, the flash write enable is started successfully.

On the basis of the foregoing embodiments, further, the sending an erasing instruction to the register on the FMC, and controlling the BMC to be upgraded to erase the original program in the flash through the register includes:

Specifically, after the write enable is successfully started by verifying the flash, the flash can be erased, and the original program in the flash is erased. Firstly, setting bit [1:0] of an FMC10 register to be 02 through an AHB, enabling an FMC command to be in a write mode, writing a command 0xd8 into bit [23:16] of an FMC10 register through the AHB, then generating an SPI write command through the FMC register, recording the SPI write command as an SPI erasing command, sending the SPI erasing command to a flash, and erasing an original program after the flash receives the SPI erasing command.

And then whether the erasing operation of the flash is successful is also checked. Firstly, setting bit [1:0] of an FMC10 register to be 01 through an AHB, enabling an FMC instruction to be In a read mode, writing an instruction 0x05 into bit [23:16] of an FMC10 register through the AHB, then generating an SPI read instruction through the FMC register, marking the SPI read instruction as a second SPI read instruction and sending the SPI read instruction to a flash, after the flash receives the second SPI read instruction, reading a value of a Write Process flag bit (WIP) according to CMD In the instruction, reading DATA returned by the flash from a DATA line of the AHB by a CPU, checking a bit0 value of the returned DATA, and if the value is 0, indicating that no task is currently executed, namely, the erasing operation is finished.

Then setting bit [1:0] of an FMC10 register to be 01 through an AHB, enabling an FMC instruction to be in a read mode, writing an instruction 0x2b into bit [23:16] of an FMC10 register through the AHB, generating an SPI read instruction through the FMC register, recording the SPI read instruction as a third SPI read instruction and sending the SPI read instruction to a flash, after the flash receives the third SPI read instruction, reading the value of an erasing success flag bit E _ Fail according to CMD in the instruction, reading DATA returned by the flash from a DATA line of the AHB by a CPU, checking the bit6 value of the returned DATA, if the value is 1, indicating that erasing is failed, and if the value is 0, indicating that erasing is successful.

On the basis of the foregoing embodiments, further, after the erasing is completed and before a write command is sent to a register on the FMC, the method further includes:

Specifically, after the erase is successful, the flash is programmed, and since the SuperIO supports at most 4bytes of data, if a normal write mode is selected, the programming of the data is abnormally slow. Since the general programming mode can only write 4bytes of data at a time and needs to check the flag bit after each writing, the amount of operations on the I/O port increases and the number of programming commands used increases, which eventually results in a very slow programming speed. Therefore, the programming mode needs to be modified into a user mode, and the user mode can perform the programming operation with the maximum data volume (256 bytes) each time programming is performed, so that the operation and the command of the I/O port are reduced, and the programming speed is improved. It should be noted that, unlike ordinary writing and reading, the address line of FMC in user mode is only used for chip select generation, and all SPI commands need to be written through the data line. Specifically, bit [1:0] of a 10 register of the FMC is set to 03 through the AHB, a programming mode of the flash can be modified to a user mode, after the user mode is modified, about 1m20 s-2 m is erased, about 3m30s is programmed, about 3m10s is verified, about 7-8 minutes is probably needed for upgrading the BMC, and compared with the prior art, the time for upgrading the BMC from a CPU end can be greatly shortened.

On the basis of the foregoing embodiments, further, the sending a write instruction to a register on the FMC includes:

The controlling the second register of the FMC so that the FMC can generate a second SPI writing instruction according to the second register, and the program to be upgraded is written into the flash through the second SPI writing instruction, and the method comprises the following steps:

Specifically, in user mode, it is necessary to piece up a whole SPI command, CMD ADDRESS DATA needs to be written into the DATA line of the AHB in sequence, each command is different, and the ADDRESS and DATA are different, and configuration is performed according to the sent command, for example, CMD is a command code to be written when writing, ADDRESS is an ADDRESS of a flash to be written, and DATA is DATA to be written into the flash.

Firstly setting bit [1:0] of an FMC10 register as 02 through an AHB, writing a programming instruction 0x02 into bit [23:16] of an FMC10 register, sending a program to be upgraded and an ADDRESS to be written into a flash to an FMC through a DATA line of the AHB in sequence, then generating a second SPI writing instruction containing CMD | ADDRESS | DATA | by the FMC, sending the second SPI writing instruction to the flash, and programming a program file by the flash.

And then, judging whether the programming is successful or not for the writing process flag bit and the programming success flag bit of the flash register. Specifically, bit [1:0] of an FMC10 register is set to be 01 through an AHB, an FMC command is In a read mode, commands 0x05 need to be written into bit [23:16] of an FMC10 register through the AHB, then the FMC register generates an SPI read command and sends the SPI read command to a flash, after the flash receives the SPI read command, the value of a Write Process flag bit (Write In Process, WIP) can be read according to CMD In the command, a CPU reads DATA returned by the flash from a DATA line of the AHB, the bit0 numerical value of the returned DATA is checked, and if the value is 0, the burning operation is finished.

Then setting bit [1:0] of an FMC10 register to be 01 through an AHB, enabling an FMC instruction to be in a read mode, writing an instruction 0x2b into bit [23:16] of an FMC10 register through the AHB, then generating an SPI read instruction through the FMC register, sending the SPI read instruction to a flash, after the flash receives the SPI read instruction, reading the value of a programming success flag bit P _ Fail according to CMD in the instruction, reading DATA returned by the flash from a DATA line of the AHB by a CPU, checking the bit5 numerical value of the returned DATA, if the value is 1, indicating that programming fails, and if the value is 0, indicating that programming succeeds.

On the basis of the foregoing embodiments, further, the sending a check instruction to a register on the FMC, and controlling the BMC to be upgraded to complete upgrade check by the register includes:

Specifically, after the programming is successful, the programming program needs to be verified, firstly, bit [1:0] of an FMC10 register is set to be 02 through an AHB, then a reading instruction 0x02 is written into bit [23:16] of an FMC10 through the AHB, the programming program is read, then the FMC generates an SPI instruction according to a register value and sends the SPI instruction to a flash, the flash returns the read programming program according to the SPI instruction, a CPU judges whether the programming program which is programmed is consistent with the issued program according to the reading value, if so, the programming is correct, and the verification is successful.

On the basis of the foregoing embodiments, further, after the BMC to be upgraded is controlled by the register to complete the upgrade process, the method further includes:

and restarting the BMC.

Specifically, after the LPC to AHB channel is opened, the watchdog program of the BMC needs to be closed by the watchdog controller of the BMC. Specifically, setting bit0 of the WDT2C register of the watchdog controller under the AHB to 0 closes the watchdog. After the programming check is successful, the watchdog counter is reset, the WDT24 register is written with the default value of the counter through the AHB, for example, 0x014FB180 is written, then bit0 of the WDT2C register is set to 1 to start the watchdog, the WDT28 register is written with 0x4755 to restart the counter, and then the BMC is automatically restarted by waiting for the timeout of the watchdog.

On the basis of the foregoing embodiments, further, after the restarting of the BMC, the method further includes:

Specifically, after the BMC is restarted, setting bit [0] of the 0x70 register of the SCU to 0 starts the CPU enable on the BMC.

On the basis of the foregoing embodiments, further, after the restarting the watchdog program of the BMC, the method further includes:

the LPC to AHB channel is closed.

Specifically, the CPU enable on the BMC to be upgraded is started, and the channel from the LPC to the AHB is closed through the SuperIO, so that the upgrading process of the BMC is completed.

According to the method for upgrading the BMC, provided by the embodiment of the invention, the channel from LPC to AHB is opened, the SCU register on the BMC to be upgraded is controlled by the AHB to close the CPU enabling on the BMC, the FMC register is controlled by the AHB to operate flash to complete the processes of erasing, programming and checking, the checking is carried out after the programming is completed once, and the programming is carried out by adopting a user mode, so that the programming checking time is saved, and the efficiency of upgrading the BMC is improved.

Fig. 2 is a schematic flow chart of a method for upgrading a BMC according to another embodiment of the present invention, as shown in fig. 2, the method includes:

step S201, upgrading BMC, and starting a channel from LPC to AHB through SuperIO; setting bit0 of WDT2C register of watchdog controller under AHB to 0 closes BMC watchdog.

Step S202, setting bit [0] of a 0x70 register of the SCU to 1 through the AHB to realize control to close the CPU enable of the BMC end and prevent instruction conflict;

step S203, setting a 0xA4 register of the FMC to be 0x2aa through the AHB to enable write address filtering control unlocking write enabling protection of the FMC;

step S204, setting bit [18:16] of a 0x00 register of the FMC to 0x7 through the AHB, and starting write enabling of the FMC to the mounted flash;

step S205, setting a register of 0xA4 of FMC to 0x000 through AHB to close address filtering write enable;

step S206, writing bit10 and bit9 of the FMC08 register into 0 by AHB to clear the zone bit of the address protection and illegal command;

step S207, setting the value of the FMC0C register to 0 through the AHB to realize that the SPI of the FMC is configured to be a 4bytes mode, and writing 0x1E620004 into 0x00000007 to realize that the SPI of the Flash is configured to be the 4bytes mode;

step S208, operating the FMC register through the AHB to start flash write enable, comprising:

a1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; a2, setting bit [1:0] of FMC10 register as 02, making SPI command be write mode; a3, writing an instruction into bit [23:16] of FMC10, A4 and FMC generating an SPI writing instruction and sending the SPI writing instruction to flash; a5, write 00 to FMC0C register, turn on SPI DATA and ADDRESS lines;

step S209, verifying flash write enable, comprising:

b1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; b2, setting bit [1:0] of an FMC10 register as 01 through AHB, and enabling the SPI instruction to be a read instruction; b3, writing a read instruction 0x05 into bits [23:16] of FMC10 through AHB, and reading a flash write enable check bit WEL; b4, generating an SPI writing instruction by the FMC and sending the SPI writing instruction to the flash; b5, write 00 to FMC0C register, turn on SPI DATA line and ADDRESS line;

step S210, obtaining a value bit1 returned by the flash from a data line of the AHB, judging whether the WEL is 1, if the WEL is 1, indicating that the write enable is correctly started, directly entering step S211, if the WEL is 0, indicating that the flash write enable is not correctly started, and jumping to step S208;

step S211, erasing the flash through FMC, comprising:

c1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; c2, setting bit [1:0] of an FMC10 register as 02 through AHB; c3, writing an erasing instruction 0xd8 to bits [23:16] of FMC10 through AHB; c4, the FMC generates an SPI writing instruction according to the register value and sends the SPI writing instruction to the flash; c5, write 00 to FMC0C register, turn on SPI DATA and ADDRESS lines; c6, erasing by the flash according to the SPI instruction;

step S212, waiting for the erase to end, includes:

d1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; d2, setting bit [1:0] of an FMC10 register as 01 through AHB; d3, AHB writes read command 0x05 to bit [23:16] of FMC10 to read WIP value; d4, the FMC generates an SPI instruction according to the register value and sends the SPI instruction to the flash; d5, write 00 to FMC0C register, turn on SPI DATA and ADDRESS lines;

step S213, acquiring a bit0 value of a numerical value returned by the flash, judging whether the WIP is 0, if so, indicating that no task is currently executed, namely, the erasure is finished, and if so, continuing to step S212;

step S214, checking the erasure success flag bit, which specifically includes:

e1, writing FF to the 0C register of FMC, closing the DATA line and ADDRESS line of SPI; e2, setting bit [1:0] of the FMC10 register as 01 through AHB; e3, read command 0x2b write to bits [23:16] of FMC10 through AHB read E _ Fail value; e4, the FMC generates an SPI instruction according to the register value and sends the SPI instruction to the flash; e5, write 00 to FMC0C register, turn on SPI DATA and ADDRESS lines;

s215, acquiring a bit6 value of the value returned by the flash, judging whether the E _ Fail is 1, if so, indicating that the erasure fails, and jumping to S211; if the value is 0, continuing;

step S216, determining that the erasing is successful;

step S217, judging whether erasing needs to be continued, if so, jumping to step S208, otherwise, continuing;

step S218, sending a programming command, including:

f1, setting bit [1:0] of a 10 register of the FMC to be 0x3 through an AHB, and modifying a flash programming mode into a user mode; f2, setting bit [1:0] of an FMC10 register as 02 through AHB, F3, and writing a programming instruction 0x02 into bit [23:16] of an FMC10 register; f4, sending the program to be upgraded and the address to be written into the flash to the FMC through the data line of the AHB in sequence; f5, FMC generates a second SPI write command containing | CMD | ADDRESS | DATA |; f6 and FMC send the second SPI writing command to flash; f7, programming a program file by the flash;

step S219, waiting for the programming to be completed, including:

g1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; g2, setting bit [1:0] of FMC10 register as 01 through AHB, and enabling the SPI instruction to be in a read mode; g3, write command 0x05 to bits [23:16] of FMC10 register through AHB; g4 and FMC register generate an SPI read instruction and send the SPI read instruction to flash; g5, write 00 to FMC0C register, turn on SPI DATA and ADDRESS lines; g6, after the flash receives the SPI reading command, reading a WIP value according to the CMD in the command;

step S220, reading a WIP value through an AHB data line, judging whether programming is finished or not, and if the WIP is 1, continuing to step S219;

step S221, checking the programming success flag bit, including:

h1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; h2, setting bit [1:0] of an FMC10 register as 01 through AHB, and enabling an FMC instruction to be in a read mode; h3, writing an instruction 0x2b into bit [23:16] of an FMC10 register through AHB, generating an SPI reading instruction by an H4 register and an FMC register, sending the SPI reading instruction to flash, H5, writing 00 into a 0C register of the FMC, and starting a DATA line and an ADDRESS line of the SPI; h6, after the flash receives the SPI read command, the value of the write success flag bit P _ Fail can be read according to the CMD in the command.

Step S222, reading DATA returned by the flash from a DATA line of the AHB by the CPU, checking a bit5 numerical value of the returned DATA, if the numerical value is 1, indicating that programming is failed, jumping to step S208, and if the numerical value is 0, indicating that programming is successful;

step S223, confirming that the programming is successful;

step S224, judging whether programming needs to be continued, if so, jumping to step S208, otherwise, continuing;

step S225, verifying the flash, comprising:

i1, writing FF to 0C register of FMC, closing DATA line and ADDRESS line of SPI; i2, setting bit [1:0] of an FMC10 register as 02 through AHB; i3, writing a read command 0x02 to bit [23:16] of FMC10 through AHB to read and write the program; i4, FMC generates SPI instruction according to register value, send to flash; i5, write 00 to FMC0C register, turn on SPI DATA and ADDRESS lines; i6, the flash returns the read programming program according to the SPI instruction; i7, the CPU follows the read value to judge whether the programmed program is consistent with the issued program, if so, the programming is correct, and the verification is successful;

step S226, after the programming verification is successful, resetting a counter of the watchdog, writing a default value of the counter into a WDT24 register through an AHB, such as writing 0x014FB180, then setting bit0 of a WDT2C register to be 1, starting the watchdog, writing 0x4755 into a WDT28 register, restarting the counter again, and then automatically restarting the BMC after waiting for the timeout of the watchdog;

step S227, setting bit [0] of a 0x70 register of the SCU to 0, and starting the CPU enabling on the BMC;

and step S228, closing the channel from LPC to AHB through SuperIO, and finishing the upgrading process of BMC.

Based on the same inventive concept, an embodiment of the present invention further provides a device for upgrading a BMC, as shown in fig. 3, including: a start module 31 and a sending module 32, wherein:

the starting module 31 is configured to start a channel from LPC to AHB, so as to control a register on the BMC to be upgraded through the AHB, where the register on the BMC to be upgraded is a slave of the AHB; the sending module 32 is configured to send an upgrade instruction to a register on the BMC to be upgraded, and control the BMC to be upgraded to complete an upgrade process through the register.

accordingly, the sending module 32 includes:

correspondingly, the device further comprises:

The above apparatus, optionally, further comprises:

correspondingly, the restart module is specifically configured to:

restarting a watchdog program of the BMC so as to restart the BMC.

The above apparatus, optionally, further comprises:

The apparatus provided in the embodiment of the present invention is configured to implement the method, and its functions specifically refer to the method embodiment, which is not described herein again.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 4, the electronic device includes: a processor (processor)41, a memory (memory)42, and a bus 43;

wherein, the processor 41 and the memory 42 complete the communication with each other through the bus 43;

processor 41 is configured to call program instructions in memory 42 to perform the methods provided by the above-described method embodiments, including, for example: opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB; and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register.

An embodiment of the present invention discloses a computer program product, which includes a computer program stored on a non-transitory computer readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer can execute the methods provided by the above method embodiments, for example, the method includes: opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB; and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register.

Embodiments of the present invention provide a non-transitory computer-readable storage medium, which stores computer instructions, where the computer instructions cause the computer to perform the methods provided by the above method embodiments, for example, the methods include: opening a channel from LPC to AHB so as to control a register on BMC to be upgraded through the AHB, wherein the register on the BMC to be upgraded is a slave of the AHB; and sending an upgrading instruction to a register on the BMC to be upgraded, and controlling the BMC to be upgraded to complete the upgrading process through the register.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above-described embodiments of the apparatuses and the like are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for upgrading a BMC, comprising:

2. The method of claim 1, wherein the registers on the BMC to be upgraded comprise: a register of FMC on the BMC to be upgraded;

3. The method of claim 2, wherein the registers on the BMC to be upgraded further comprise: the register of the SCU on the BMC to be upgraded;

4. The method of claim 3, wherein prior to sending an erase instruction to a register on the FMC, further comprising:

controlling a first register of the FMC to turn on FMC write enable.

5. The method of claim 4, wherein after the initiating FMC write enable, further comprising:

6. The method of claim 5, wherein after the starting of the flash write enable, further comprising:

7. The method as claimed in claim 6, wherein the sending an erase instruction to a register on the FMC, and controlling the BMC to be upgraded to erase an original program in the flash through the register, includes:

8. The method of claim 7, wherein after the erasing is completed and before sending a write command to a register on the FMC, further comprising:

9. The method of claim 8, wherein sending a write instruction to a register on the FMC comprises:

10. The method as claimed in claim 9, wherein the controlling the second register of the FMC so that the FMC generates a second SPI write command according to the second register, and the writing the program to be upgraded into the flash by the second SPI write command comprises:

11. The method as claimed in claim 10, wherein the sending a check instruction to a register on the FMC, and controlling the BMC to be upgraded to complete upgrade check through the register includes:

12. The method as claimed in any one of claims 3 to 11, wherein after controlling the BMC to be upgraded to complete the upgrade process through the register, the method further includes:

and restarting the BMC.

13. The method of claim 12, wherein after the opening the LPC to AHB channel, further comprising:

closing a watchdog program of the BMC;

accordingly, the rebooting the BMC includes:

restarting a watchdog program of the BMC so as to restart the BMC.

14. The method of claim 13, wherein after the restarting the BMC, further comprising:

15. The method of claim 14, wherein after restarting the watchdog program of the BMC, further comprising:

the LPC to AHB channel is closed.

16. An apparatus for upgrading a BMC, comprising:

17. The apparatus of claim 16, wherein the registers on the BMC to be upgraded comprise: a register of FMC on the BMC to be upgraded;

accordingly, the sending module comprises:

18. The apparatus of claim 17, wherein the registers on the BMC to be upgraded further comprise: the register of the SCU on the BMC to be upgraded;

correspondingly, the device further comprises:

19. The apparatus of claim 18, further comprising:

20. The apparatus of claim 19, further comprising:

21. The apparatus of claim 20, wherein the third control module is further configured to:

22. The apparatus of claim 21, wherein the erase unit is specifically configured to:

23. The apparatus of claim 22, wherein the third control module is further configured to:

24. The apparatus of claim 23, wherein the programming unit specifically comprises:

25. The apparatus according to claim 24, wherein the instruction generation subunit is specifically configured to:

26. The apparatus according to claim 25, wherein the verification unit is specifically configured to:

27. An electronic device, comprising:

the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1 to 15.

28. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1 to 15.