CN112600520B - Parallel digital frequency conversion method, system and storage medium - Google Patents
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Abstract
The invention provides a parallel digital frequency conversion method, a system and a storage medium, wherein the method comprises the following steps: inputting the received signal to a serial-parallel converter for serial-parallel conversion, and refreshing down-conversion parameters when refreshing the flag bit; inputting the converted signal and the refreshed down-conversion parameters to a corresponding down-converter to obtain a down-conversion signal; and inputting the down-conversion signal to a parallel-to-serial converter for parallel-to-serial conversion to complete digital frequency conversion. The invention can realize higher signal compensation precision of digital down-conversion by using smaller storage resources and fewer multipliers.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a parallel digital frequency conversion method, system, and storage medium.
Background
In broadband wireless systems, when the bandwidth is large, the bandwidth of signals can often reach hundreds of megabytes, and the corresponding requirement on the sampling rate is also met. The requirement for the digital front end is that the input data sampling rate can reach hundreds of megabits or even more than 1G, which places a high demand on the processing speed of the hardware.
The existing processing architecture has two types of serial and parallel, and the parallel can reduce the requirement on the hardware processing speed.
The existing frequency conversion invention comprises a table lookup method, a CORDIC implementation method, a secondary table lookup method and the like.
In order to realize high-precision frequency offset compensation, the table lookup method needs to store a relatively large table, and occupies resources.
CORDIC implementations increase latency and require a large number of iterations in order to achieve higher accuracy, which also increases power consumption.
The invention is a better compromise in the secondary table lookup method, which can better balance the storage space and the power consumption, but the complex multiplication is needed to be performed once more after the secondary table lookup, certain resources are consumed, and the performance is also influenced by the size of the secondary table lookup.
Disclosure of Invention
The invention aims to provide a parallel digital frequency conversion method, a system and a storage medium, which can realize higher signal compensation precision of digital down-conversion by using smaller storage resources and fewer multipliers.
The technical invention provided by the invention is as follows:
The invention provides a parallel digital frequency conversion method, which comprises the following steps:
inputting the received signal to a serial-parallel converter for serial-parallel conversion, and refreshing down-conversion parameters when refreshing the flag bit;
Inputting the converted signal and the refreshed down-conversion parameters to a corresponding down-converter to obtain a down-conversion signal;
And inputting the down-conversion signal to a parallel-to-serial converter for parallel-to-serial conversion to complete digital frequency conversion.
Further, the step of inputting the received signal to the serial-to-parallel converter for serial-to-parallel conversion and refreshing the down-conversion parameter when the refresh flag bit is updated includes the steps of:
Before updating the refreshing flag bit, pre-configuring a variable frequency initial value;
acquiring hierarchical parameters and initial phase parameters according to the variable frequency initial value and storing the hierarchical parameters and the initial phase parameters into a register;
The frequency conversion initial value comprises a down-conversion frequency, a sampling rate and an initial phase value of each channel of the down-converter; the down-conversion parameters comprise the hierarchy parameters and initial phase parameters corresponding to all channels of the down-converter.
Further, the step of obtaining and storing the hierarchical parameters and the initial phase parameters according to the down-conversion parameters includes the steps of:
substituting the down-conversion frequency and the sampling rate into the following hierarchical function to calculate and obtain the hierarchical parameters;
fac＝k*f0/fs*2^32；
Substituting the initial phase value, the down-conversion frequency and the sampling rate into the following initial phase operation function to calculate and obtain initial phase parameters corresponding to each channel;
phi(m)＝phi_0+(m-1)*f0/fs*2^32；
Wherein fac is the hierarchical parameter, f0 is the down-conversion frequency, fs is the sampling rate, phi (m) is the initial phase parameter corresponding to the current channel, phi_0 is the initial phase value, m is the channel sequence number value of the current channel, k is the parallel path value,/represents the divisor,/represents the multiplier, <' > represents the 32 nd power of 2;
and storing the hierarchical parameters and the initial phase parameters into a register.
Further, the down converter includes a phase accumulator, CORDCI calculator, and an approximation calculator; the step of inputting the converted signal and the refreshed down-conversion parameters to the corresponding down-converter to obtain the down-conversion signal comprises the following steps:
Inputting the hierarchical parameters and the initial phase parameters into phase accumulators at the corresponding channels to perform accumulation calculation to obtain a phase accumulated value and a first target value;
Inputting the converted signal and the phase accumulated value to a CORDCI calculator for calculation to obtain a calibrated converted signal and a second target value;
and inputting the calibrated and converted signal, the first target value and the second target value to the approximation calculator for approximation calculation to obtain a down-conversion signal.
Further, the step of inputting the converted signal and the phase accumulated value to a CORDCI calculator to calculate to obtain second output data includes the steps of:
substituting the converted signal into a real part evaluation function to obtain a first initial iteration value, and substituting the converted signal into an imaginary part evaluation function to obtain a second initial iteration value;
And taking the phase accumulated value as an iteration initial value, and carrying out iterative calculation according to the iteration initial value, the first initial iteration value and the second initial iteration value to obtain a calibrated and converted signal and a second target value.
Further, the step of performing iterative computation according to the iteration initial value, the first initial iteration value and the second initial iteration value to obtain a calibrated and converted signal and a second target value includes the steps of:
If the iteration initial value or the iteration parameter value is equal to zero, determining that a first split value is equal to the first initial iteration value and a second split value is equal to the second initial iteration value, and stopping iterative calculation;
if the iteration initial value or the iteration parameter value is not equal to zero, substituting the iteration initial value into the following iteration function to calculate to obtain the iteration parameter value;
z(i+1)＝z(i)-d*atantext(i)；
substituting the iteration parameter value into the following symbol function to calculate a symbol value;
d＝sign(z(i))；
substituting the first initial iteration value, the second initial iteration value and the symbol value into the following first split function to calculate the first split value;
x1(i+1)＝x1(i)-d*(x2(i)>>i-1)；
Substituting the first initial iteration value, the second initial iteration value and the symbol value into the following second splitting function to calculate the second splitting value;
x2(i+1)＝x2(i)+d*(x1(i)>>i-1)；
Calculating according to the first differential value, the second differential value and the iteration parameter value when iteration is stopped to obtain a calibrated and converted signal and a second target value;
Wherein z (i) is an iteration parameter value calculated in the previous iteration, i is an iteration sequence number value representing the ith iteration, i is a natural number and 1.ltoreq.i.ltoreq.9, z (i+1) is an iteration parameter value calculated in the current iteration, d represents a sign value, x1 (i+1) is a first component value calculated in the current iteration, x1 (i) is a first component value calculated in the previous iteration, x2 (i+1) is a second component value calculated in the current iteration, x2 (i) is a second component value calculated in the previous iteration, x1 (1) is a first initial iteration value, x2 (1) is a second initial iteration value, and z (1) is an iteration initial value.
Further, the step of calculating the calibration converted signal and the second target value according to the first derivative value, the second derivative value and the iteration parameter value when the iteration is stopped includes the steps of:
substituting the first split value and the second split value when iteration stops into the following calibration function to obtain the calibrated and converted signal;
x″＝x1′(i+1)+1i*x2′(i+1)；
Substituting the iteration parameter value when iteration stops into the following valued function to obtain the second target value;
index2＝z′(i+1)；
where x "is the calibration converted signal, index2 is the second target value, x1' (i+1) is the first split value at the time of iteration stop, x2' (i+1) is the second split value at the time of iteration stop, and z ' (i+1) is the iteration parameter value at the time of iteration stop.
Further, the step of inputting the calibrated and converted signal, the first target value and the second target value to the approximation calculator to perform approximation calculation to obtain a down-conversion signal includes the steps of:
Inputting the calibrated and converted signal and the second target value into the following approximate calculation function to calculate to obtain a real part update parameter and an imaginary part update parameter;
x1_re＝real(x″)-imag(x″)*index2；
x1_im＝imag(x″)+real(x″)*index2；
Substituting the real part update parameter and the imaginary part update parameter into the following update function to calculate and obtain target calibration data;
x″′＝x1_re+1i*x1_im；
calculating and acquiring the down-conversion signal according to the first target value and target calibration data;
Wherein x1_re is a real part update parameter, x1_im is an imaginary part update parameter, x "is a calibrated converted signal, index2 is a second target value, real () is a real part evaluation function, and imag () is an imaginary part evaluation function.
The invention also provides a parallel digital frequency conversion device, which comprises:
The serial-to-parallel conversion module is used for inputting the received signal to the serial-to-parallel converter for serial-to-parallel conversion and refreshing the down-conversion parameters when refreshing the flag bit;
the data calibration module is used for inputting the converted signals and the refreshed down-conversion parameters to the corresponding down-converters to obtain down-conversion signals;
and the parallel-serial conversion module is used for inputting the down-conversion signal to a parallel-serial converter for parallel-serial conversion to complete digital conversion.
The present invention also provides a storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement the operations performed by the parallel digital frequency conversion method.
The parallel digital frequency conversion method, the system and the storage medium provided by the invention can realize higher signal compensation precision of digital down-conversion by using smaller storage resources and fewer multipliers.
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The above features, technical features, advantages and implementation of a parallel digital frequency conversion method, system and storage medium will be further described in the following in a clear and understandable manner by describing preferred embodiments with reference to the accompanying drawings.
FIG. 1 is a flow chart of one embodiment of a parallel digital frequency conversion method of the present invention;
FIG. 2 is a schematic diagram of the down converter of the present invention;
FIG. 3 is an iterative schematic diagram of a parallel digital frequency conversion method of the present invention;
Fig. 4 is a schematic diagram of a wireless communication receiver of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In order to more clearly illustrate the embodiments of the present invention or the technical invention in the prior art, a specific embodiment of the present invention will be described below with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
In one embodiment of the present invention, as shown in fig. 1, a parallel digital frequency conversion method includes:
s100, inputting a receiving signal to a serial-parallel converter for serial-parallel conversion, and refreshing down-conversion parameters when refreshing flag bits;
Specifically, the Refresh flag bit refers to a Refresh signal, and when the Refresh flag bit is updated, it represents that a new receiving signal is received. Therefore, once the refresh zone bit is updated, the received signal is subjected to serial-to-parallel conversion, that is, the received signal is converted from the serial format on a single line to the parallel format on multiple lines to complete serial-to-parallel conversion, so as to obtain a converted signal.
S200, inputting the converted signals and the refreshed down-conversion parameters to corresponding down-converters to obtain down-conversion signals;
specifically, the frequency conversion can be classified into down-conversion (frequency reduction) and up-conversion (frequency increase) according to the conditions before and after the frequency conversion. The down-conversion parameters are written in the register in advance, after serial-parallel conversion is completed, the converted signal and the down-conversion parameters are input into the down-converter, and the down-converter carries out frequency mixing processing on the converted signal so as to change the frequency band of the converted signal to obtain a down-conversion signal.
S300, the down-conversion signal is input to a parallel-to-serial converter for parallel-to-serial conversion to complete digital conversion.
Specifically, after the down-conversion signal is obtained in the above manner, the down-conversion signal is subjected to parallel-to-serial conversion, that is, the received signal is converted from the parallel format on multiple lines to the serial format on single lines to complete the parallel-to-serial conversion, thereby completing the frequency conversion processing of the received signal.
The serial-to-parallel converter and the parallel-to-serial converter are matched with each other, and the serial-to-parallel converter converts a continuous received signal into six corresponding sets of signal elements appearing in parallel, which are converted signals, assuming that the number of parallel-to-serial paths is 6, for example. Then, the parallel-to-serial converter converts the down-converted signal corresponding to the converted signal into a continuous signal to complete the frequency conversion processing of the received signal.
In this embodiment, the received signals are processed in parallel, so that the requirement on the hardware processing speed is reduced, and the efficiency of the frequency conversion processing of the received signals is improved.
Based on the foregoing embodiment, the inputting the received signal to the serial-to-parallel converter for serial-to-parallel conversion, and before refreshing the down-conversion parameter when refreshing the flag bit update, includes the steps of:
Before updating the refreshing flag bit, pre-configuring a variable frequency initial value;
acquiring hierarchical parameters and initial phase parameters according to the variable frequency initial value and storing the hierarchical parameters and the initial phase parameters into a register;
The frequency conversion initial value comprises a down-conversion frequency, a sampling rate and an initial phase value of each channel of the down-converter; the down-conversion parameters comprise the hierarchy parameters and initial phase parameters corresponding to all channels of the down-converter.
Based on the foregoing embodiment, the step of obtaining and storing the hierarchical parameters and the initial phase parameters according to the down-conversion parameters includes the steps of:
substituting the down-conversion frequency and the sampling rate into the following hierarchical function (1) to calculate the hierarchical parameters;
fac＝k*f0/fs*2^32； (1)
Substituting the initial phase value, the down-conversion frequency and the sampling rate into the following initial phase operation function to calculate and obtain initial phase parameters corresponding to each channel;
phi(m)＝phi_0+(m-1)*f0/fs*2^32； (2)
Wherein fac is the hierarchical parameter, f0 is the down-conversion frequency, fs is the sampling rate, phi (m) is the initial phase parameter corresponding to the current channel, phi_0 is the initial phase value, m is the channel sequence number value of the current channel, k is the parallel path value,/represents the divisor,/represents the multiplier, <' > represents the 32 nd power of 2;
and storing the hierarchical parameters and the initial phase parameters into a register.
Specifically, k may take the values of 2,4,6,8, 16, k being a multiple of 2 and greater than zero. In summary, the value of k is equal to the value of m. When a mark to be generated by a Refresh signal is acquired, the down-conversion frequency f0, the sampling frequency fs and initial phase values of all channels of the down-converter are configured in advance, and substituted into a hierarchical function in an 8-channel parallel processing mode to convert the hierarchical parameter fac:
fac＝8*f0/fs*2^32；
And then, substituting m=1, 2,3,4,5,6,7 and 8 into the initial phase operation function according to the initial phase value phi_0 and the initial phase phi (m) of each channel to calculate and obtain initial phase parameters corresponding to each channel.
phi(m)＝phi_0+(m-1)*f0/fs*2^32。
After the hierarchical parameters and the initial phase parameters are calculated by the calculation formula, the hierarchical parameters and the initial phase parameters are stored in a register.
Based on the foregoing embodiments, the down converter includes a phase accumulator, CORDCI calculator, and an approximation calculator; the step of inputting the converted signal and the refreshed down-conversion parameters to the corresponding down-converter to obtain the down-conversion signal comprises the following steps:
Inputting the hierarchical parameters and the initial phase parameters into phase accumulators at the corresponding channels to perform accumulation calculation to obtain a phase accumulated value and a first target value;
Inputting the converted signal and the phase accumulated value to a CORDCI calculator for calculation to obtain a calibrated converted signal and a second target value;
and inputting the calibrated and converted signal, the first target value and the second target value to the approximation calculator for approximation calculation to obtain a down-conversion signal.
Specifically, as shown in fig. 2, each of the downconverters has the same structure: comprises a phase accumulator, CORDCI calculator, and an approximation calculator. And inputting the hierarchical parameters and the initial phase parameters into phase accumulators at the corresponding channels to perform accumulation calculation to obtain a phase accumulated value and a first target value, wherein each time the phase accumulators accumulate, one phase accumulated value and one first target value are output.
Then, the converted data and the phase accumulated value are input to the CORDIC calculator, and z (1) =delta, x1 (1) =real (x), x2 (1) =imag (x), antantext is a stored atan table, wherein atantext =round (atan (2++0:15))/(pi) ×2++31), and the number of iterations is 10. And then performing CORDIC calculation to output the calibrated converted signal and the second target value. And inputting the calibrated and converted signal, the first target value and the second target value into the approximation calculator for approximation calculation to obtain a down-conversion signal.
Based on the foregoing embodiment, the step of inputting the converted signal and the accumulated phase value to the CORDCI calculator to calculate to obtain the second output data includes the following steps:
substituting the converted signal into a real part evaluation function to obtain a first initial iteration value, and substituting the converted signal into an imaginary part evaluation function to obtain a second initial iteration value;
And taking the phase accumulated value as an iteration initial value, and carrying out iterative calculation according to the iteration initial value, the first initial iteration value and the second initial iteration value to obtain a calibrated and converted signal and a second target value.
Based on the foregoing embodiment, the performing iterative computation according to the iteration initial value, the first initial iteration value, and the second initial iteration value to obtain the calibrated and converted signal and the second target value includes the steps of:
If the iteration initial value or the iteration parameter value is equal to zero, determining that a first split value is equal to the first initial iteration value and a second split value is equal to the second initial iteration value, and stopping iterative calculation;
If the iteration initial value or the iteration parameter value is not equal to zero, substituting the iteration initial value into the following iteration function (3) to calculate to obtain the iteration parameter value;
z(i+1)＝z(i)-d*atantext(i)； (3)
substituting the iteration parameter value into the following symbol function to calculate a symbol value;
d＝sign(z(i))；
Substituting the first initial iteration value, the second initial iteration value and the sign value into the following first splitting function (4) to calculate and obtain the first splitting value;
x1(i+1)＝x1(i)-d*(x2(i)>>i-1)； (4)
Substituting the first initial iteration value, the second initial iteration value and the sign value into the following second splitting function (5) to calculate to obtain the second splitting value;
x2(i+1)＝x2(i)+d*(x1(i)>>i-1)； (5)
Calculating according to the first differential value, the second differential value and the iteration parameter value when iteration is stopped to obtain a calibrated and converted signal and a second target value;
Wherein z (i) is an iteration parameter value calculated in the previous iteration, i is an iteration sequence number value representing the ith iteration, i is a natural number and 1.ltoreq.i.ltoreq.9, z (i+1) is an iteration parameter value calculated in the current iteration, d represents a sign value, x1 (i+1) is a first component value calculated in the current iteration, x1 (i) is a first component value calculated in the previous iteration, x2 (i+1) is a second component value calculated in the current iteration, x2 (i) is a second component value calculated in the previous iteration, x1 (1) is a first initial iteration value, x2 (1) is a second initial iteration value, and z (1) is an iteration initial value.
Specifically, as shown in fig. 3, ifz (i) = 0, that is, if the iteration initial value or the iteration parameter value is equal to zero, x1 (i+1) = x1 (i), x2 (i+1) = x2 (i) is output, the iteration is jumped out, that is, it is determined that the first split value is equal to the first initial iteration value and the second split value is equal to the second initial iteration value, and the iterative calculation is stopped.
And if the iteration initial value is not equal to zero, substituting the iteration initial value into an iteration function to calculate so as to obtain an iteration parameter value. And substituting the first initial iteration value, the second initial iteration value and the symbol value into the following first splitting function to calculate the first splitting value, and substituting the first initial iteration value, the second initial iteration value and the symbol value into the following second splitting function to calculate the second splitting value. And after the iteration is completed for i times, calculating according to the first differential value, the second differential value and the iteration parameter value when the iteration is stopped to obtain a calibrated and converted signal and a second target value.
Based on the foregoing embodiment, the calculating according to the first split value, the second split value and the iteration parameter value when the iteration is stopped to obtain the calibrated and converted signal and the second target value includes the steps of:
Substituting the first split value and the second split value when iteration stops into the following calibration function (6) to obtain the calibrated and converted signal;
x″＝x1′(i+1)+1i*x2′(i+1)； (6)
Substituting the iteration parameter value when iteration stops into the following valued function (7) to obtain the second target value;
index2＝z′(i+1)； (7)
where x "is the calibration converted signal, index2 is the second target value, x1' (i+1) is the first split value at the time of iteration stop, x2' (i+1) is the second split value at the time of iteration stop, and z ' (i+1) is the iteration parameter value at the time of iteration stop.
Based on the foregoing embodiment, the step of inputting the calibration converted signal, the first target value, and the second target value to the approximation calculator to perform approximation calculation to obtain a down-converted signal includes the steps of:
inputting the calibrated and converted signal and the second target value into the following approximate calculation function (8) for calculation to obtain a real part update parameter and an imaginary part update parameter;
x1_re＝real(x″)-imag(x″)*index2；
x1_im＝imag(x″)+real(x″)*index2； (8)
Substituting the real part update parameter and the imaginary part update parameter into the following update function (9) to calculate to obtain target calibration data;
x″′＝x1_re+1i*x1_im； (9)
calculating and acquiring the down-conversion signal according to the first target value and target calibration data;
Wherein x1_re is a real part update parameter, x1_im is an imaginary part update parameter, x "is a calibrated converted signal, index2 is a second target value, real () is a real part evaluation function, and imag () is an imaginary part evaluation function.
The invention mainly realizes the digital down-conversion of the wide bandwidth wireless communication system by a method combining 8-path parallel processing, quadrant mapping method, CORDIC and small-angle approximate processing.
In wireless communication systems, it is often necessary to down-convert the received signal. Let the sampling frequency of the signal be fs, the required down-conversion frequency be f0, the received signal be x (k) (k=0, … …, n), the down-converted signal be y (k), x, y be complex, then
y(k)＝x(k)*(cos(f0/fs*2*pi*(k-1))+1i*sin(f0/fs*2*pi*(k-1)))；
Where k=1, … …, n.
The equivalent is considered as:
y(k)＝x(k)*(cos(delta)+1i*sin(delta))；
wherein k=1, … …, n; delta is between 0 and 2 pi, thereby achieving frequency offset compensation.
When 8 parallel lines are adopted, the mth line (m=0, 1,2 … …) at the k time:
y_m(k)＝x(8*k+m)*(cos(8*f0/fs*2*pi*(k-1)+m*f0/fs)+1i*sin(f8*0/fs*2*pi*(k-1))+m*f0/fs)
For each way in parallel, it can be seen that:
y (k) =x (k) × (cos (delta) +1i×sin (delta)), k=1, … …, ndelta is between 0 and 2×pi.
The rotation of the data by delta angle can be directly performed by CORDIC. Let the CORDIC pass through a limited iteration, the rotation angle be delta1 and the residual angle be delta2.
delta＝delta1+delta2；
Let the rotated data be x2=x (cos (delta 1) +1i sin (delta 1));
then the required y=x2 x (cos (delta 2) +1i sin (delta 2));
Since the delta2 angle is small, an approximation can be obtained: cos (delta 2) =1, sin (delta 2) =delta2;
real(y)＝real(x2)-delta2*imag(x2)；
imag(y)＝imag(x2)+delta2*real(x2)；
For any angle a,0< = a <2 pi, a = b + m pi/2 can be written, where 0= < b < pi/2, m is a number from 0 to 3. Then
cos(a)＝cos(b+m*pi/2)；
For m=0; cos (a) = cos (b), m = 1, cos (a) = -sin (b); similarly, cos (a) can always be expressed as the sine and cosine value of b, and the result of the sign of the sine and cosine value. Similarly, sin (a) can be expressed as such. The angle sine and cosine values in the range of 0-2 pi can be calculated, and the result in the range of 0-pi/2 can be calculated. Then the rotation of any angle of 0-2 pi can be carried out, the rotation within 0-pi/2 is carried out, and then the rotation is obtained through a conversion formula.
The digital down-conversion of the wide-bandwidth wireless communication system is realized by a method combining multipath parallel processing, quadrant mapping method, CORDIC and small-angle approximate processing, and the high compensation precision can be realized by using smaller storage resources and smaller multipliers. The 8-way parallelism reduces the requirement for hardware processing speed.
The invention comprises a register, a serial-to-parallel converter, a parallel-to-serial converter and a down converter with the same number as the number of parallel-to-serial-to-parallel paths. The register configures down-conversion parameters to the down-converter corresponding to each channel in advance, and when the Refresh flag (i.e. the Refresh flag bit) generates update, the Refresh flag bit is transferred to the down-converter to take effect to participate in calculation. The serial-to-parallel converter finishes the serial-to-parallel conversion of the received signal, and the parallel-to-serial converter finishes the parallel-to-serial conversion of the down-converted signal, the down-converter respectively realizes down-conversion for each parallel channel, and the down-conversion parameter change is effectively controlled by a Refresh mark.
The invention adopts the method of combining 8-path parallel processing, quadrant mapping method, CORDIC and small-angle approximate processing to realize digital down-conversion of the wide-bandwidth wireless communication system, and can use smaller storage resources and multipliers to realize higher compensation precision. The 8-way parallelism reduces the requirement for hardware processing speed. The data is directly rotated by the CORDIC to obtain the compensated initial value, and the initial value is not provided with a multiplier, only is added and shifted, so that the resource is saved. The number of CORDIC iterations is not required to be too large, the time delay is reduced, the number of CORDIC iterations can be reduced by half, and the original same performance is achieved. The calibration result is obtained by approximate calculation, and high calculation accuracy can be achieved. By mapping 0-2 pi to 0-pi/2, the trigonometric function transformation formula is applied without increasing the operand, thereby ensuring the convergence of the CORDIC. The CORDIC increases an early exit mechanism, avoids invalid iterations, and wastes power consumption.
For example, as shown in fig. 4, for a certain wireless communication receiver, it is assumed that its sampling rate=2.4g, and down-conversion frequency f0=300m. When the refresh zone bit is updated, the down-converter is configured with down-conversion frequency f0 and sampling rate fs in advance, and fac, initial phase phi_0 and initial phase phi (m) of each channel are calculated according to an 8-path parallel processing mode, wherein m=1, 2,3,4,5,6,7 and 8.
fac＝8*f0/fs*2^32；
phi(m)＝phi_0+(m-1)*f0/fs*2^32。
The invention adopts the method of combining 8-path parallel processing, quadrant mapping method, CORDIC and small-angle approximate processing to realize digital down-conversion of the wide-bandwidth wireless communication system, and can use smaller storage resources and multipliers to realize higher compensation precision. The 8-way parallelism reduces the requirement for hardware processing speed. The data is directly rotated by the CORDIC to obtain the compensated initial value, and the initial value is not provided with a multiplier, only is added and shifted, so that the resource is saved. The number of CORDIC iterations is not required to be too large, the time delay is reduced, the number of CORDIC iterations can be reduced by half, and the original same performance is achieved. By mapping 0-2 pi to 0-pi/2, the trigonometric function transformation formula is applied without increasing the operand, thereby ensuring the convergence of the CORDIC. The CORDIC increases an early exit mechanism, avoids invalid iterations, and wastes power consumption. The calibration result is obtained by approximate calculation, and high calculation accuracy can be achieved.
One embodiment of the present invention is a parallel digital frequency conversion device, comprising:
The serial-to-parallel conversion module is used for inputting the received signal to the serial-to-parallel converter for serial-to-parallel conversion and refreshing the down-conversion parameters when refreshing the flag bit;
the data calibration module is used for inputting the converted signals and the refreshed down-conversion parameters to the corresponding down-converters to obtain down-conversion signals;
and the parallel-serial conversion module is used for inputting the down-conversion signal to a parallel-serial converter for parallel-serial conversion to complete digital conversion.
Specifically, the embodiment is an embodiment of a device corresponding to the embodiment of the method, and specific effects refer to the embodiment of the method, which is not described herein in detail.
It will be apparent to those skilled in the art that the above-described program modules are only illustrated in the division of the above-described program modules for convenience and brevity, and that in practical applications, the above-described functional allocation may be performed by different program modules, i.e., the internal structure of the apparatus is divided into different program units or modules, to perform all or part of the above-described functions. The program modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one processing unit, where the integrated units may be implemented in a form of hardware or in a form of a software program unit. In addition, the specific names of the program modules are also only for distinguishing from each other, and are not used to limit the protection scope of the present application.
In one embodiment of the present invention, a storage medium has at least one instruction stored therein, where the instruction is loaded and executed by a processor to implement the operations performed by the corresponding embodiments of the parallel digital frequency conversion method described above. For example, the storage medium may be read-only memory (ROM), random-access memory (RAM), compact disk read-only (CD-ROM), magnetic tape, floppy disk, optical data storage device, etc.
They may be implemented in program code that is executable by a computing device such that they may be stored in a memory device for execution by the computing device, or they may be separately fabricated into individual integrated circuit modules, or a plurality of modules or steps in them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technology. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the object of the present embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units may be stored in a storage medium if implemented in the form of software functional units and sold or used as stand-alone products. With this understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by sending an instruction to related hardware by the computer program 121, where the computer program 121 may be stored in a storage medium, and the computer program 121 may implement the steps of each of the method embodiments described above when executed by a processor. Wherein the computer program 121 may be in the form of source code, object code, executable file, some intermediate form, or the like. The storage medium may include: any entity or device capable of carrying the computer program 121, a recording medium, a USB flash disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that, the content contained in the storage medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example: in some jurisdictions, computer-readable storage media do not include electrical carrier signals and telecommunication signals, in accordance with legislation and patent practice.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (9)
1. A parallel digital frequency conversion method, comprising the steps of:
Inputting a received signal to a serial-to-parallel converter for serial-to-parallel conversion, refreshing a down-conversion parameter when refreshing a flag bit, wherein the refreshing flag bit is updated when acquiring the received signal, and the down-conversion parameter comprises: the method comprises the steps that hierarchy parameters and initial phase parameters corresponding to all channels of a down converter are determined based on a pre-configured frequency conversion initial value;
the down converter comprises a phase accumulator, a CORDCI calculator and an approximation calculator, and inputs the converted signal and the refreshed down conversion parameters to the corresponding down converter to obtain a down conversion signal, and the down converter comprises: inputting the hierarchical parameters and the initial phase parameters corresponding to the channels into the phase accumulators at the corresponding channels to perform accumulation calculation to obtain a phase accumulated value and a first target value; inputting the converted signal and the phase accumulated value to the CORDCI calculator for calculation to obtain a calibrated converted signal and a second target value; inputting the calibrated and converted signal, the first target value and the second target value to the approximation calculator for approximation calculation to obtain a down-conversion signal;
And inputting the down-conversion signal to a parallel-to-serial converter for parallel-to-serial conversion to complete digital frequency conversion.
2. The parallel digital frequency conversion method according to claim 1, wherein the step of inputting the received signal to the serial-to-parallel converter for serial-to-parallel conversion and refreshing the down-conversion parameters at the time of refreshing the flag bit update comprises the steps of:
acquiring the hierarchy parameters and the initial phase parameters according to the variable frequency initial value and storing the hierarchy parameters and the initial phase parameters into a register;
the frequency conversion initial value comprises a down-conversion frequency, a sampling rate and initial phase values of all channels of the down-converter.
3. The parallel digital frequency conversion method according to claim 2, wherein the step of acquiring and storing hierarchical parameters and initial phase parameters according to the down-conversion parameters comprises the steps of:
substituting the down-conversion frequency and the sampling rate into the following hierarchical function to calculate and obtain the hierarchical parameters;
fac=k*f0/fs*2^32；
substituting the initial phase value, the down-conversion frequency and the sampling rate into the following initial phase operation function to calculate and obtain initial phase parameters corresponding to each channel;
phi(m)=phi_0+(m-1)*f0/fs*2^32；
Wherein fac is the hierarchical parameter, f0 is the down-conversion frequency, fs is the sampling rate, phi (m) is the initial phase parameter corresponding to the current channel, phi_0 is the initial phase value, m is the channel sequence number value of the current channel, k is the parallel path value,/represents the divisor,/represents the multiplier, and 2x 32 represents the 32 nd power of 2;
and storing the hierarchy parameters and the initial phase parameters into a register.
4. A parallel digital frequency conversion method according to claim 3, wherein the step of inputting the converted signal and the phase accumulated value to a CORDCI calculator to calculate the second output data includes the steps of:
substituting the converted signal into a real part evaluation function to obtain a first initial iteration value, and substituting the converted signal into an imaginary part evaluation function to obtain a second initial iteration value;
And taking the phase accumulated value as an iteration initial value, and carrying out iterative calculation according to the iteration initial value, the first initial iteration value and the second initial iteration value to obtain a calibrated and converted signal and a second target value.
5. The parallel digital frequency conversion method according to claim 4, wherein the iterative calculation to obtain the calibrated and converted signal and the second target value according to the iterative initial value, the first initial iterative value and the second initial iterative value comprises the steps of:
If the iteration initial value or the iteration parameter value is equal to zero, determining that a first split value is equal to the first initial iteration value and a second split value is equal to the second initial iteration value, and stopping iterative calculation;
if the iteration initial value or the iteration parameter value is not equal to zero, substituting the iteration initial value into the following iteration function to calculate to obtain the iteration parameter value;
z(i+1) = z(i)-d*atantext(i)；
substituting the iteration parameter value into the following symbol function to calculate a symbol value;
d = sign(z(i))；
substituting the first initial iteration value, the second initial iteration value and the symbol value into the following first split function to calculate the first split value;
x1(i+1) = x1(i)-d* (x2(i)>>i-1)；
Substituting the first initial iteration value, the second initial iteration value and the symbol value into the following second splitting function to calculate the second splitting value;
x2(i+1) = x2(i)+d* (x1(i)>>i-1)；
Calculating according to the first differential value, the second differential value and the iteration parameter value when iteration is stopped to obtain a calibrated and converted signal and a second target value;
Wherein z (i) is an iteration parameter value calculated in the previous iteration, i is an iteration sequence number value representing the ith iteration, i is a natural number and 1.ltoreq.i.ltoreq.9, z (i+1) is an iteration parameter value calculated in the current iteration, d represents a sign value, x1 (i+1) is a first component value calculated in the current iteration, x1 (i) is a first component value calculated in the previous iteration, x2 (i+1) is a second component value calculated in the current iteration, x2 (i) is a second component value calculated in the previous iteration, x1 (1) is a first initial iteration value, x2 (1) is a second initial iteration value, and z (1) is an iteration initial value.
6. The parallel digital frequency conversion method according to claim 5, wherein the calculating according to the first division value, the second division value and the iteration parameter value at the time of stopping the iteration to obtain the calibrated and converted signal and the second target value comprises the steps of:
substituting the first split value and the second split value when iteration stops into the following calibration function to obtain the calibrated and converted signal;
x´´ = x1´(i+1)+1i* x2´(i+1)；
Substituting the iteration parameter value when iteration stops into the following valued function to obtain the second target value;
index2=z´(i+1)；
wherein x 'is a calibration converted signal, index2 is a second target value, x 1' is a first split value at the time of iteration stop, x2 'is a second split value at the time of iteration stop, and z' is an iteration parameter value at the time of iteration stop.
7. The parallel digital frequency conversion method according to claim 1, wherein the step of inputting the calibrated converted signal, the first target value, and the second target value to the approximation calculator to perform approximation calculation to obtain a down-converted signal includes the steps of:
Inputting the calibrated and converted signal and the second target value into the following approximate calculation function to calculate to obtain a real part update parameter and an imaginary part update parameter;
x1_re =real(x´´)-imag(x´´)* index2；
x1_im =imag(x´´)+real(x´´)* index2；
Substituting the real part update parameter and the imaginary part update parameter into the following update function to calculate and obtain target calibration data;
x´´´ = x1_re+1i* x1_im；
calculating and acquiring the down-conversion signal according to the first target value and target calibration data;
Wherein x1_re is a real part update parameter, x1_im is an imaginary part update parameter, x' is a calibrated converted signal, index2 is a second target value, real () is a real part evaluation function, and imag () is an imaginary part evaluation function.
8. A parallel digital frequency conversion device, comprising:
the serial-parallel conversion module is used for inputting a received signal to the serial-parallel converter for serial-parallel conversion, refreshing a down-conversion parameter when refreshing a flag bit, wherein the refreshing flag bit is updated when acquiring the received signal, and the down-conversion parameter comprises: the method comprises the steps that hierarchy parameters and initial phase parameters corresponding to all channels of a down converter are determined based on a pre-configured frequency conversion initial value;
The down converter comprises a phase accumulator, a CORDCI calculator and an approximation calculator;
The data calibration module is configured to input the converted signal and the refreshed down-conversion parameter to a corresponding down-converter to obtain a down-conversion signal, and includes: inputting the hierarchical parameters and the initial phase parameters corresponding to the channels into the phase accumulators at the corresponding channels to perform accumulation calculation to obtain a phase accumulated value and a first target value; inputting the converted signal and the phase accumulated value to the CORDCI calculator for calculation to obtain a calibrated converted signal and a second target value; inputting the calibrated and converted signal, the first target value and the second target value to the approximation calculator for approximation calculation to obtain a down-conversion signal;
and the parallel-serial conversion module is used for inputting the down-conversion signal to a parallel-serial converter for parallel-serial conversion to complete digital conversion.
9. A storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement the operations performed by the parallel digital frequency conversion method of any one of claims 1 to 7.
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