CN112599587B - Semiconductor device with buffer layer structure - Google Patents
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- CN112599587B CN112599587B CN202011443412.4A CN202011443412A CN112599587B CN 112599587 B CN112599587 B CN 112599587B CN 202011443412 A CN202011443412 A CN 202011443412A CN 112599587 B CN112599587 B CN 112599587B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000002019 doping agent Substances 0.000 claims abstract description 214
- 230000005684 electric field Effects 0.000 description 24
- 230000000903 blocking effect Effects 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 7
- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention belongs to the field of power semiconductor device testing, and particularly relates to a semiconductor device with a buffer layer structure, which comprises a first dopant region, a second dopant region, a third dopant region, an upper dopant region, a lower dopant region and a middle dopant region, wherein the first dopant region, the second dopant region and the third dopant region are sequentially arranged; the upper dopant region is located between the first dopant region and the second dopant region; the lower dopant region is located between the second dopant region and the third dopant region; the middle dopant region is positioned between the second dopant regions, and the invention has the advantages of realizing smaller leakage current, thereby improving the voltage endurance capability of the device, the highest operable junction temperature and the current capacity of the device.
Description
Technical Field
The invention belongs to the field of power semiconductor device testing, and particularly relates to a semiconductor device with a buffer layer structure.
Background
As a core component of power equipment, a large-capacity power electronic device has become a key to improve reliability and reduce cost. In the application of unidirectional current and bidirectional blocking, a device is required to have reverse blocking capability, so that a method of connecting an asymmetric device and a diode in series is generally adopted. The reverse resistance device has forward through-current and bidirectional blocking capabilities, can save series diodes, reduces the number of devices, saves cost, reduces loss, and has remarkable advantages in current source converters, bidirectional solid-state circuit breakers and the like.
Traditional asymmetric device changes electric field distribution through setting up buffer layer or field stop layer, under guaranteeing the same withstand voltage condition, reduces the whole piece thickness of device to reduce and switch on voltage drop isoparametric, belong to and wear to lead to the type structure. The non-punch-through IGCT structure with the buffer layer and its internal electric field distribution are shown in fig. 1, and the punch-through IGCT structure and its internal electric field distribution are shown in fig. 2. The buffer layer can change the electric field distribution from triangle to trapezoid, greatly reducing the sheet thickness requirement.
In order to realize the reverse voltage endurance, the reverse resistor device cannot adopt the buffer layer structure shown in fig. 1, because if both sides of the PN junction are highly doped, the electric field distribution is concentrated on both sides of the junction, and after the peak electric field strength exceeds the critical electric field strength, the PN junction will generate avalanche breakdown at a very low voltage. After the buffer layer structure is removed, the leakage current of the device is increased, especially the leakage current at high temperature.
The leakage current of the reverse resistance device mainly consists of two parts, namely body leakage current and edge leakage current. Under the same voltage level, if the same edge termination structure is adopted, the edge leakage currents of the asymmetric device and the reverse resistance device are theoretically the same, but the body leakage currents are completely different. The body leakage current is composed of two parts, one is generated by free carrier diffusion, and the other is generated in a space charge region. The leakage current generated by free carrier diffusion is closely related to the amplification factor of the PNP transistor.
Taking a conventional reverse-resistance IGCT as an example, when the gate cathode is short-circuited, the depletion layer distribution in the forward blocking state is as shown in fig. 3, where W is the depletion layer expansion width, and L is the non-depleted width of the drift region. With the increase of voltage, the width of the undepleted layer is gradually reduced, holes injected from the anode side pass through the undepleted layer under the action of diffusion movement, and carriers drift to the cathode under the action of a strong electric field in a space charge area, so that partial leakage current is formed. In order to realize reverse blocking capability, the J1 junction needs to ensure low doping on one side, so that in a blocking state, the emission efficiency of the anode side of the reverse blocking device is high, and the amplification factor of the PNP transistor is high.
The structure of the conventional reverse blocking device is shown in fig. 4, the device is composed of a first dopant region, a second dopant region and a third dopant region, an emitter structure is often arranged in the first dopant region, and the structure can be ignored when considering device blocking. The first dopant region is connected to the cathode and the second dopant region, and the third dopant region is connected to the anode and the second dopant region. If the first dopant region of the device is doped in a P type, the second dopant region is doped in an N type, the third dopant region is doped in a P type, and when the anode of the device withstands forward voltage, the voltage is withstood by a PN junction between the first dopant and the second dopant; when the anode of the device is endured by the reverse voltage, the voltage is endured by the PN junction between the second dopant and the third dopant.
Disclosure of Invention
In the application scenario of high voltage direct current, it is required that the blocking voltage level of the switching device is as high as possible and the leakage current is as low as possible. The smaller leakage current can not only reduce the loss of the system, but also improve the voltage endurance capability of the device, the highest operable junction temperature and the current capability of the device. In order to solve the above problems, the present patent proposes a semiconductor device having a buffer layer structure.
The specific technical scheme is as follows:
a semiconductor device with a buffer layer structure comprises a first dopant region (1), a second dopant region (2) and a third dopant region (3) which are sequentially arranged, and further comprises an upper dopant region (4), a lower dopant region (5) and a middle dopant region (6) which are arranged in a one-or-more combined mode;
the upper dopant region (4) is located between the first dopant region (1) and the second dopant region (2);
the lower dopant region (5) is located between the second dopant region (2) and the third dopant region (3);
the middle dopant region (6) is located in the middle of the second dopant region (2).
Specifically, the upper dopant region (4) and the lower dopant region (5) are located at a PN junction position subjected to withstand voltage
In particular, the upper dopant region (4) and the lower dopant region (5) are of the same doping type as the second dopant region (2).
In particular, the upper dopant region (4) and the lower dopant region (5) are doped N-type.
Specifically, the upper dopant region (4) and the lower dopant region (5) have a thickness of 1-10 um.
In particular, the upper dopant region (4) and the lower dopant region (5) have a doping concentration greater than the concentration of the second dopant region (2) and less than the peak concentration of the third dopant region (3).
Specifically, the doping concentration of the upper dopant region (4) and the lower dopant region (5) ranges from 1e13 to 1e16cm-3。
Specifically, a second dopant upper region (21) and a second dopant lower region (22) are respectively arranged on two sides of the middle dopant region (6); the thickness of the middle dopant region (6) is less than the thickness of the second upper dopant region (21) and the second lower dopant region (22). .
Specifically, the thickness of the middle dopant region (6) ranges from 1 um to 50 um.
In particular, if the doping type of the central dopant region (6) is the same as the type of the two parts into which the second dopant region (2) is divided, the doping concentration of the central dopant region (6) is greater than the doping concentration of the second dopant region (2).
Specifically, the doping concentration of the middle dopant region (6) ranges from 1e13 to 1e16cm-3。
The invention has the advantages that:
(1) the corresponding structure when the upper dopant region and the lower dopant region are arranged, and the doping concentration of the transparent buffer layer is higher than that of the n-base region, so that the electric field intensity change slope of the transparent buffer layer is larger according to the Poisson equation. However, the transparent buffer layer is very thin, so that the actual adjusting effect on the electric field distribution is very small and even negligible, and under the condition, the device still belongs to a non-through type and the bidirectional blocking capability of the device can be ensured. The transparent buffer layer can reduce the emission efficiency of the PNP transistor under low current density, greatly reduces leakage current formed by free carrier diffusion under the condition of not increasing the thickness of the sheet, and is particularly suitable for various semiconductor reverse resistance devices.
(2) The middle dopant region structure has a modulation effect on an electric field, the doping concentration and thickness of the second dopant upper region, the second dopant lower region and the middle dopant region are matched to reduce the whole thickness of the device, so that the voltage drop of the device is reduced, meanwhile, the leakage current formed by free carrier diffusion can be effectively inhibited, the loss of the system is reduced, the highest operable junction temperature of the device is improved, and the through-current capacity of the device is increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a non-punch-through IGCT structure and its internal electric field distribution plot;
FIG. 2 is a diagram of a punch-through IGCT structure and its internal electric field profile;
FIG. 3 is a graph of a conventional reverse-blocking IGCT depletion layer profile;
FIG. 4 is a structural view of a conventional reverse resistance device;
fig. 5 is a semiconductor device structure having an upper dopant region and a lower dopant region;
fig. 6 is a semiconductor device structure having a central dopant region;
FIG. 7 is a graph of the electric field strength at different locations corresponding to forward withstand voltage and reverse withstand voltage for a reverse blocking IGCT having an upper dopant region and a lower dopant region;
fig. 8 is a diagram of the structure of a reverse-blocking IGCT with a central dopant region, and plots of the electric field strength at different locations for the forward withstand voltage and the reverse withstand voltage.
The reference numerals are explained below:
1. a first dopant region; 2. a second dopant region; 21. a second dopant upper region; 22. a second dopant lower region; 3. a third dopant region; 4. an upper dopant region; 5. a lower dopant region; 6. middle dopant region
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A semiconductor device with a buffer layer structure comprises a first dopant region 1, a second dopant region 2 and a third dopant region 3 which are sequentially arranged, and at least one other dopant region is arranged between the first dopant region 1 and the third dopant region 3. Specifically, the other dopant region includes the following technical schemes: as shown in fig. 5-6, an upper dopant region 4 located between the first dopant region 1 and the second dopant region 2, a lower dopant region 5 located between the second dopant region 2 and the third dopant region 3, and a middle dopant region 6 located in the middle of the second dopant region 2; two embodiments are explained below.
The first scheme is as follows:
as shown in fig. 5, the upper dopant region 4 and the lower dopant region 5 are simultaneously provided. The upper dopant region 4 and the lower dopant region 5 are located at a PN junction position which bears withstand voltage; the doping type of the upper dopant region 4 and the doping type of the lower dopant region 5 are the same as the doping type of the second dopant region 2, and in a specific embodiment of the reverse blocking device, the second dopant type is N-type doping; in the semiconductor structure, both P-type doping and N-type doping are possible. The upper dopant region 4 and the lower dopant region 5 are each 1-10um thick, with a doping concentration greater than the concentration of the second dopant region 2, and the peak concentration of the third dopant region 3. In this scheme, the doping concentrations of the upper dopant region 4 and the lower dopant region 5 are 1e13-1e16cm-3。
When the scheme is applied to a specific reverse-resistance IGCT, as shown in fig. 7, the first dopant region 1 is a P-base region, the second dopant region 2 is an n-base region, the third dopant region 3 is a P + emitter, the upper dopant region 4 is located between the P-base region and the n-base region, the lower dopant region 5 is located between the n-base region and the P + emitter, the P + base region is disposed on the outer side of the P-base region, the n + emitter is disposed in the middle of the outer side of the P + base region and serves as a cathode, gate electrodes are disposed on two sides, and the upper dopant region 4 and the lower dopant region 5 are collectively referred to as a transparent buffer layer. In the scheme, the thickness of a P + emitter on the anode side is 50-120um, and the peak doping concentration is 1e14-1e16cm-3(ii) a The thickness of the n + emitter of the cathode region is 10-25um, and the peak doping concentration is 1e18-1e21cm-3(ii) a The thickness of the P + base region is 30-60um, and the peak doping concentration is 1e16-1e18cm-3(ii) a The thickness of the P base region is 50-120um, and the peak doping concentration is 1e14-5e15cm-3(ii) a The doping concentration of the drift region n-base region is 5e11-1e14cm-3In this case less than 5e13cm-3(ii) a The above peak doping concentration refers to the net doping concentration and to the concentration maximum in the layers in the actual structure.
The electric field distribution of the structure in forward voltage resistance and reverse voltage resistance is shown in fig. 7, and the electric field intensity change slope of the transparent buffer layer is larger according to the poisson equation because the doping concentration of the transparent buffer layer is higher than that of the n-base region. However, the transparent buffer layer is very thin, so that the actual adjusting effect on the electric field distribution is very small and even negligible, and under the condition, the device still belongs to a non-through type and the bidirectional blocking capability of the device can be ensured. The transparent buffer layer can reduce the emission efficiency of the PNP transistor under low current density, greatly reduces leakage current formed by free carrier diffusion under the condition of not increasing the thickness of the sheet, and is particularly suitable for various semiconductor reverse resistance devices.
The second scheme is as follows:
as shown in fig. 6, the middle portion of the second dopant region 2 is provided with a middle dopant region 6, and the middle dopant region 6 divides the second dopant region 2 in the conventional structure into an upper portion and a lower portion, which are a second dopant upper region 21 and a second dopant lower region 22, respectively. In this scheme, the central dopant region 6 is located at the center of the overall structure; the doping type of the middle dopant region 6 may be the same as or opposite to that of the second dopant region 2; if the middle dopant region 6 is of the same type as the second dopant region 2, its dopant concentration is greater than the concentration of the second dopant region 2. The middle dopant region 6 has a thickness less than both the second dopant upper region 21 and the second dopant lower region 22, specifically less than 50 um.
The scheme is applied to a specific reverse-resistance IGCT, as shown in fig. 8, wherein the first dopant region 1 is a P-base region, the second dopant region 2 is an n-base region, the third dopant region 3 is a P + emitter, the middle dopant region 6 divides the second dopant region 2 into a second dopant upper region 21 and a second dopant lower region 22, wherein the P + base region is arranged outside the P-base region, the n + emitter is arranged in the middle of the outside of the P + base region and serves as a cathode, and gate electrodes are arranged on both sides. In this scheme, the doping type of the middle dopant region 6 may be N-type doping or P-type doping, and specifically, the thickness of the middle dopant region 6 ranges from 1 um to 50um, and the doping concentration ranges from 1e13 to 1e16cm-3(ii) a The characteristics of the anode side P + emitter, the P base region and the P + base region in the structure are the same as those of the reverse-resistance IGCT with the transparent buffer layer in the first mode. The electric field profile will be different when the doping type of the central dopant region 6 is different. When the doping type of the middle dopant region 6 is N-type doping, the electric field distribution at the forward withstand voltage is as shown in the forward withstand voltage 1 in fig. 8, and the variation tendency of the electric field intensity in the coordinate direction is the same as that of the second dopant upper region 21 and the second dopant lower region 22, but the slope is larger than that of the second dopant upper region 21 and the second dopant lower region 22. When the doping type of the middle dopant region 6 is P-type doping, the electric field distribution at the forward withstand voltage is as shown by the forward withstand voltage 2 in fig. 8, and the variation tendency of the electric field intensity in the coordinate direction is opposite to that of the second dopant upper region 21 and the second dopant lower region 22.
The structure of the middle dopant region 6 has a modulation effect on an electric field, the doping concentration and thickness of the second dopant upper region 21, the second dopant lower region 22 and the middle dopant region 6 are matched to reduce the whole thickness, so that the voltage drop of the device is reduced, meanwhile, the leakage current formed by free carrier diffusion can be effectively inhibited, the loss of a system is reduced, the highest operational junction temperature of the device is improved, and the through-current capacity of the device is increased.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A semiconductor device with a buffer layer structure, wherein the semiconductor device is a reverse-resistance IGCT, and comprises a first dopant region (1), a second dopant region (2) and a third dopant region (3) which are arranged in sequence,
further comprising an upper dopant region (4), a lower dopant region (5) and a middle dopant region (6);
the first dopant region (1) is a P base region, the second dopant region (2) is an n-base region, the third dopant region (3) is a P + emitter, a P + base region is arranged on the outer side of the P base region, an n + emitter serving as a cathode is arranged in the middle of the outer side of the P + base region, and gate poles are arranged on two sides of the n + emitter; the doping concentration of the upper dopant region (4) and the lower dopant region (5) is greater than the concentration of the second dopant region (2); the upper dopant region (4) and the lower dopant region (5) are positioned at a PN junction position bearing a withstand voltage, and the thickness of the upper dopant region (4) and the thickness of the lower dopant region (5) are 1-10 mu m; the upper dopant region (4) and the lower dopant region (5) are buffer layers, and the doping types of the upper dopant region (4) and the lower dopant region (5) are the same as those of the second dopant region (2);
the upper dopant region (4) is located between the first dopant region (1) and the second dopant region (2);
the lower dopant region (5) is located between the second dopant region (2) and the third dopant region (3);
the middle dopant region (6) is positioned in the middle of the second dopant region (2), the middle dopant region (6) is doped in an N type or a P type, and a second dopant upper region (21) and a second dopant lower region (22) are respectively arranged on two sides of the middle dopant region (6); the thickness of the middle dopant region (6) is smaller than the thickness of the second upper dopant region (21) and the thickness of the second lower dopant region (22), and if the doping type of the middle dopant region (6) is the same as the type of the two parts divided by the second dopant region (2), the doping concentration of the middle dopant region (6) is greater than that of the second dopant region (2).
2. A semiconductor device having a buffer layer structure according to claim 1, wherein the upper dopant region (4) and the lower dopant region (5) have a doping concentration which is less than the peak concentration of the third dopant region (3).
3. The semiconductor device with the buffer layer structure as claimed in claim 1, wherein the upper dopant region (4) and the lower dopant region (5) have a doping concentration in the range of 1e13-1e16cm-3。
4. A semiconductor device having a buffer layer structure according to claim 1, wherein the thickness of the central dopant region (6) is in the range of 1-50 μm.
5. A semiconductor device having a buffer layer structure according to claim 1, wherein the doping concentration of the central dopant region (6) is in the range of 1e13-1e16cm-3。
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| CN102687277A (en) * | 2009-11-02 | 2012-09-19 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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| CN110534567A (en) * | 2019-09-06 | 2019-12-03 | 电子科技大学 | A kind of silicon carbide gate level turn-off thyristor |
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| CN102687277A (en) * | 2009-11-02 | 2012-09-19 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN106098553A (en) * | 2015-04-30 | 2016-11-09 | 英飞凌科技股份有限公司 | Semiconductor device is manufactured by epitaxial growth |
| CN107591454A (en) * | 2016-07-07 | 2018-01-16 | 英飞凌科技股份有限公司 | Semiconductor devices and the method for forming semiconductor devices |
| CN110521000A (en) * | 2017-04-24 | 2019-11-29 | 力特半导体（无锡）有限公司 | Improved field prevents thyristor structure and its manufacturing method |
| CN110534567A (en) * | 2019-09-06 | 2019-12-03 | 电子科技大学 | A kind of silicon carbide gate level turn-off thyristor |
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