CN112599583A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN112599583A
CN112599583A CN202011481726.3A CN202011481726A CN112599583A CN 112599583 A CN112599583 A CN 112599583A CN 202011481726 A CN202011481726 A CN 202011481726A CN 112599583 A CN112599583 A CN 112599583A
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China
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voltage signal
low
level voltage
area
signal line
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Granted
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CN202011481726.3A
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CN112599583B (en
Inventor
刘金贵
李颖
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Priority to CN202011481726.3A priority Critical patent/CN112599583B/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light

Abstract

The present application relates to a display panel and a display device. The display panel includes a display area and a non-display area disposed around the display area, and further includes: the array structure layer comprises a substrate, an array structure layer, a light-emitting device layer comprising a first electrode and a second electrode and an encapsulation layer; the substrate is provided with a first area and a second area, the second area comprises an auxiliary packaging area, a packaging retaining wall area and an edge packaging area, the auxiliary packaging area is positioned between the first area and the packaging retaining wall area, and the edge packaging area is positioned on one side, far away from the auxiliary packaging area, of the packaging retaining wall area; the low-level voltage signal line is arranged in the second area and on the surface of one side, far away from the substrate, of the array structure layer, and the low-level voltage signal line is electrically connected with the second electrode; and the low-level voltage signal extension line is electrically connected to one end of the low-level voltage signal line, which is far away from the substrate, and extends to one side of the packaging layer, which is far away from the substrate, along the light-emitting direction which is perpendicular to the light-emitting device. The application provides a display panel can reduce the voltage drop of fixed voltage signal line.

Description

Display panel and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
An OLED (Organic light-emitting diode) display panel is widely popularized due to its advantages of low power consumption, high saturation, wide viewing angle, thin thickness, flexibility, and the like.
In the current development trend, the OLED display panel is being developed toward the direction of light and thin and narrow bezel. The OLED display panel comprises a display area and a non-display area which is arranged around the display area in the horizontal direction. The non-display area is generally used to arrange signal lines, such as high-level voltage signal lines, low-level voltage signal lines, and other fixed voltage signal lines. Under the technical background of narrow frame design of the OLED display panel, the width of a non-display area in the horizontal direction of the OLED display panel is smaller and smaller, and then the line width of a fixed voltage signal line arranged in the non-display area is smaller and smaller, so that the voltage drop of the fixed voltage signal line is increased, and the luminous efficiency of the OLED display panel is influenced.
Therefore, how to reduce the voltage drop of the fixed voltage signal line without changing the width of the frame is an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
Therefore, it is necessary to provide a display panel for reducing the voltage drop of the fixed voltage signal lines without changing the width of the frame; the display panel that this application provided, including the display area with around the non-display area that the display area set up, further include:
the substrate is provided with a first area corresponding to the display area and a second area corresponding to the non-display area, the second area sequentially comprises an auxiliary packaging area, a packaging retaining wall area and an edge packaging area along the direction far away from the first area, the auxiliary packaging area is positioned between the first area and the packaging retaining wall area, and the edge packaging area is positioned on one side, far away from the auxiliary packaging area, of the packaging retaining wall area;
the array structure layer is arranged on one side of the substrate;
the light-emitting device layer is arranged on one side, away from the substrate, of the array structure layer and comprises a first electrode, a second electrode and a light-emitting device;
the packaging layer is arranged on one side, far away from the array structure layer, of the light-emitting device layer and covers the light-emitting device in the first area, and the packaging layer is arranged in the auxiliary packaging area and the packaging retaining wall area and covers the array structure layer in the second area;
the low-level voltage signal line is arranged on the surface of one side, away from the substrate, of the array structure layer in the second area and is electrically connected with the second electrode;
and the low-level voltage signal extension line is electrically connected to one end, far away from the substrate, of the low-level voltage signal line and extends to one side, far away from the substrate, of the packaging layer along the light-emitting direction perpendicular to the light-emitting device.
In one embodiment, the display panel further includes: the touch control structure layer is arranged on one side, far away from the light-emitting device layer, of the packaging layer; one end, far away from the low-level voltage signal line, of the low-level voltage signal extension line extends in the direction close to the touch control structure layer and is arranged at intervals with the touch control structure layer.
In one embodiment, the low-level voltage signal extension line extends beyond the boundary of the encapsulation layer on the side of the encapsulation layer away from the substrate in the direction away from the low-level voltage signal line.
In one embodiment, the low-level voltage signal lines are distributed across the auxiliary package region, the package retaining wall region and the edge package region, and one end of the low-level voltage signal line, which is far away from the first region, is disposed in the edge package region.
In one embodiment, in the edge encapsulation region, an orthogonal projection of the low-level voltage signal line on the substrate and an orthogonal projection of the encapsulation layer on the substrate at least partially overlap each other.
In one embodiment, in the edge encapsulation region, the low-level voltage signal line extends in a direction away from the first region and breaks through a boundary of the encapsulation layer.
Preferably, in the edge encapsulation region, the encapsulation layer covers the low-level voltage signal line.
Preferably, the display panel further includes a protective layer disposed in the edge sealing region, and the protective layer covers a boundary of the low-level voltage signal line in the edge sealing region;
in one embodiment, the low-level voltage signal lines include a first sub low-level voltage signal line and a second sub low-level voltage signal line which are located on different conductive layers and electrically connected to each other, and the first sub low-level voltage signal line crosses the auxiliary encapsulation area, the encapsulation barrier area and the edge encapsulation area in a cross section of the non-display area; the cross section of the second sub-low level voltage signal line in the non-display area crosses the auxiliary packaging area, the packaging retaining wall area and the edge packaging area.
In one embodiment, the low-level voltage signal lines further include a third sub low-level voltage signal line, the first sub low-level voltage signal line, the second sub low-level voltage signal line, and the third sub low-level voltage signal line are located on different conductive layers, the first sub low-level voltage signal line and the third sub low-level voltage signal line are electrically connected to each other, and the third sub low-level voltage signal line crosses the auxiliary encapsulation area, the encapsulation barrier area, and the edge encapsulation area in a cross section of the non-display area.
In one embodiment, the first electrode is an anode and the second electrode is a cathode.
The application further provides a display device comprising the display panel according to any one of the embodiments.
In the display panel of the embodiment of the application, since the low-level voltage signal extension line is electrically connected to one end of the fixed voltage signal line, which is far away from the fixed voltage signal line substrate, of the low-level voltage signal line and extends to one side of the fixed voltage signal line packaging layer, which is far away from the fixed voltage signal line substrate, along the light emitting direction perpendicular to the fixed voltage signal line light emitting device, so that on the premise of not widening the width of the first region, the space of the display panel in the direction perpendicular to the substrate is fully utilized, the routing width of the low-level voltage signal line is increased, the resistance of the low-level voltage signal line is reduced, the voltage drop of the low-level voltage signal line is reduced, the influence of the problem of overlarge voltage drop in the low-level voltage signal line on the display uniformity of the display panel is reduced, the possibility of uneven display brightness of the display panel is reduced, and, reducing the voltage drop of the fixed voltage signal line is a technical problem that needs to be solved by those skilled in the art.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of the display panel of FIG. 1 along the direction B-B according to the embodiment of the present application;
FIG. 3 is a schematic diagram of a partial cross-sectional structure of a display panel according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a partial cross-sectional structure of a display panel according to still another embodiment of the present application;
FIG. 5 is a schematic diagram of a partial cross-sectional structure of a display panel according to yet another embodiment of the present application;
FIG. 6 is a schematic diagram of a partial cross-sectional structure of a display panel according to still another embodiment of the present application;
fig. 7 is a schematic partial cross-sectional structural view of a display panel according to another embodiment of the present application;
fig. 8 is a schematic top view of a display device according to an embodiment of the present application.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Embodiments of a display panel and a display device are described below with reference to the accompanying drawings.
The Display panel provided in the embodiment of the present application may be an Organic Light Emitting Diode (OLED) Display panel or a Liquid Crystal Display (LCD) panel, which is not limited in the present application.
Fig. 1 shows a schematic top view of a display panel according to an embodiment of the present application. Fig. 2 shows an exemplary schematic cross-sectional view along the direction B-B in fig. 1. Referring to fig. 1 and fig. 2, a display panel 100 according to an embodiment of the present disclosure has a display area AA and a non-display area NA. The display area AA has a plurality of pixels for displaying a picture. The non-display area NA is disposed around the display area AA. Fig. 1 shows that the display area AA of the display panel 100 is a regular rectangle; it is understood that the display area AA of the display panel 100 may be provided in other shapes.
Referring to fig. 2, the display panel 100 provided in the embodiment of the present disclosure may include a substrate 10, an array structure layer 20, a light emitting device layer 30, an encapsulation layer 40, and a touch structure layer TP, where the array structure layer 20 is disposed on one side of the substrate 10, the light emitting device layer 30 is disposed on one side of the array structure layer 20 away from the substrate 10, the encapsulation layer 40 is disposed on one side of the light emitting device layer 30 away from the array structure layer 20, and the touch structure layer TP is disposed on one side of the encapsulation layer 40 away from the light emitting device layer 30. Alternatively, the substrate 10 may be a flexible substrate, but may also be a rigid substrate; the touch structure layer TP may use a Metal Mesh (Metal Mesh) as a Mesh electrode, or may use a block electrode formed by Indium Tin Oxide (ITO), which is not limited in this application.
In the embodiment of the present application, the substrate 10 has a first area 11 corresponding to the display area AA and a second area 12 corresponding to the non-display area NA. The second region 12 may be further divided into an auxiliary encapsulation region 121, an encapsulation wall region 122, and an edge encapsulation region 123. The auxiliary packaging region 121 is located between the first region 11 and the packaging retaining wall region 122. The edge sealing region 123 is located on a side of the sealing wall region 122 away from the auxiliary sealing region 121. It is understood that none of the auxiliary package region 121, the package wall region 122 and the edge package region 123 are used for displaying, and the auxiliary package region 121 is generally used for arranging metal traces of the display panel, for example: a gate driving circuit and the like for outputting a Scan Signal (Scan Signal) or a light emitting control Signal (Emit Signal) to drive the display of the display panel 100, so that the auxiliary packaging region 121 adopts a thin film packaging structure which is the same as the packaging layer 40 in the first region 11 and is formed by overlapping a first inorganic layer, an organic layer and a second inorganic layer to protect the internal wiring; the encapsulation barrier region 122 is formed by disposing an elevated encapsulation barrier on a side of the auxiliary encapsulation region 121 away from the first region 11, so as to extend the distance of water vapor and oxygen from penetrating into the first region 11, and enhance the structural stability of the display panel 100 in the second region 12; the edge sealing region 123 is generally located at an edge position of the display panel 100, and in some alternative embodiments, the edge sealing region 123 may also include a sealing wall, so as to further improve the structural stability of the display panel 100 in the second region 12 while extending the distance of water vapor and oxygen from the first region 11.
In the embodiment of the present application, the light emitting device layer 30 is disposed in the display area AA and on a side of the array structure layer 20 away from the substrate 10. The light emitting device layer 30 includes a pixel defining layer 31 and a plurality of light emitting devices 32. The pixel defining layer 31 has a plurality of openings. The light emitting device 32 is located within the opening. The light emitting device 32 may be an organic light emitting device. The light emitting device 32 may include a first electrode 321, a second electrode 322, and an organic light emitting layer 323 between the first electrode 321 and the second electrode 322. When voltages are applied to the first electrode 321 and the second electrode 322, the organic light-emitting layer 323 emits light. The light emitting device 32 may include a red light emitting device, a green light emitting device, and a blue light emitting device, thereby realizing color display; the light emitting device 32 may further include a white light emitting device to enhance color expression of the display panel 100; in addition, in the embodiment of the present application, the light emitting device 32 may further include quantum dots (quantum dots) to reduce power consumption of the display panel 100 on the premise of maintaining or improving brightness. The present application is not limited to the color and the specific structure of the light emitting device 32.
It will be understood by those skilled in the art that the display panel 100 can be either a top emission display panel or a bottom emission display panel. When the display panel 100 is a top emission display panel, the first electrode 321 is an anode and the second electrode 322 is a cathode; when the display panel 100 is a bottom emission display panel, the first electrode 321 is a cathode and the second electrode 322 is an anode. As an example, the content shown in the present specification and the drawings of the present specification is only the case when the display panel 100 is a top emission display panel, and in fact, the display panel 100 provided in the embodiments of the present application may also be a bottom emission display panel, and the present application does not further describe the case when the display panel 100 may also be a bottom emission display panel.
In the embodiment of the present application, the array structure layer 20 includes a plurality of driving elements T. The driving element T, which is part of the pixel driving circuit, typically functions as a control element or switching element, driving the light emitting devices 32 in the light emitting device layer 30 to emit light. Further, the driving element T may include an active layer 21, a gate electrode 22, a source electrode 23, and a drain electrode 24. The connection relationship shown in the specification and the drawings of the specification is just one possible case where the drain electrode 24 of the driving element T is connected to one of the electrodes of the light emitting device 32, and in the embodiment of the application, the case where the drain electrode 24 of the driving element T is connected to the drain electrode 24 of the light emitting device 32 is shown. In other possible cases, the source 23 of the driving element T may be connected to one of the electrodes of the light emitting device 32, which is not limited in the embodiment of the present application.
In the embodiment of the present application, the display panel 100 further includes a light emission control circuit (EM) including a fixed voltage signal line, and further including a high level voltage signal line (ELVDD, not shown) and a low level voltage signal line 60 (ELVSS). A high-level voltage Signal line for transmitting a high-level Signal (VDD Signal), which is generally connected to the source 23 of the driving element T functioning as a control; the low-level voltage signal line 60 is connected to the cathode, and in the embodiment of the present application, the second electrode 322 is a cathode, so in the drawings, the low-level voltage signal line 60 is actually connected to the second electrode 322, and in other embodiments, such as a bottom emission display panel, the first electrode 321 is a cathode, and the low-level voltage signal line 60 is connected to the first electrode 321. In a more preferred embodiment, the first electrode 321 is an anode, the second electrode 322 is a cathode, and the low-level voltage signal line 60 is electrically connected to the second electrode 322.
In the embodiment of the present application, the array structure layer 20 further includes a capacitor C. The capacitor C may include a first plate 28 and a second plate 29. The first electrode plate 28 and the second electrode plate 29 are insulated and stacked. The array structure layer 20 further includes a plurality of insulating layers, for example: a gate insulating layer 25, a capacitor insulating layer 26, and an interlayer insulating layer 27; the gate insulating layer 25 is disposed between the gate 22 and the active layer 21 to insulate the gate 22 from the active layer 21. In the related process, the first plate 28 and the gate 22 may be formed in the same process step using the same conductive material, i.e., they are disposed in the same layer. It is to be understood that the same layer arrangement refers to structures formed in the same process step, and that the individual structures may or may not be located at the same level. The capacitor insulating layer 26 is disposed between the first plate 28 and the second plate 29, so that the first plate 28 and the second plate 29 are insulated. The interlayer insulating layer 27 is disposed on a side of the capacitor insulating layer 26 away from the substrate 10, and the interlayer insulating layer 27 may have a stacked structure including a plurality of sublayers, and when the interlayer insulating layer 27 has the stacked structure, at least one sublayer of the interlayer insulating layer 27 covers the second plate 29. The source electrode 23 and the drain electrode 24 are generally disposed in the same layer, and are disposed in an insulating manner via an interlayer insulating layer 27, and are disposed separately via the same layerThe corresponding via is connected to the active layer 21. It is understood that the material of the insulating layer is selected from silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride (SiO)xNy) And the examples of this application do not limit this. In a preferred embodiment, the low-level voltage signal line 60 is disposed on a surface of the array structure layer 20 away from the substrate 10 in the second region 12, and further, the low-level voltage signal line 60 is disposed on a surface of the interlayer insulating layer 27 away from the substrate 10.
In the embodiment of the present application, the display panel 100 further includes a planarization layer 80. The planarization layer 80 is disposed on a side of the interlayer insulating layer 27 away from the substrate 10, and the planarization layer 80 covers at least the source electrode 23 and the drain electrode 24. The light emitting device layer 30 is disposed on a side of the planarization layer 80 away from the array structure layer 20, further, the planarization layer 80 is disposed on a side of the array structure layer 20 away from the substrate 10, and specifically, the planarization layer 80 is disposed on a side of the interlayer insulating layer 27 away from the capacitor insulating layer 26. The planarization layer 80 is provided for the purpose of: since the etching process is usually used in the process of manufacturing the source 23 and the drain 24, and the etching process is restricted by the process conditions, it cannot be guaranteed that the surface of the interlayer insulating layer 27 is still flat after etching, and the subsequent process performed on the basis must guarantee that the surface is flat and has no defect, so forming the planarization layer 80 on the side of the interlayer insulating layer 27 away from the substrate 10 after manufacturing the source 23 and the drain 24 helps to guarantee that the surface of the substrate is flat before performing the subsequent process.
In the embodiment of the present application, the display panel 100 further includes an encapsulation layer 40. In the first region 11, the encapsulation layer 40 is disposed on a side of the light emitting device layer 30 away from the array structure layer 20 and covers the light emitting device layer 30, the encapsulation layer 40 at least includes a first inorganic layer 41, an organic layer 42 and a second inorganic layer 43, and the inorganic layer and the organic layer are stacked to provide protection for the light emitting device layer 30: the inorganic layer generally has good compactness and can isolate water vapor and oxygen from the light-emitting device layer 30, the organic layer has the characteristic of flexibility, and the application of the organic layer as one layer of the packaging layer 40 can buffer the stress from the outside for the light-emitting device layer 30, so that the risk of packaging failure caused by the fracture of the inorganic layer is reduced while the display effect of the light-emitting device layer 30 is prevented from being influenced by the outside stress; in the second region 12, the encapsulation layer 40 is disposed on the auxiliary encapsulation region 121, the blocking wall region 122 and covers the array structure layer 40, in the auxiliary encapsulation region 121, the encapsulation layer 40 includes at least a first inorganic layer 41, an organic layer 42, and a second inorganic layer 43, provides protection for the light emitting device layer 30 by stacking the inorganic layer and the organic layer, in the blocking wall region 122, the blocking wall region 122 at least includes a first inorganic layer 41 and a second inorganic layer 43, since the organic layer 42 is typically in the form of a fluid or gel during the fabrication process, by providing the elevated wall structures 50 in the encapsulation wall regions 122, it is effectively avoided that the organic layer 42 overflows in a direction away from the first region 11 to cause package failure, therefore, the solution provided by the present application arranges the retaining wall structure 50 in a dam shape around the first region 11 so that the encapsulation boundary of the organic layer can be defined; further, the encapsulation layer 40 may also extend to the edge encapsulation region 123 along a direction parallel to the substrate 10, thereby extending a path of moisture and oxygen invading the light emitting device 30 from the side of the display panel 100.
In the embodiment of the present application, the display panel 100 further includes a touch structure layer TP, the touch structure layer TP is disposed in the first region 11, and the encapsulation layer 40 is far away from the light emitting device layer 30; it can be understood that, in the first region 11, the touch structure layer TP may be disposed on the whole surface, or a certain space may be left at the edge of the first region 11 to avoid a false touch operation when the display panel is operated. As a better implementation manner, a certain space is left in the edge position of the first region 11 by the touch structure layer TP.
It can be understood by those skilled in the art that the high gray-scale luminance uniformity of the display panel 100 and the voltage drops of the high-level voltage signal lines and the low-level voltage signal lines exhibit negative correlation, in other words, the higher the voltage drop of the high-level voltage signal lines and/or the low-level voltage signal lines, the worse the high gray-scale luminance uniformity of the display panel 100. As described above, the high-level voltage signal line is usually connected to the source 23 of the driving element T for controlling, and directly affects the current of the driving element T for controlling, and the low-level voltage signal line 60 is connected to the cathode and affects the cathode potential of the light emitting device 32, in other words, the low-level voltage signal line 60 and the high-level voltage signal line jointly guarantee the operating voltage of the driving element T for controlling and the light emitting device 32. According to the relationship between the voltage and the current, the wiring voltage drop can be reduced by reducing the wiring resistance of the high-level voltage signal line and the low-level voltage signal line 60, so that the overall brightness uniformity and power consumption of the screen are reduced. For the display panel 100, the number of the traces of the high-level voltage signal lines and the low-level voltage signal lines is relatively determined, and therefore, the trace resistance can be reduced by increasing the width of the traces (i.e., the cross-sectional area of the traces) of the high-level voltage signal lines and/or the low-level voltage signal lines 60 without changing the number of the traces of the high-level voltage signal lines and the low-level voltage signal lines 60. However, since the low-level voltage signal lines 60 are usually mostly disposed in the second region 12, in the context of narrow frame design, the width of the second region 12 in the horizontal direction of the display panel 100 becomes smaller and smaller, and the line width of the low-level voltage signal lines 60 disposed in the second region 12 also becomes smaller and smaller, which results in an increase in voltage drop of the low-level voltage signal lines and an influence on the light emitting efficiency of the display panel 100. Meanwhile, the second electrode 322, i.e. the cathode in the embodiment of the present application, is usually formed on the whole surface in the process, unlike the anode, so that the low-level voltage signal line 60 is connected to the whole surface of the cathode, and the voltage drop of the low-level voltage signal line 60 has a direct influence on the display effect of the display panel 100. Therefore, on the premise of not affecting the high-level voltage signal lines in the existing design, the trace width of the low-level voltage signal lines 60 is improved to reduce the voltage drop of the low-level voltage signal lines 60, and the influence of the problem of overlarge voltage drop in the low-level voltage signal lines 60 on the display uniformity of the display panel 100 is reduced, so that the voltage drop of the low-level voltage signal lines is favorably reduced, and the display uniformity of the display panel 100 is improved.
Based on this, referring to fig. 2, the display panel 100 in the embodiment of the present application further includes a low-level voltage signal extension line 90, and the low-level voltage signal extension line 90 is electrically connected to one end of the low-level voltage signal line 60 away from the substrate 10 and extends to one side of the encapsulation layer 40 away from the substrate 10 along a light emitting direction perpendicular to the light emitting device 323. On the premise of not widening the width of the first region 11, the space of the display panel 100 in the direction perpendicular to the substrate 10 is fully utilized, and the routing width of the low-level voltage signal line 60 is increased, so that the resistance of the low-level voltage signal line 60 is reduced, the voltage drop of the low-level voltage signal line 60 is further reduced, the influence of the problem of overlarge voltage drop in the low-level voltage signal line 60 on the display uniformity of the display panel 100 is reduced, and the possibility of uneven display brightness of the display panel 100 is reduced; it is understood that the material of the low-level voltage signal extension line 90 is the same as the material of the low-level voltage signal line 60, and accordingly, the electrical conductivity of the two lines is the same; in the embodiment of the present application, the low-level voltage signal extension line 90 may also be made of a material with higher conductivity than the low-level voltage signal line 60, which is not limited in the embodiment of the present application.
Alternatively, as shown in fig. 2, on the side of the encapsulation layer 40 away from the substrate 10, the low-level voltage signal extension line 90 extends beyond the boundary of the encapsulation layer 40 in the direction away from the low-level voltage signal line 60, so that the space of the display panel 100 in the direction perpendicular to the substrate 10 is fully utilized under the low-level voltage signal extension line 90, and the resistance of the low-level voltage signal extension line 90 is further reduced, thereby further reducing the voltage drop of the low-level voltage signal line 60.
Alternatively, the low-level voltage signal line 60 and the low-level voltage signal extension line 90 may each include a titanium metal layer and an aluminum metal layer that are stacked. The aluminum metal layer can ensure the conductivity of the low-level voltage signal extension line 90 and the low-level voltage signal extension line 90, and the titanium metal layer can improve the corrosion resistance of the low-level voltage signal extension line 90 and the low-level voltage signal extension line 90, so that the part of the low-level voltage signal line 60 exceeding the encapsulation layer 40 is not easy to corrode.
It is understood that the low-level voltage signal extension line 90 may be formed while the low-level voltage signal line 60 is prepared, so that the encapsulation of the end of the low-level voltage signal extension line 90 away from the low-level voltage signal line 60 may be achieved when the encapsulation layer 40 is prepared, thereby sufficiently utilizing the space of the display panel 100 in the direction perpendicular to the substrate 10 without affecting the encapsulation protection effect. In the embodiment of the present application, the low-level voltage signal extension line 90 may be prepared by forming a through hole after the encapsulation layer 40 is formed, and the material of the low-level voltage signal extension line is the same as that of the first electrode plate 28 or the second electrode plate 29 in the capacitor C, so that the process difficulty may be effectively reduced.
As shown in fig. 3, in the embodiment provided in the present application, one end of the low-level voltage signal extension line 90, which is far away from the low-level voltage signal line 60, may further extend in a direction close to the touch structure layer TP and be disposed at an interval with the touch structure layer TP, which is equivalent to that, under the condition that the frame width of the display panel 100 is not increased, the space width reserved at the same layer position of the touch structure layer TP by the display panel 100 is utilized, the routing width of the low-level voltage signal line 60 is further increased, the resistance of the low-level voltage signal line 60 can be effectively reduced, so as to reduce the voltage drop of the level voltage signal line 60, reduce the problem of too large voltage drop in the low-level voltage signal line 60, further facilitate improving the display uniformity of the display panel 100, and reduce the possibility that the display brightness. It is understood that the embodiment of the present application does not further limit the distance that the low-level voltage signal extension line 90 extends away from one end of the low-level voltage signal line 60 along the direction close to the touch structure layer TP.
In the display panel 100 provided in the present application, referring to fig. 4, in the embodiment of the present application, the low-level voltage signal line 60 is distributed across the auxiliary package region 121, the blocking wall region 122 and the edge package region 123, in other words, one end of the low-level voltage signal line 60 away from the first region 11 is disposed in the edge package region 123, and the cross section of the package layer 40 in the second region 12 extends across the auxiliary package region 121, the blocking wall region 122 and the edge package region 123. In the edge encapsulation area 123, at least a portion of the orthographic projection of the low-level voltage signal line 60 on the substrate 10 and the orthographic projection of the encapsulation layer 40 on the substrate 10 are overlapped with each other, so that the space of the second area 12 can be fully utilized by the low-level voltage signal line 60, and under the condition that the frame width of the display panel 100 is not increased, the routing width of the low-level voltage signal line 60 can be increased in the second area 12 with a limited size, so that the resistance of the low-level voltage signal line 60 can be effectively reduced, the voltage drop of the low-level voltage signal line 60 is reduced, the problem of overlarge voltage drop in the low-level voltage signal line 60 is reduced, the display uniformity of the display panel 100 is improved, and the possibility of uneven display brightness of the display panel 100 is reduced. As an alternative, in the edge encapsulation area 123, the low-level voltage signal line 60 extends in a direction away from the first area 11 and breaks through the boundary of the encapsulation layer 40, so that the low-level voltage signal line 60 can utilize the space of the second area 12 to the maximum extent without affecting the encapsulation, and the resistance of the low-level voltage signal line 60 is further reduced, thereby further reducing the voltage drop of the low-level voltage signal line 60.
Referring to fig. 2-4, the display panel 100 further includes a protective layer 70. The protection layer 70 is disposed in the edge sealing region 123 and covers the low-level voltage signal line 60 at the boundary of the edge sealing region 123, so as to protect the widened cross section of the low-level voltage signal line 60, and further reduce the possibility of corrosion of the widened low-level voltage signal line 60. Meanwhile, the protective layer 70 may cover the low-level voltage signal line 60 far from the first region 11 and break through the boundary of the encapsulation layer 40, so as to prevent the low-level voltage signal line 60 from being corroded preferentially when water vapor and oxygen invade, thereby making full use of the width space of the display panel 100 in the non-display area NA without affecting the basic function of the low-level voltage signal line 60, reducing the resistance of the low-level voltage signal line 60, and further reducing the voltage drop of the low-level voltage signal line 60.
Referring to fig. 5, in the display panel 100 provided by the present application, in the edge sealing region 123, the sealing layer 40 covers the low-level voltage signal line 60, so that the sealing layer 40 can protect the low-level voltage signal line 60, which is beneficial to reducing the possibility of corrosion of the low-level voltage signal line 60 and reducing the influence of the widened low-level voltage signal line 60 on the package. Optionally, the display panel 100 further comprises a protective layer 70. The protection layer 70 is disposed on the edge sealing region 123. The encapsulation layer 40 covers the protection layer 70. The protective layer 70 covers the boundary of the low-level voltage signal line 60 in the edge sealing region 123, so that the cross section of the widened low-level voltage signal line 60 can be protected, and the possibility of corrosion of the widened low-level voltage signal line 60 can be further reduced.
In the embodiment of the present application, referring to fig. 6, the low-level voltage signal line 60 includes a first sub low-level voltage signal line 61 and a second sub low-level voltage signal line 62 which are located on different conductive layers and electrically connected to each other. The first sub-low-level voltage signal line 61 crosses the auxiliary encapsulation area 121, the encapsulation stopper area 122 and the edge encapsulation area 123 in the cross section of the non-display area NA. The second sub-low-level voltage signal line 62 crosses the auxiliary encapsulation area 121, the encapsulation stopper area 122 and the edge encapsulation area 123 in the cross section of the non-display area NA. Alternatively, the cross section of the second sub-low voltage signal line 62 in the non-display area NA may also cross only the auxiliary package region 121 and the dam region 122. Further, the second sub-low level voltage signal line 62 is disposed on a surface of the capacitor insulating layer 26 away from the substrate 10, and is electrically connected to the first sub-low level voltage signal line 61; by providing the first sub low-level voltage signal line 61 and the second sub low-level voltage signal line 62, on one hand, the cross section of the low-level voltage signal line 60 can be made larger in the limited space of the non-display area NA, and on the other hand, the space of the display panel 100 in the direction perpendicular to the substrate 10 can be more fully utilized by the film thickness reserved in the interlayer insulating layer 27 of the non-display area NA, so that the resistance of the low-level voltage signal line 60 is further reduced, and the voltage drop of the low-level voltage signal line 60 is further reduced.
Optionally, the material of the first sub-low-level voltage signal line 61 is the same as the material of the first plate 29 of the capacitor C1, and the first sub-low-level voltage signal line 61 is disposed in the same layer as the first plate 28, so that the first sub-low-level voltage signal line 61 and the first plate 28 can be formed at the same time in the same process step, which is beneficial to reducing the process complexity and the process cost.
Optionally, the material of the second sub-low-level voltage signal line 62 is the same as the material of the second plate 29 of the capacitor C1, and the second sub-low-level voltage signal line 62 and the second plate 29 are disposed in the same layer, so that the second sub-low-level voltage signal line 62 and the second plate 29 can be formed simultaneously in the same process step, which is beneficial to reducing the process complexity and the process cost.
In the embodiment of the present application, the display panel 100 further includes a first insulating layer. The first insulating layer is positioned between the first sub-low level voltage signal line 61 and the second sub-low level voltage signal line 62. In the edge encapsulation area 123, the first insulating layer covers the second sub-low level voltage signal line 62. The first insulating layer crosses the auxiliary encapsulation region 121, the encapsulation dam region 122 and the edge encapsulation region 123 in a cross section of the non-display region NA. The first insulating layer has a first via. The first sub low-level voltage signal line 61 and the second sub low-level voltage signal line 62 are electrically connected through the first via.
Optionally, the material of the first insulating layer is the same as that of the interlayer insulating layer 27, and the first insulating layer and the interlayer insulating layer 27 are disposed on the same layer, so that the first insulating layer and the interlayer insulating layer 27 can be formed simultaneously in the same process step, which is beneficial to reducing process complexity and process cost.
In the embodiment of the present application, referring to fig. 7, the low-level voltage signal line 60 further includes a third sub-low-level voltage signal line 63. The first sub low-level voltage signal line 61, the second sub low-level voltage signal line 62, and the third sub low-level voltage signal line 63 are located at different conductive layers. The third sub-low-level voltage signal line 63 crosses the auxiliary encapsulation area 121, the encapsulation dam area 122 and the edge encapsulation area 123 in the cross section of the non-display area NA. Further, a third sub low-level voltage signal line 63 is provided on a surface of the gate insulating layer 25 on a side away from the power insulating layer 26, and electrically connected to the first sub low-level voltage signal line 61 and the second sub low-level voltage signal line 62; by providing the first sub low-level voltage signal line 61, the second sub low-level voltage signal line 62, and the third sub low-level voltage signal line 63, on one hand, the cross section of the low-level voltage signal line 60 can be further increased in the limited space of the non-display area NA, and on the other hand, the space of the display panel 100 in the direction perpendicular to the substrate 10 can be further sufficiently utilized by the film thickness reserved in the interlayer insulating layer 27 and the capacitor insulating layer 26 by the non-display area NA, so that the resistance of the low-level voltage signal line 60 is further reduced, and the voltage drop of the low-level voltage signal line 60 is further reduced.
Optionally, the material of the third sub-low-level voltage signal line 63 is the same as the material of the gate 22 of the driving element T, and the third sub-low-level voltage signal line 63 and the gate 22 are disposed in the same layer, so that the third sub-low-level voltage signal line 63 and the gate 22 can be formed simultaneously in the same process step, which is beneficial to reducing the process complexity and the process cost.
Optionally, the display panel 100 further includes a second insulating layer. The second insulating layer is positioned between the second sub low-level voltage signal line 62 and the third sub low-level voltage signal line 63. In the edge encapsulating region 123, the second insulating layer covers the third sub-low-level voltage signal line 63. Illustratively, the second insulating layer crosses the auxiliary encapsulation region 121, the encapsulation dam region 122 and the edge encapsulation region 123 in a cross-section of the non-display area NA. The second insulating layer has a second via. The first and third sub low-level voltage signal lines 61 and 63 are electrically connected through the first and second vias.
Optionally, the material of the second insulating layer is the same as that of the capacitor insulating layer 26, and the second insulating layer and the capacitor insulating layer 26 are disposed on the same layer, so that the second insulating layer and the capacitor insulating layer 26 can be formed simultaneously in the same process step, which is beneficial to reducing process complexity and process cost.
It can be understood that, in the display panel 100 provided in the embodiment of the present application, a passivation layer may be further disposed between the planarization layer 80 and the interlayer insulating layer 27, and since the source electrode 23 and the drain electrode 24 are both made of a metal material, the passivation layer may convert metal surfaces of the source electrode 23 and the drain electrode 24 into a state that is not easily oxidized, so as to slow down corrosion rate of metal used for the source electrode 23 and the drain electrode 24 during a related process or during use of the display panel 100; the passivation layer may be made of at least one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy), so the passivation layer may be a single layer or a stacked layer, in order to ensure the connection relationship between the source electrode 23 or the drain electrode 24 and the first electrode 321, a through hole communicating with the source electrode 23 or the drain electrode 24 is usually formed in the passivation layer along a direction perpendicular to the substrate 10, and a conductive metal is deposited to communicate the source electrode 23 or the drain electrode 24 with the first electrode 321. Optionally, the material of the second sub low-level voltage signal line 62 may be the same as the material of the conductive metal, and the second sub low-level voltage signal line 62 and the conductive metal are disposed on the same layer, so that the second sub low-level voltage signal line 62 and the conductive metal may be formed simultaneously in the same process step, which is beneficial to reducing the process complexity and the process cost.
Based on the same inventive concept, referring to fig. 8, the present application further provides a display device 1000. The display device 1000 includes the display panel 100 provided in any embodiment of the present application. In the present embodiment, the display device 1000 may be a mobile phone, or may be any device having a display function, such as a tablet computer, a notebook, or a display.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A display panel including a display area and a non-display area provided around the display area, the display panel comprising:
the substrate is provided with a first area corresponding to the display area and a second area corresponding to the non-display area, the second area sequentially comprises an auxiliary packaging area, a packaging retaining wall area and an edge packaging area along the direction far away from the first area, the auxiliary packaging area is positioned between the first area and the packaging retaining wall area, and the edge packaging area is positioned on one side, far away from the auxiliary packaging area, of the packaging retaining wall area;
the array structure layer is arranged on one side of the substrate;
the light-emitting device layer is arranged on one side, away from the substrate, of the array structure layer and comprises a first electrode, a second electrode and a light-emitting device;
the packaging layer is arranged on one side, far away from the array structure layer, of the light-emitting device layer and covers the light-emitting device in the first area, and the packaging layer is arranged in the auxiliary packaging area and the packaging retaining wall area and covers the array structure layer in the second area;
the low-level voltage signal line is arranged on the surface of one side, away from the substrate, of the array structure layer in the second area and is electrically connected with the second electrode;
and the low-level voltage signal extension line is electrically connected to one end, far away from the substrate, of the low-level voltage signal line and extends to one side, far away from the substrate, of the packaging layer along the light-emitting direction perpendicular to the light-emitting device.
2. The display panel according to claim 1, characterized in that the display panel further comprises:
the touch control structure layer is arranged on one side, far away from the light-emitting device layer, of the packaging layer; one end, far away from the low-level voltage signal line, of the low-level voltage signal extension line extends in the direction close to the touch control structure layer and is arranged at intervals with the touch control structure layer.
3. The display panel according to claim 2, wherein the low-level voltage signal extension line extends beyond a boundary of the encapsulation layer on a side of the encapsulation layer away from the substrate in a direction away from the low-level voltage signal line.
4. The display panel according to claim 3, wherein the low-level voltage signal lines are distributed across the auxiliary encapsulation region, the blocking wall region and the edge encapsulation region, and one end of the low-level voltage signal line away from the first region is disposed in the edge encapsulation region.
5. The display panel according to claim 4, wherein in the edge encapsulating region, an orthogonal projection of the low-level voltage signal line on the substrate and an orthogonal projection of the encapsulating layer on the substrate at least partially overlap each other.
6. The display panel according to claim 5, wherein in the edge encapsulating region, the low-level voltage signal line extends in a direction away from the first region and breaks through a boundary of the encapsulating layer;
preferably, in the edge encapsulation region, the encapsulation layer covers the low-level voltage signal line;
preferably, the display panel further includes a protective layer disposed in the edge sealing region, and the protective layer covers a boundary of the low-level voltage signal line located in the edge sealing region.
7. The display panel according to claim 3, wherein the low-level voltage signal lines include a first sub-low-level voltage signal line and a second sub-low-level voltage signal line that are located on different conductive layers and electrically connected to each other, the first sub-low-level voltage signal line crossing the auxiliary encapsulation region, the encapsulation wall region, and the edge encapsulation region in a cross section of the non-display region; the cross section of the second sub-low level voltage signal line in the non-display area crosses the auxiliary packaging area, the packaging retaining wall area and the edge packaging area.
8. The display panel according to claim 7, wherein the low-level voltage signal lines further include a third sub-low-level voltage signal line, the first, second, and third sub-low-level voltage signal lines are located on different conductive layers, the first and third sub-low-level voltage signal lines are electrically connected to each other, and the third sub-low-level voltage signal line crosses the auxiliary encapsulation region, the encapsulation barrier region, and the edge encapsulation region in a cross section of the non-display region.
9. The display panel according to claim 1, wherein the first electrode is an anode and the second electrode is a cathode.
10. A display device comprising the display panel according to any one of claims 1 to 9.
CN202011481726.3A 2020-12-15 2020-12-15 Display panel and display device Active CN112599583B (en)

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Publication number Priority date Publication date Assignee Title
CN115311943A (en) * 2022-07-27 2022-11-08 武汉天马微电子有限公司 Display module and display device

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CN109545831A (en) * 2018-11-28 2019-03-29 上海天马微电子有限公司 Display panel and display device
CN109817681A (en) * 2019-01-31 2019-05-28 武汉华星光电半导体显示技术有限公司 Display panel and display device

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Publication number Priority date Publication date Assignee Title
CN109545831A (en) * 2018-11-28 2019-03-29 上海天马微电子有限公司 Display panel and display device
CN109817681A (en) * 2019-01-31 2019-05-28 武汉华星光电半导体显示技术有限公司 Display panel and display device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115311943A (en) * 2022-07-27 2022-11-08 武汉天马微电子有限公司 Display module and display device

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