CN112599576A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN112599576A CN112599576A CN202011455611.7A CN202011455611A CN112599576A CN 112599576 A CN112599576 A CN 112599576A CN 202011455611 A CN202011455611 A CN 202011455611A CN 112599576 A CN112599576 A CN 112599576A
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- 238000005452 bending Methods 0.000 claims abstract description 29
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- 239000010410 layer Substances 0.000 description 38
- 238000006056 electrooxidation reaction Methods 0.000 description 11
- 230000009286 beneficial effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000002035 prolonged effect Effects 0.000 description 3
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- 230000005540 biological transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910001410 inorganic ion Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
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- 238000004806 packaging method and process Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a bending area, wherein a first type signal line group, a second type signal line group and a third type signal line group are arranged in the bending area along a first direction; the first type signal line group comprises at least two first type signal lines arranged along a first direction, and the first type signal lines are used for transmitting first type potential signals; the second type signal line group comprises at least two second type signal lines arranged along a first direction, and the second type signal lines are used for transmitting second type potential signals; the third type signal line group comprises at least two third type signal lines arranged along the first direction, and the third type signal lines are used for transmitting third potential signals. The embodiment of the invention can reduce the probability of corrosion or crack of the signal line and improve the display effect.
Description
Technical Field
The embodiment of the invention relates to a display technology, in particular to an array substrate, a display panel and a display device.
Background
With the development of display technology, the application of display panels is becoming more and more important, the display panels are composed of array substrates and light emitting elements, and accordingly the requirements for the array substrates are also becoming higher and higher.
However, the signal lines in the bending region of the conventional array substrate are easily corroded or cracked, which seriously affects the display effect.
Disclosure of Invention
The invention provides an array substrate, a display panel and a display device, which are used for reducing the probability of corrosion or crack of a signal wire and improving the display effect.
In a first aspect, an embodiment of the present invention provides an array substrate, where the array substrate includes a bending region, where a first type signal line group, a second type signal line group, and a third type signal line group that are arranged along a first direction are disposed in the bending region; the first type signal line group comprises at least two first type signal lines arranged along a first direction, and the first type signal lines are used for transmitting first type potential signals; the second type signal line group comprises at least two second type signal lines arranged along a first direction, and the second type signal lines are used for transmitting second type potential signals; the third type signal line group comprises at least two third type signal lines arranged along the first direction, and the third type signal lines are used for transmitting third potential signals.
Optionally, the first potential signal is a positive potential signal, the second potential signal is a negative potential signal, and the third potential signal is an alternating potential signal; two groups of first type signal line groups respectively positioned at two sides of the third type signal line group are arranged in the bending area; and two groups of second type signal line groups respectively positioned at two sides of the third type signal line group are arranged.
Optionally, in the first type signal line group and the second type signal line group located on the same side of the third type signal line group, a positive potential signal transmitted by the first type signal line close to the second type signal line group is less than or equal to a positive potential signal transmitted by the first type signal line far from the second type signal line group;
and/or, in the first type signal wire group and the second type signal wire group which are positioned on the same side of the third type signal wire group, the negative potential signal transmitted by the second type signal wire close to the first type signal wire group is greater than or equal to the positive potential signal transmitted by the second type signal wire far away from the first type signal wire group.
Optionally, in the first type signal line group and the second type signal line group located on the same side of the third type signal line group, the second type signal line group is located between the first type signal line group and the third type signal line group.
Optionally, in any two adjacent signal line groups, along the first direction, the distance between two adjacent signal lines of different types is greater than the distance between two adjacent signal lines of the same type.
Optionally, the array substrate includes a first conductive layer and a second conductive layer; the first type signal line is positioned on the first conducting layer or the second conducting layer; the second type signal line is positioned on the first conductive layer or the second conductive layer; the third type signal line is located on the first conductive layer or the second conductive layer.
Optionally, in any two adjacent signal line groups, two adjacent signal lines of different types are respectively located on different conductive layers.
Optionally, any two adjacent signal lines are respectively located on different conductive layers.
In a second aspect, an embodiment of the present invention further provides a display panel, where the display panel includes the array substrate according to the first aspect.
In a third aspect, an embodiment of the present invention further provides a display device, where the display panel is described in the second aspect of the display device.
According to the technical scheme of the embodiment of the invention, the adopted array substrate comprises a bending area, wherein a first type signal line group, a second type signal line group and a third type signal line group which are arranged along a first direction are arranged in the bending area; the first type signal line group comprises at least two first type signal lines arranged along a first direction, and the first type signal lines are used for transmitting first type potential signals; the second type signal line group comprises at least two second type signal lines arranged along the first direction, and the second type signal lines are used for transmitting second type potential signals; the third type signal line group comprises at least two third type signal lines arranged along the first direction, and the third type signal lines are used for transmitting third potential signals. In the bending area, the adjacent signal lines with smaller potential difference are more, and the adjacent signal lines with larger potential difference are less, so that the probability of electrochemical corrosion is greatly reduced, the probability of corrosion and cracks of the signal lines is favorably reduced, the yield of the array substrate is improved, the service life is prolonged, and the display effect of the formed display panel is improved.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along line A1A2 in FIG. 1;
FIG. 3 is a further cross-sectional view taken along line A1A2 in FIG. 1;
FIG. 4 is a further cross-sectional view taken along line A1A2 in FIG. 1;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the signal lines in the bending region are prone to crack or corrosion in the prior art array substrate, and the applicant has found through careful study that the reason for this technical problem is: the signal wire in the bending area is easy to permeate into impurities such as water oxygen due to poor packaging effect, and inorganic ions or organic ions may be mixed in the impurities such as the water oxygen, so that an electrolyte solution is formed; when the signal lines in the bending area transmit the signal lines, the potential difference between the adjacent signal lines is large, so that the probability of electrochemical corrosion under the conditions of high temperature, high humidity and the like is high, the signal lines with low potential are corroded, the signal lines with high potential are cracked, and the display effect is greatly influenced.
Based on the technical problem, the invention provides the following solution:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and referring to fig. 1, the array substrate includes a bending region W, and a first type signal line group 10, a second type signal line group 11, and a third type signal line group 12 arranged along a first direction X are disposed in the bending region W; the first-type signal line group 10 includes at least two first-type signal lines 101 arranged along a first direction, the first-type signal lines 101 are used for transmitting first-type potential signals; the second-type signal line group 11 includes at least two second-type signal lines 111 arranged along the first direction X, the second-type signal lines 111 being used for transmitting second-type potential signals; the third-type signal line group 12 includes at least two third-type signal lines 121 arranged in the first direction X, and the third-type signal lines 121 are used to transmit a third potential signal.
Specifically, as shown in fig. 1, the array substrate may include a display area AA and a non-display area, the non-display area includes a bending area W, the display area AA is used for displaying, and a signal line in the array substrate, which needs to be connected to the driving chip, is bent at the bending area W, which is beneficial to reducing a frame of the array substrate.
In this embodiment, the first type signal line group 10, the second type signal line group 11 and the third type signal line group 12 are arranged along a first direction X, the bending region W and the display region AA are arranged along a second direction Y, and the first direction X is perpendicular to the second direction Y; in this embodiment, the number and the arrangement order of the first type signal line group 10, the second type signal line group 11 and the third type signal line group 12 are not specifically limited. The first type signal line 101 is used for transmitting a first type potential signal, the first type potential signal may be a positive potential signal, that is, when the first type signal line works, voltage signals transmitted thereon are all positive potentials, and may be used as a "high level" in driving or testing in the array substrate, and signal potentials transmitted by different first type signal lines 101 may be the same or different; the second type signal line 111 is used for transmitting a second type potential signal, and the second type potential signal may be a negative potential signal, that is, when the second type signal line works, voltage signals transmitted thereon are all negative potentials, and may be used as a "low level" in driving or testing of the array substrate; the third type signal line 121 is used for transmitting a third type potential signal, and the third type potential signal may be an alternating potential signal, that is, when the third type signal line operates, the signal transmitted thereon is an alternating signal, and the alternating signal is a signal with a positive potential and a negative potential alternating with each other, and may be used as a clock signal in driving or testing the array substrate.
In this embodiment, the first-type signal lines 101 in the first-type signal line group 10 are all used for transmitting a first-type potential signal, the second-type signal lines 111 in the second-type signal line group 11 are all used for transmitting a second-type potential signal, the third-type signal lines 121 in the third-type signal line group 12 are all used for transmitting a third-type potential signal, that is, the signal lines in the same-type signal line group are all used for transmitting a same-type potential signal, the signal lines of different types are not arranged alternately, that is, for any signal line, at least one signal line adjacent to the signal line is a signal line of the same type as the signal line, and in the array substrate, the potential difference between different first-type potential signals is small, for example, typical values of positive potentials in the array substrate include two types, namely 7V and 3V, and the potential difference is 4V; and the difference between the first type of potential signal and the second type of potential signal is larger, for example, the typical value of the negative potential in the array substrate includes-7V and-3, even if the potential difference between the second type of signal line for transmitting-3V potential and the first type of signal line for transmitting 3V potential reaches 6V, therefore, in the embodiment, more adjacent signal lines with smaller potential difference and fewer adjacent signal lines with larger potential difference can be arranged in the bending region, thereby greatly reducing the probability of electrochemical corrosion, reducing the probability of corrosion and crack of the signal lines, being beneficial to improving the yield of the array substrate, prolonging the service life and improving the display effect of the formed display panel.
In the technical scheme of this embodiment, the array substrate includes a bending region, and a first type signal line group, a second type signal line group and a third type signal line group arranged along a first direction are disposed in the bending region; the first type signal line group comprises at least two first type signal lines arranged along a first direction, and the first type signal lines are used for transmitting first type potential signals; the second type signal line group comprises at least two second type signal lines arranged along the first direction, and the second type signal lines are used for transmitting second type potential signals; the third type signal line group comprises at least two third type signal lines arranged along the first direction, and the third type signal lines are used for transmitting third potential signals. In the bending area, the adjacent signal lines with smaller potential difference are more, and the adjacent signal lines with larger potential difference are less, so that the probability of electrochemical corrosion is greatly reduced, the probability of corrosion and cracks of the signal lines is favorably reduced, the yield of the array substrate is improved, the service life is prolonged, and the display effect of the formed display panel is improved.
Alternatively, as shown in fig. 1, the first potential signal is a positive potential signal, the second potential signal is a negative potential signal, and the third potential signal is an alternating potential signal; two groups of first type signal wire groups 10 which are respectively positioned at two sides of the third type signal wire group are arranged in the bending area W; and two sets of the second-type signal line group 11 respectively located on both sides of the third-type signal line group 12 are provided.
Specifically, the array substrate generally includes a display area and frame areas located at two sides of the display area and used for setting gate driving circuits, each gate driving circuit needs to be connected with one or more first-type signal lines, and if only one first-type signal group is set, the wiring difficulty between the gate driving circuit farther away from the first-type signal line group and the first-type signal line group is large; similarly, each gate driving circuit needs to be connected with one or more second-type signal lines, and if only one second-type signal line group is arranged, the wiring difficulty between the gate driving circuit far away from the second-type signal line group and the second-type signal line group is also large; therefore, in this embodiment, two first-type signal line groups may be disposed, and are respectively located at two sides of the third-type signal line group; and two second type signal line groups are arranged and respectively positioned at two sides of the third type signal line group, so that the probability of electrochemical corrosion can be reduced. In this embodiment, along the first direction, the third type signal line group is farther from the edge of the array substrate than the first type signal line group and the second type signal line group, and the third type signal line transmits a third potential signal, which is more susceptible to external environment interference than the first type signal line and the second type signal line, so that the third type signal line group is disposed in the middle of the bending region in this embodiment, which is also beneficial to reducing the risk of interference of the third type signal line and improving the working stability of the array substrate.
Optionally, in the first type signal line group and the second type signal line group located on the same side of the third type signal line group, a first potential signal transmitted by the first type signal line close to the second type signal line group is less than or equal to a first potential signal transmitted by the first type signal line far from the second type signal line group; and/or in the first type signal line group and the second type signal line group which are positioned on the same side of the third type signal line group, a second potential signal transmitted by a second type signal line close to the first type signal line group is greater than or equal to a first potential signal transmitted by a second type signal line far away from the first type signal line group.
Exemplarily, as shown in fig. 1, in the first type signal line group 10 and the second type signal line group 11 on the left side of the third type signal line group 12, the first type signal line 101 close to the second type signal line group 11 is used for transmitting a smaller first type potential signal, and the first type signal line 101 far from the second type signal line group 11 is used for transmitting a larger first type potential signal, that is, in the first type signal line group 10, the closer to the first type signal line of the second type signal line group, the smaller the first type potential signal for transmission is, it can be understood that the first type signal lines for transmitting the same first type potential signal are only adjacent, and which is close to the second type signal line group is not specifically limited; with such an arrangement, in the first-type signal line group 10, along the direction close to the second-type signal line group, the first potential signals transmitted by at least two first-type signal lines are in a decreasing relationship, and the potential difference between any two adjacent first-type signal lines is smaller, so as to further reduce the probability of occurrence of electrochemical corrosion risk.
Similarly, the second-type signal line 111 close to the first-type signal line group 10 is used to transmit a larger second-type potential signal, and the second-type signal line 111 far from the first-type signal line group 10 is used to transmit a smaller second-type potential signal, that is, in the second-type signal line group 11, the closer to the second-type signal line of the first-type signal line group, the larger the first-type potential signal used for transmission is, it can be understood that the second-type signal lines used to transmit the same second-type potential signal are only adjacent, and which is close to the first-type signal line group is not specifically limited; by this arrangement, in the second-type signal line group 11, along the direction close to the first-type signal line group 10, the second potential signals transmitted by at least two second-type signal lines are in an increasing relationship, and the potential difference between any two adjacent second-type signal lines is smaller, thereby further reducing the probability of the occurrence of electrochemical corrosion risk.
Meanwhile, in the embodiment, in the two adjacent first type signal line groups and the second type signal line group, the first type signal line closest to the second type signal line group transmits the smallest first type potential signal, and the second type signal line closest to the first type signal line group transmits the largest second type potential signal, that is, the potential difference between the two adjacent first type signal lines and the second type signal line is also small, so that the probability of electrochemical corrosion risk is further reduced, and the probability of corrosion or crack of the signal line is further reduced.
Alternatively, with continued reference to fig. 1, in the first-type signal line group 10 and the second-type signal line group 11 located on the same side of the third-type signal line group 12, the second-type signal line group 11 is located between the first-type signal line group 10 and the third-type signal line group 11.
Specifically, the second type signal line group 11 may include signal lines for extending into the display area AA, for example, if the array substrate is an OLED (Organic Light Emitting Diode) display panel, the display area AA includes a plurality of pixel driving circuits, the pixel driving circuits may include seven transistors and one capacitive pixel driving circuit, which is commonly referred to as a "7T 1C" pixel driving circuit by those skilled in the art, and the specific circuit structure and operation principle thereof are well known by those skilled in the art and will not be described herein again; in the "7T 1C" pixel circuit, a reference signal needs to be input, the reference signal is a negative potential signal, that is, a second potential signal, that is, a greater number of signal lines in the second-type signal line group 11 need to extend to the display area AA, and the second-type signal line group 11 is disposed between the first-type signal line group 10 and the third-type signal line group 12, which is more favorable for the wiring between the bending area W and the display area AA.
Alternatively, with continued reference to fig. 1, in any two adjacent signal line groups, the distance between two adjacent signal lines of different types is greater than the distance between two adjacent signal lines of the same type along the first direction.
Specifically, as shown in fig. 1, since the potential difference between the adjacent different types of signal lines is large and the potential difference between the adjacent same type of signal lines is small, it is possible to set the distance between the adjacent different types of signal lines to be large, as in fig. 1, the distance D1 between the adjacent first type of signal line 101 and second type of signal line is larger than the distance D2 between the adjacent first type of signal line 101 and first type of signal line, and the distance D1 between the adjacent first type of signal line 101 and second type of signal line is larger than the distance D3 between the adjacent second type of signal line 111 and second signal line, so that the probability of electrochemical corrosion occurring between the adjacent different types of signal lines is also small. Illustratively, D2 and D3 may be equal, D1 may have a value greater than or equal to 3 times D1, and greater than or equal to 3 times D2, and D1 may have a value greater than or equal to 3 microns.
Alternatively, fig. 2 is a cross-sectional view taken along a direction A1a2 in fig. 1, and in conjunction with fig. 1 and 2, the array substrate includes a first conductive layer 20 and a second conductive layer 30; the first type signal line 101 is located in the first conductive layer 20 or the second conductive layer 30; the second-type signal line 111 is located in the first conductive layer 20 or the second conductive layer 30; the third-type signal line 121 is located on the first conductive layer 20 or the second conductive layer 30.
Specifically, the array substrate may include a multi-layer structure, such as a substrate, an active layer, a gate electrode layer, a gate insulating layer, a source drain electrode layer, an interlayer insulating layer, a power supply metal layer, and the like; in this embodiment, the first type signal line, the second type signal line, and the third type signal line may be disposed in the first conductive layer or the second conductive layer, the source drain electrode layer is disposed in the first conductive layer, and the power metal layer is disposed in the second conductive layer, which may be used for a larger space for signal line arrangement, and is beneficial to reducing the difficulty of arrangement. The conductive layer may have a Ti/Al/Ti structure, which is not particularly limited in the embodiments of the invention.
Preferably, as shown in fig. 3, fig. 3 is a further cross-sectional view taken along a direction A1a2 in fig. 1, where in any two adjacent signal line groups, two adjacent signal lines of different types are located on different conductive layers respectively.
Illustratively, taking the case where the first-type signal line group 10 includes a first-type signal line 1011 and a second first-type signal line 1012, the second-type signal line group 11 includes a first second-type signal line 1111 and a second-type signal line 1112, and the third-type signal line group 12 includes a first third-type signal line 1211 and a second third-type signal line 1212, where the first-type signal line 1011 may be used to provide the high level VGH of the gate driver circuit, the second first-type signal line 1012 may be used as a display Panel Crack Detect line (PCD), the first second-type signal line 1111 may be used to provide the low level VGL of the gate driver circuit, the second-type signal line 1112 may be used to provide the reference signal VREF of the pixel circuit, the first third-type signal line may be used to provide the first clock signal SCK 1211 of the gate driver circuit, the second third-type signal line 1212 may be used to provide the second clock signal ECK of the gate driving circuit; in this embodiment, the adjacent different types of signal lines may be disposed on different conductive layers, that is, the second first type signal line 1012 and the first second type signal line 1111 are disposed on different conductive layers, and the second type signal line 1112 and the first third type signal line 1211 are disposed on different conductive layers, so that the actual distance between the different types of signal lines may be larger, thereby further reducing the probability of electrochemical corrosion between the adjacent different types of signal lines.
Further, as shown in fig. 4, fig. 4 is a cross-sectional view taken along a direction A1a2 in fig. 1, where any two adjacent signal lines are located on different conductive layers. By the arrangement, the actual distance between any two adjacent signal wires is large, so that the probability of electrochemical corrosion between any two adjacent signal wires can be reduced, the probability of corrosion or cracks of the signal wires is further reduced, the yield of the array substrate is further improved, the service life is prolonged, and the display effect of the formed display panel is improved.
Fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention, referring to fig. 5, the display panel may include a display area AA and a non-display area, a gate driving circuit 40 is disposed in the non-display area, the gate driving circuit 40 is connected to a portion of signal lines in the bending area W, the connection relationship is as described above, the display area AA includes a plurality of pixel circuits 50, each pixel circuit 50 includes a pixel driving circuit and a light emitting unit, the light emitting unit may be, for example, an OLED or a micro led, the pixel circuit 50 is connected to a portion of signal lines in the bending area W, and the connection relationship is as described above; the display panel of the embodiment includes the array substrate provided in any embodiment of the present invention, and thus has the same beneficial effects, which are not described herein again. The display panel may further include an encapsulation layer, for example, in the form of a film package or a glass frit package, and the specific structure is well known to those skilled in the art and will not be described herein again.
Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 6, the display device may be a mobile phone, a tablet computer, a display, a smart watch, a smart helmet or other wearable devices, and the like, and the display device includes the display panel according to any embodiment of the present invention, so that the display device has the same beneficial effects, and details are not repeated herein.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a bending area, wherein a first type signal line group, a second type signal line group and a third type signal line group are arranged in the bending area along a first direction;
the first type signal line group comprises at least two first type signal lines arranged along a first direction, and the first type signal lines are used for transmitting first type potential signals;
the second type signal line group comprises at least two second type signal lines arranged along a first direction, and the second type signal lines are used for transmitting second type potential signals;
the third type signal line group comprises at least two third type signal lines arranged along the first direction, and the third type signal lines are used for transmitting third potential signals.
2. The array substrate of claim 1, wherein the first potential signal is a positive potential signal, the second potential signal is a negative potential signal, and the third potential signal is an alternating potential signal; two groups of first type signal line groups respectively positioned at two sides of the third type signal line group are arranged in the bending area; and two groups of second type signal line groups respectively positioned at two sides of the third type signal line group are arranged.
3. The array substrate of claim 2, wherein, in the first and second signal line groups located on the same side of the third signal line group, a positive potential signal transmitted by the first signal line group close to the second signal line group is less than or equal to a positive potential signal transmitted by the first signal line group far from the second signal line group;
and/or, in the first type signal wire group and the second type signal wire group which are positioned on the same side of the third type signal wire group, the negative potential signal transmitted by the second type signal wire close to the first type signal wire group is greater than or equal to the positive potential signal transmitted by the second type signal wire far away from the first type signal wire group.
4. The array substrate of claim 3, wherein the second type signal line group is located between the first type signal line group and the third type signal line group in the first type signal line group and the second type signal line group located on the same side of the third type signal line group.
5. The array substrate of claim 1, wherein in any two adjacent signal line groups, the distance between two adjacent signal lines of different types is greater than the distance between two adjacent signal lines of the same type along the first direction.
6. The array substrate of claim 1, wherein the array substrate comprises a first conductive layer and a second conductive layer;
the first type signal line is positioned on the first conducting layer or the second conducting layer; the second type signal line is positioned on the first conductive layer or the second conductive layer; the third type signal line is located on the first conductive layer or the second conductive layer.
7. The array substrate of claim 6, wherein in any two adjacent signal line groups, two adjacent signal lines of different types are located on different conductive layers respectively.
8. The array substrate of claim 7, wherein any two adjacent signal lines are located on different conductive layers.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011455611.7A CN112599576A (en) | 2020-12-10 | 2020-12-10 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011455611.7A CN112599576A (en) | 2020-12-10 | 2020-12-10 | Array substrate, display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112599576A true CN112599576A (en) | 2021-04-02 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113363304A (en) * | 2021-06-03 | 2021-09-07 | 武汉天马微电子有限公司 | Display panel and display device |
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| CN107272284A (en) * | 2016-03-31 | 2017-10-20 | 三星显示有限公司 | Display device including flexible display panels |
| CN109961752A (en) * | 2017-12-22 | 2019-07-02 | 三星显示有限公司 | Display device |
| CN110286513A (en) * | 2019-06-27 | 2019-09-27 | 昆山国显光电有限公司 | The processing method of display panel motherboard and display panel |
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| CN107272284A (en) * | 2016-03-31 | 2017-10-20 | 三星显示有限公司 | Display device including flexible display panels |
| CN109961752A (en) * | 2017-12-22 | 2019-07-02 | 三星显示有限公司 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113363304A (en) * | 2021-06-03 | 2021-09-07 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113363304B (en) * | 2021-06-03 | 2022-09-13 | 武汉天马微电子有限公司 | Display panel and display device |
| US11588007B2 (en) | 2021-06-03 | 2023-02-21 | Wuhan Tianma Micro-Electronics Co., Ltd. | Display panel and display device |
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Application publication date: 20210402 |