CN112599521B

CN112599521B - Method and device for optimizing current distribution, integrated circuit chip and electronic equipment

Info

Publication number: CN112599521B
Application number: CN202011462429.4A
Authority: CN
Inventors: 冯东东; 杨洋
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2022-10-14
Anticipated expiration: 2040-12-10
Also published as: CN112599521A

Abstract

The application relates to a method and a device for optimizing current distribution, an integrated circuit chip and electronic equipment, and belongs to the technical field of integrated circuits. The method comprises the following steps: obtaining an analysis result for representing electrostatic discharge of the chip layout; searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result; and when the target through hole VIA with the current value larger than the first preset threshold exists, optimizing the arrangement of the through hole VIA network in the chip layout so as to reduce the maximum current value of the through hole VIA flowing through the optimized through hole VIA network. Based on the analysis result of electrostatic discharge representing the chip layout, when the target through hole VIA with the current value larger than the first preset threshold value is found, the arrangement of the through hole VIA network in the chip layout is optimized, so that the maximum current value flowing through the through hole VIA in the optimized through hole VIA network is reduced, and the problem of unbalanced distribution of the current on the through hole VIA is solved.

Description

Method and device for optimizing current distribution, integrated circuit chip and electronic equipment

Technical Field

The application belongs to the technical field of integrated circuits, and particularly relates to a method and a device for optimizing current distribution, an integrated circuit chip and electronic equipment.

Background

With the continuous progress of semiconductor manufacturing processes, the gate length of Field-Effect transistors (FETs) is from 90nm, 40nm, 28nm before to 16nm, 7nm in current FinFET (Field-Effect Transistor) processes. Under the condition that the metal line width is the same, the cross-sectional area of the metal line is also reduced proportionally with the reduction of the thickness of the metal layer, so the over-current capability of the metal line is weakened, but the requirement of the market for the product to resist the Electro-Static discharge (ESD) current is not changed, for example, the metal connecting line also needs to meet the requirement of Electro-Migration (EM) capability of an ESD Human Body discharge Model (HBM) under the standard of 2kv or 4kv, and is converted into the ESD current which is approximately equal to 1.5A or 3A transient current, so that the contradiction between the metal ESD current/EM resistance and the metal line width is further highlighted.

In order to meet the design requirement of metal wire for resisting ESD current, the current treatment methods include the following steps:

1. and wiring is carried out in a multilayer metal overlapping mode. For example, if one layer of metal has a trace width of 20um, then three layers of metal are stacked together (different layers are connected through VIA), and the trace width is 60um. Therefore, the design requirement of ESD current resistance of the metal wire can be met. However, because the properties of each layer of metal lines are different, such as the sheet resistance, the maximum line width, and the like, and the resistance of each layer of VIA is also different, the resistance value of each line is different, the current is not evenly distributed to the three layers of metal, and the current will take a path with the smallest resistance. Therefore, if the metal is overlapped with the wires and the layout distribution is not proper, the ESD current can flow to the metal circuit with the minimum resistance, and no current or a small amount of ESD current flows through other metal layers; or although a plurality of lines are connected in parallel, the ESD instantaneous current is only concentrated on a certain number of lines, and as a result, the metal lines with the ESD instantaneous large current are blown preferentially.

2. And (6) metal corner processing. The current will concentrate inside the corner during the circuit flowing process, resulting in excessive local current density, so that the metal wire can be trimmed at an angle of 45 deg. and the current distribution can be improved. However, if the corners are not located on the same metal layer, it is necessary to jumper the layout between different metals by connecting different metal layers through VIAs VIA. The disadvantage is that most of the ESD transient current is carried away in the corner areas of the two connecting wires, and the current in other areas is reduced greatly in turn. The instantaneous ESD current is not evenly distributed to each VIA area, so that the VIA current density at the corner still exceeds the standard and exceeds the maximum ESD EM capacity of the metal wire, and the risk of fusing the metal wire is increased.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method, an apparatus, an integrated circuit chip and an electronic device for optimizing current distribution, so as to solve the problem of current distribution imbalance on the VIAs VIA.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a method for optimizing current distribution, including: obtaining an analysis result for representing electrostatic discharge of the chip layout; searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result; and when the target through hole VIA with the current value larger than the first preset threshold value exists, optimizing the arrangement of the through hole VIA network in the chip layout so as to reduce the maximum current value of the through hole VIA flowing through the optimized through hole VIA network. In the embodiment of the application, by obtaining an analysis result representing electrostatic discharge of a chip layout and searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result, when the target through hole VIA with the current value larger than the first preset threshold exists, the arrangement of a through hole VIA network in the chip layout is optimized, so that the maximum current value of the through hole VIA in the optimized through hole VIA network becomes smaller (the originally integrated current is shared by more VIAs, and the maximum current value of the through hole VIA in the optimized through hole VIA network becomes smaller), the problem of unbalanced distribution of the current on the through hole VIA is solved, the phenomenon of current density concentration is improved, the current distribution is more uniform, and the electrostatic discharge (ESD) performance index of a product in design is improved.

With reference to a possible implementation manner of the embodiment of the first aspect, optimizing the arrangement of the VIA networks in the chip layout includes: and optimizing the arrangement of the through hole VIA network on the path of the target through hole VIA. In the embodiment of the application, when the arrangement of the through hole VIA networks in the chip layout is optimized, the arrangement of the through hole VIA networks on the path where the target through hole VIA is located is optimized, the maximum current value of the through hole VIA flowing through the optimized through hole VIA networks can be quickly reduced, and the problem of uneven current distribution is solved.

With reference to a possible implementation manner of the embodiment of the first aspect, optimizing the arrangement of the network of VIA holes VIA on the VIA where the target VIA hole VIA is located includes: and deleting the through hole VIA network on the path of the target through hole VIA. In the embodiment of the present application, when the arrangement of the through-hole VIA networks on the path where the target through-hole VIA is located is optimized, the through-hole VIA networks on the path where the target through-hole VIA is located are directly deleted, so that the optimization speed is further increased, and the current flowing through the through-holes VIA is shared by more through-holes VIA.

With reference to one possible implementation manner of the embodiment of the first aspect, the method further includes: searching whether a target through hole VIA with a current value smaller than a second preset threshold value exists or not based on the analysis result, wherein the second preset threshold value is smaller than the first preset threshold value; and deleting the target through holes VIA with the current value smaller than the second preset threshold value when the target through holes VIA with the current value smaller than the second preset threshold value exist. In the embodiment of the application, whether the target through hole VIA with the current value smaller than the second preset threshold exists or not is searched based on the analysis result, when the target through hole VIA with the current value smaller than the second preset threshold exists, the target through hole VIA with the current value smaller than the second preset threshold is deleted, and through reducing the through holes VIA with small meanings, wiring distribution is simplified, and cost is saved.

With reference to a possible implementation manner of the embodiment of the first aspect, optimizing the arrangement of the VIA networks in the chip layout includes: optimizing the arrangement of the through hole VIA network on the path where the target through hole VIA is located; and determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value. In the embodiment of the application, when the arrangement of the through hole VIA networks in the chip layout is optimized, besides the optimization of the arrangement of the through hole VIA networks on the path where the target through hole VIA is located, it is further determined that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than a first preset threshold, and the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold, so that the problem of local damage caused by excessive current is directly solved.

With reference to one possible implementation manner of the embodiment of the first aspect, determining that the current flowing through any VIA in the optimized VIA network is smaller than the first preset threshold includes: analyzing the electrostatic discharge of the chip layout with the arrangement of the through hole VIA network optimized to obtain a latest analysis result; searching whether a target through hole VIA with a current value larger than the first preset threshold exists or not based on the latest analysis result; and when the target through hole VIA with the current value larger than the first preset threshold value does not exist, determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value. In the embodiment of the application, the electrostatic discharge of the chip layout with the optimized arrangement of the through hole VIA network is analyzed, whether the target through hole VIA with the current value larger than the first preset threshold exists is searched based on the latest analysis result, and when the target through hole VIA with the current value larger than the first preset threshold does not exist, the current flowing through any through hole VIA in the optimized through hole VIA network is determined to be smaller than the first preset threshold, so that the current flowing through any through hole VIA in the optimized through hole VIA network can be ensured to be smaller than the first preset threshold, and the reliability of the result is ensured while the purpose is achieved.

In a second aspect, an embodiment of the present application further provides an apparatus for optimizing current distribution, including: the device comprises an acquisition module and a processing module; the acquisition module is used for acquiring an analysis result for representing the electrostatic discharge of the chip layout; the processing module is used for searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result; and the processing module is further used for optimizing the arrangement of the through hole VIA network in the chip layout when the target through hole VIA with the current value larger than the first preset threshold exists, so that the maximum current value flowing through the through hole VIA in the optimized through hole VIA network is reduced.

In a third aspect, an embodiment of the present application further provides an integrated circuit chip, including: a plurality of metal wire layers; and each two adjacent layers in the multilayer metal wire layers are connected through the through holes VIA, and the arrangement density of the through holes VIA at the corners of the two adjacent layers of metal wire layers is smaller than that of the through holes VIA in the rest areas of the two adjacent layers of metal wire layers.

In a fourth aspect, an embodiment of the present application further provides an electronic device, including: the processor is connected with the memory; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform the method according to the first aspect embodiment and/or any possible implementation manner of the first aspect embodiment.

In a fifth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the method provided in the foregoing first aspect and/or in connection with any one of the possible implementation manners of the first aspect.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The above and other objects, features and advantages of the present application will become more apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application.

Fig. 1 shows a schematic flowchart of a method for optimizing current distribution according to an embodiment of the present application.

Fig. 2 is a diagram illustrating a conventional VIA arrangement between two adjacent metal line layers.

FIG. 3 is a schematic diagram of a resistor network corresponding to the distribution diagram shown in FIG. 2.

Fig. 4 is a distribution diagram of through-hole VIA optimized from the distribution diagram shown in fig. 2 according to an optimization manner provided by an embodiment of the present application.

Fig. 5 is a schematic diagram illustrating a distribution of VIA holes VIA provided in an embodiment of the present application.

Fig. 6 shows a VIA current distribution diagram corresponding to the distribution diagram shown in fig. 5 provided in an embodiment of the present application.

Fig. 7 is a distribution diagram of VIA optimized from the distribution diagram shown in fig. 2 according to another optimization manner provided by the embodiment of the present application.

Fig. 8 shows a block diagram of an apparatus for optimizing current distribution according to an embodiment of the present disclosure.

Fig. 9 shows a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In view of the current imbalance problem of the prior integrated circuit in the VIA. The embodiment of the application provides a method for optimizing current distribution, so that the problem of unbalanced current distribution on a through hole VIA is solved, the phenomenon of current density concentration is improved, the current distribution is more uniform, and the electrostatic discharge (ESD) performance index of a product in design is improved. It should be noted that the metal wiring layer in the integrated circuit is formed by stacking metal wiring layers one on another, and the connection between different metal wiring layers is VIA (VIA), which is called a VIA hole for conducting electricity. The through holes VIA are used for connecting different metal wire layers, and the electric connection between the adjacent metal wire layers is connected through the through holes VIA, wherein the metal wire layers and the through holes VIA can be made of copper, aluminum, gallium and other metal materials.

The method for optimizing the current distribution provided by the embodiment of the present application will be described with reference to fig. 1.

Step S101: and obtaining an analysis result of electrostatic discharge for representing the chip layout.

When the current flowing through a through hole VIA in layout wiring of a digital chip needs to be analyzed, an analysis result for representing the electrostatic discharge of the chip layout is obtained.

As an implementation manner, the obtained analysis result for characterizing the electrostatic discharge of the chip layout may be prepared in advance, and when needed, the analysis result may be directly obtained from a database or a magnetic disk. An optional implementation manner may be obtained in real time, for example, after the layout wiring of the chip is completed, the analysis result of the electrostatic discharge for representing the chip layout is obtained by analyzing the layout wiring.

When analyzing the electrostatic discharge of the chip layout, an existing analysis tool, such as a redlawk tool, may be used. The electrostatic discharge of the chip layout can be analyzed by inputting the layout of the chip and the corresponding netlist into the tool, and a corresponding analysis result is obtained. The specific analysis process is well known to those skilled in the art, and will not be described herein.

Step S102: and searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result.

After an analysis result for representing the electrostatic discharge of the chip layout is obtained, whether a target through hole VIA with a current value larger than a first preset threshold exists is searched for based on the analysis result, and if yes, namely, if the target through hole VIA with the current value larger than the first preset threshold exists, the step S103 is executed; if not, that is, if there is no target VIA having a current value greater than the first preset threshold, the arrangement of the VIA network in the chip layout may not be optimized, and since the current value is not greater than the first preset threshold, the influence on Electromigration (EM) is not great, and thus the optimization may not be performed, where the tendency of EM depends on the current density in the wires and also on the switching rate of signals in the interconnections. When digital signals are switched, there is a transient large current burst, and a small amount of EM may occur during such a large current burst. And analyzing the obtained analysis result to find a large-current path and a key ESD discharge path, and analyzing whether a target through hole VIA with a current value larger than a first preset threshold exists on the paths or not. The high current in the high current path described herein is equivalent to the current in the remaining path, that is, a path having a larger current than the current in the remaining path is the high current path. In addition, the boundary of the current magnitude can be determined according to the use scenario of the chip.

In an embodiment, the first preset threshold may be 0.15I (I is total current), that is, the through hole VIA with a current of more than 15% of the total current is the target through hole VIA, that is, the current flowing through the target through hole VIA accounts for more than 15% of the total current. Of course, 15% of the example is not understood to be a limitation to the first preset threshold of the present application, and the first preset threshold may also be a remaining value greater than 15%, such as 0.2i,0.25i, etc., and may be determined according to the usage scenario of the chip.

Step S103: and optimizing the arrangement of the through hole VIA networks in the chip layout so as to reduce the maximum current value of the through holes VIA flowing through the optimized through hole VIA networks.

When the target through hole VIA with the current value larger than the first preset threshold exists, the position arrangement of the through hole VIA network in the layout is optimized, so that the maximum current value flowing through the through hole VIA in the optimized through hole VIA network is reduced, namely the maximum current value flowing through the through hole VIA in the optimized through hole VIA network is smaller than the maximum current value flowing through the through hole VIA in the through hole VIA network before optimization. Assuming that the maximum current value flowing through VIA in the optimized VIA network is a and the maximum current value flowing through VIA in the VIA network before optimization is B, a is smaller than B. Through optimizing the position arrangement of the through hole VIA networks in the layout, the maximum current value of the through holes VIA flowing through the optimized through hole VIA networks is reduced, so that the current concentrated on the target through hole VIA can be distributed to more VIAs, the phenomenon of current density concentration is improved, the current distribution is more uniform, and the problem of unbalanced distribution of the current on the through holes VIA is solved.

In one embodiment, when the arrangement of the VIA networks in the chip layout is optimized, only the arrangement of the VIA networks on the path where the target VIA is located may be optimized. In such an embodiment, the arrangement of the network of VIA holes VIA on the path where the remaining VIA holes VIA except the target VIA hole VIA are located may not be optimized. Since the network of through-holes VIA on the path where the target through-hole VIA is located shares a large amount of current, the maximum value of the current flowing through the through-holes VIA in the optimized network of through-holes VIA becomes small by optimizing the network.

In addition, in addition to searching whether a target through hole VIA with a current value larger than a first preset threshold value exists based on the analysis result, whether a target through hole VIA with a current value smaller than a second preset threshold value exists may also be searched based on the analysis result, wherein the second preset threshold value is smaller than the first preset threshold value. Accordingly, in addition to optimizing the arrangement of the network of through holes VIA on the path where the target through hole VIA having the current value greater than the first preset threshold value is located, the arrangement of the network of through holes VIA on the paths where the other through holes VIA are located may be optimized, for example, the arrangement of the network of through holes VIA on the path where the target through hole VIA having the current value less than the second preset threshold value is located may be optimized. In this embodiment, the method further comprises: and searching whether the target through holes VIA with the current value smaller than the second preset threshold exist or not based on the analysis result, and optimizing the arrangement of the through hole VIA network on the passage where the target through holes VIA with the current value smaller than the second preset threshold exist when the target through holes VIA with the current value smaller than the second preset threshold exist, for example, deleting the target through holes VIA with the current value smaller than the second preset threshold.

In an embodiment, the second preset threshold may be 0.01I (I is the total current), that is, during optimization, the through holes VIA whose current accounts for less than 1% of the total current may also be deleted. Of course, the 1% illustrated here is not to be understood as a limitation to the second preset threshold, and the second preset threshold may also be a remaining value less than 1%, such as 0.005i,0.008i, and the like, and may be determined according to a usage scenario of the chip.

Wherein, when optimizing the arrangement of the network of VIA VIAs on the path in which the target VIA VIA is located, in one embodiment, the network of VIA's in the path of the target VIA may be deleted. Through deleting the through hole VIA network on the path where the target through hole VIA is located, the current approximately and evenly flows through more through holes VIA (through holes VIA in other areas), damage to a chip caused by the fact that the current flows through too much current from the position of the target through hole VIA with smaller resistance is avoided, each VIA at the connection position can sufficiently meet overcurrent requirements, and the reliability is improved while the performance is guaranteed.

For ease of understanding, it will be illustrated below that, assuming that the conventional layout of VIAs VIA between two adjacent metal line layers (M1, M2) is shown in fig. 2, in the conventional wiring scheme, since the maximum current that can be carried by a single VIA is limited, VIA is generally distributed over the connection in order to reduce the resistance on the wiring. It has been found that a disadvantage of such a layout is that the corner regions of the two connection layers (VIA regions in the upper left corner) carry most of the ESD transient current, and the other regions in turn have a significantly reduced current. By plotting the corresponding resistor network shown in fig. 2 (as shown in fig. 3), the reason for this can be analyzed: in the case of uniform wire width, the parasitic resistance is substantially linear with the length of the wire, and the resistances of the VIA's in the same layer are equal, so the closer the route to the corner (where the turn is, such as but not limited to right angle), the shorter the length, the smaller the resistance, and the same the voltages at the access point and the output point, the smaller the resistance, the larger the current flowing, which eventually results in non-uniform current distribution of each VIA, so that the EM (electro-migration) current of the VIA's at the corner exceeds the standard. The electromigration generally refers to a phenomenon that metal ions migrate under the action of an electric field, such as the common silver ion migration occurring on the surface of an adjacent conductor and the metalized electron migration occurring inside a metal conductor. When the device is in operation, a certain current flows through the metal interconnection line, and mass transport of metal ions along the conductor occurs, which results in the formation of voids or whiskers (hillocks) in some parts of the conductor, which is an electromigration phenomenon. The interconnect may deform over time as atoms move along the interconnect towards the cathode. This results in pits appearing in the wire closer to the anode and small metal bumps beginning to grow along the surface of the wire closer to the cathode. As time passes, more metal migrates at a faster rate and the process eventually ends with a short or open circuit. Open circuit failures occur when the metal along the wire is completely depleted and voids are left in the wire. In the event of a short circuit, dendrites can grow out of the wire until they bridge the gap between the two conductors. In either case, the assembly fails to function properly and must be replaced. In a large scale integrated circuit, the probability of a short circuit fault occurring is higher than that of an open circuit fault simply because the distance between interconnects is closer.

It should be noted that the through holes VIA shown in fig. 2 and 3 are only schematic diagrams of a part of the through holes VIA connecting two adjacent metal line layers.

In the embodiment of the application, through optimizing the through hole VIA network on the channel where the target through hole with the current value larger than the first preset threshold value is located, if the through hole VIA network on the channel where the target through hole is located is deleted, the current flows through more VIA relatively averagely, and the problem of local damage is avoided. The optimized arrangement of the through holes VIA is shown in fig. 4, and more current flows through more VIAs (e.g., three through holes VIA indicated by arrows in fig. 4) relatively averagely by removing the through holes VIA with the largest current, that is, the through holes VIA in the first row, the first column, and the second row, and the first column are deleted, so that the current originally flowing through the through holes relatively averagely flows through more VIAs. The current flowing through the first row and the first column of the through holes is the largest (and therefore the path is the shortest), and the current flowing through the second row and the second column of the through holes is relatively larger than the current flowing through the VIA of the second row and the first column (the current is smaller than the current flowing through the VIA of the first row and the first column and is larger than the current flowing through the rest of the through holes). Wherein the currents flowing through the three VIAs VIA are equal. Analyzing the resistor network of the wiring arrangement shown in fig. 4, the paths taken by the currents flowing through the three VIAs VIA indicated by the arrows are substantially identical, so that it can be concluded that the resistances of each of the three paths are substantially equal, and therefore the currents flowing through the three VIAs VIA are equal.

In the embodiment of the present application, by analyzing the electrostatic discharge of the VIA shown in fig. 5, the VIA current distribution is shown in fig. 6, and it can be seen that the EM (electro-migration) of the VIA at the corner (the lower right corner in fig. 6) is the largest, for example, 35.1% (the current at the VIA at the corner is the proportion of the total current). The darker color of fig. 6 represents a large current (lower right corner in fig. 6), gradually transitioning to a light color, and finally a small current to white (upper left corner in fig. 6). It can be seen that there are severe EM problems with the VIA at the corners, which directly affect the performance of the circuit. Therefore, in the embodiment of the present application, the arrangement of the VIA networks in different chip layouts is optimized, for example, VIA at a corner is deleted, so that more VIA VIAs VIA share the current, and thus the maximum current value flowing through the VIA in the optimized VIA network is reduced. In addition, through-hole VIA through which only a small current flows may be deleted, for example, a target through-hole VIA with a current value smaller than the second preset threshold may be deleted, and in this embodiment, a schematic diagram of VIA wiring shown in fig. 2 after optimization may be shown in fig. 7. In the schematic diagram shown in fig. 7, not only the through holes VIA with the current value greater than the first preset threshold value are deleted, but also the through holes VIA with the current value less than the second preset threshold value are deleted.

The current distribution corresponding to different through hole VIA distributions is different, and the arrangement of the through hole VIA networks in the chip layout is optimized, so that the maximum current value flowing through the through holes VIA in the optimized through hole VIA networks is reduced. In the optimization, the current distribution of the current on the VIA may be optimized in other ways besides the above-described deletion way. For example, in addition to the above embodiment, the circuit area of the metal layer may be increased, and the metal layer circuit may be increased to accommodate more VIA VIAs VIA, so as to increase the resistance, and make more VIA VIAs VIA share the current, thereby reducing the maximum current value flowing through the optimized VIA in the VIA network.

In another embodiment, when the arrangement of the through-hole VIA networks in the chip layout is optimized, a step of determining that the current flowing through any through-hole VIA in the optimized through-hole VIA network is smaller than the first preset threshold may be further added on the basis of optimizing the arrangement of the through-hole VIA networks on the path where the target through-hole VIA is located. As can be seen from the above description, optimizing the arrangement of the network of through-hole VIAs on the path where the target through-hole VIA is located may reduce the maximum current value flowing through the through-hole VIAs in the optimized network of through-hole VIAs, and in order to make the current flowing through any through-hole VIA in the optimized network of through-hole VIAs smaller than the first preset threshold, multiple optimizations may be involved. The current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value, so that the problem of local damage caused by overlarge current is solved.

As an embodiment, it may be determined that the current flowing through any VIA in the optimized VIA network is less than the first preset threshold by: analyzing the electrostatic discharge of the chip layout with the optimized arrangement of the through hole VIA network to obtain a latest analysis result, and searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the latest analysis result; and when the target through hole VIA with the current value larger than the first preset threshold value does not exist, determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value. If the target through hole VIA with the current value larger than the first preset threshold value is still found based on the latest analysis result, the arrangement of the through hole VIA networks in the chip layout is further optimized until the current flowing through any through hole VIA in the optimized through hole VIA networks is smaller than the first preset threshold value. The second optimization may be performed in the same manner as the first optimization, for example, the arrangement of the through-hole VIA network on the path where the target through-hole VIA is located is optimized, for example, the through-hole VIA network on the path where the target through-hole VIA is located is deleted, which is not described herein again.

When the wiring is carried out in a mode of selecting superposition of multiple layers of metal wires, when different layers of metal wires are connected, the resistance consistency of parallel wires and the distribution rationality of VIA at a joint, namely, the current distribution equality are ensured. The optimization principle is similar, namely the resistances of different paths are approximately equal as much as possible, so that the current is uniformly distributed into the different paths as much as possible, the current is prevented from flowing to the metal line with the minimum resistance, and no or little ESD current flows through other metal layers.

It should be noted that, the distribution of current can be well improved by changing the distribution of the VIA holes VIA, the influence of different VIA hole VIA distribution conditions on current is large, the corresponding current distribution is also different, in the actual optimization process, as long as the effect of improving the distribution of current on the VIA can be achieved, the VIA at the corner is not necessarily deleted, according to the connection and distribution conditions of specific connecting wires, the current density is reasonably adjusted by adjusting the distribution of the VIA, so that the comprehensive performance of the circuit is improved, and therefore the above example cannot be understood as the limitation of the present application. The method for optimizing current distribution provided by the embodiment of the application has the advantages of wide applicability, strong practicability, high flexibility and the like.

The embodiment of the application also provides an integrated circuit chip, which comprises a plurality of metal wire layers and through holes VIA. Every two adjacent layers of the multilayer metal wire layers are connected through holes VIA, wherein the arrangement density of the through holes VIA at the corners of the two adjacent layers of metal wire layers is smaller than that of the through holes VIA at the rest areas of the two adjacent layers of metal wire layers. In general, the arrangement density of the VIA at the corner of two adjacent metal line layers is the same as that of the VIA at the remaining region of two adjacent metal line layers, and the VIA may be filled at the corner. As can be seen from the above description, since the current flowing through the VIA at the corner of the two adjacent metal line layers is larger than that in the remaining region (because the path length at the corner is shorter, the resistance is smaller because of the shorter path length, and the current flowing through the VIA is larger), the current flowing through the VIA is not uniform, and the current flowing through the VIA at the corner exceeds the withstand capability thereof. In the embodiment of the application, the arrangement of the through holes VIA at the corners of the two adjacent metal wire layers is optimized, and the target through holes VIA with the current value larger than the first preset threshold value are removed, so that the arrangement density of the through holes VIA at the corners of the two adjacent metal wire layers is smaller than that of the through holes VIA in the rest areas of the two adjacent metal wire layers. For example, the arrangement density of the VIA holes VIA at the corner of two adjacent metal wire layers is 90% of the arrangement density of the VIA holes VIA in the rest area. It should be noted that 90% is only an example, and is only for illustrating that the arrangement density of VIA at the corner of two adjacent metal line layers is less than that of VIA at the rest of two adjacent metal line layers, and therefore, the present application is not limited thereto.

The integrated circuit chip may be an integrated circuit chip such as a processor and a memory. The Memory may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Read Only Memory (EPROM), an electrically Erasable Read Only Memory (EEPROM), and the like. The Processor may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), etc.; but also a Digital Signal Processor (DSP) or a Microprocessor (MCU).

The embodiment of the present application further provides an apparatus 100 for optimizing current distribution, as shown in fig. 8. The apparatus 100 for optimizing current distribution includes: an acquisition module 110 and a processing module 120.

The obtaining module 110 is configured to obtain an analysis result of electrostatic discharge for characterizing the chip layout.

The processing module 120 is configured to search whether a target through hole VIA with a current value larger than a first preset threshold exists based on the analysis result; and the chip layout is also used for optimizing the arrangement of the through hole VIA network in the chip layout when the target through hole VIA with the current value larger than the first preset threshold exists, so that the maximum current value flowing through the through holes VIA in the optimized through hole VIA network is reduced.

Optionally, the processing module 120 is configured to optimize the arrangement of the network of through-hole VIA on the path where the target through-hole VIA is located.

Optionally, the processing module 120 is configured to delete a VIA network in a VIA where the target VIA is located.

Optionally, the processing module 120 is further configured to search, based on the analysis result, whether a target through hole VIA with a current value smaller than a second preset threshold exists, where the second preset threshold is smaller than the first preset threshold; and when the target through hole VIA with the current value smaller than the second preset threshold exists, deleting the target through hole VIA with the current value smaller than the second preset threshold.

Optionally, the processing module 120 is configured to optimize the arrangement of the network of through-hole VIAs VIA in the path where the target through-hole VIA is located; and determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value.

Optionally, the processing module 120 is configured to analyze the electrostatic discharge of the chip layout with the optimized arrangement of the VIA network, so as to obtain a latest analysis result; searching whether a target through hole VIA with a current value larger than the first preset threshold exists or not based on the latest analysis result; and when the target through hole VIA with the current value larger than the first preset threshold value does not exist, determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value.

The implementation principle and the resulting technical effect of the apparatus 100 for optimizing current distribution provided in the embodiment of the present application are the same as those of the foregoing method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing method embodiments for the part of the apparatus embodiments that is not mentioned.

As shown in fig. 9, fig. 9 is a block diagram illustrating a structure of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used for transceiving data. The memory 220 is used for storing a computer program, such as the software functional module shown in fig. 8, i.e. the apparatus 100 for optimizing current distribution. The apparatus 100 for optimizing current distribution includes at least one software functional module, which may be stored in the memory 220 in the form of software or firmware (firmware) or solidified in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute an executable module stored in the memory 220, for example, a software functional module or a computer program included in the apparatus 100 for optimizing current distribution. For example, the processor 240 is configured to obtain an analysis result of electrostatic discharge for characterizing the chip layout; searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result; and when the target through hole VIA with the current value larger than the first preset threshold value exists, optimizing the arrangement of the through hole VIA network in the chip layout so as to reduce the maximum current value of the through hole VIA flowing through the optimized through hole VIA network.

The Memory 220 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.

The processor 240 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.

The electronic device 200 includes, but is not limited to, a computer, a server, and the like.

The present embodiment also provides a non-volatile computer-readable storage medium (hereinafter, referred to as a storage medium), where the storage medium stores a computer program, and the computer program is executed by a computer such as the electronic device 200 described above to perform the method for optimizing current distribution described above.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of optimizing current distribution, comprising:

obtaining an analysis result for representing electrostatic discharge of the chip layout;

searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result;

when a target through hole VIA with a current value larger than the first preset threshold value exists, optimizing the arrangement of the through hole VIA network in the chip layout so as to reduce the maximum current value of the through hole VIA flowing through the optimized through hole VIA network;

wherein, optimize the arrangement of through-hole VIA network in the chip domain, include: and deleting the through hole VIA network on the path where the target through hole VIA is located, so that the current which flows through the through hole VIA network on the path where the target through hole VIA is located is shared by more through holes VIA in the chip layout.

2. The method of claim 1, further comprising:

searching whether a target through hole VIA with a current value smaller than a second preset threshold value exists or not based on the analysis result, wherein the second preset threshold value is smaller than the first preset threshold value;

and when the target through hole VIA with the current value smaller than the second preset threshold exists, deleting the target through hole VIA with the current value smaller than the second preset threshold.

3. The method according to claim 1, wherein optimizing the arrangement of VIA networks in the chip layout comprises:

optimizing the arrangement of the through hole VIA network on the path where the target through hole VIA is located;

and determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value.

4. The method of claim 3, wherein determining that the current flowing through any VIA in the optimized VIA network is less than the first preset threshold comprises:

analyzing the electrostatic discharge of the chip layout with the optimized arrangement of the through hole VIA network to obtain the latest analysis result;

searching whether a target through hole VIA with a current value larger than the first preset threshold exists or not based on the latest analysis result;

and when the target through hole VIA with the current value larger than the first preset threshold value does not exist, determining that the current flowing through any through hole VIA in the optimized through hole VIA network is smaller than the first preset threshold value.

5. An apparatus for optimizing current distribution, comprising:

the acquisition module is used for acquiring an analysis result for representing the electrostatic discharge of the chip layout;

the processing module is used for searching whether a target through hole VIA with a current value larger than a first preset threshold exists or not based on the analysis result;

the processing module is further configured to optimize the arrangement of the through hole VIA networks in the chip layout when a target through hole VIA with a current value larger than the first preset threshold exists, so that the maximum current value flowing through the through holes VIA in the optimized through hole VIA networks is reduced;

6. An integrated circuit chip, comprising:

a plurality of metal wire layers;

and through-hole VIAs, wherein every two adjacent layers in the multilayer metal wire layers are connected through the through-hole VIAs, the arrangement density of the through-hole VIAs at the corners of the two adjacent metal wire layers is smaller than that of the through-hole VIAs at the rest areas of the two adjacent metal wire layers, wherein the arrangement of the through-hole VIAs at the corners of the two adjacent metal wire layers is optimized by using the method for optimizing current distribution as claimed in any one of claims 1 to 4, and the target through-hole VIAs with the current value larger than the first preset threshold value are deleted, so that the arrangement density of the through-hole VIAs at the corners of the two adjacent metal wire layers is smaller than that of the through-hole VIAs at the rest areas of the two adjacent metal wire layers.

7. An electronic device, comprising:

the processor is connected with the memory;

the memory is used for storing programs;

the processor to invoke a program stored in the memory to perform the method of any of claims 1-4.

8. A storage medium having stored thereon a computer program which, when executed by a processor, performs the method according to any one of claims 1-4.