Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a schematic structural diagram of an organic light emitting display panel according to an embodiment of the present disclosure, and fig. 2 to 5 are schematic structural diagrams of a pixel driving circuit according to an embodiment of the present disclosure. Referring to fig. 1 to 5, the present application provides an organic light emitting display panel 100, including a plurality of pixel units P arranged in an array along a first direction x and a second direction y, the pixel units P including light emitting elements EL and pixel driving circuits 10 connected to the light emitting elements EL, the first direction x intersecting the second direction y;
the organic light emitting display panel 100 further includes a first power signal terminal PVDD, and the pixel driving circuit 10 includes: a data writing module 101, a light emission control module 102, and a driving transistor M0; wherein,
a driving transistor M0 for generating a driving current and driving the light emitting element EL to emit light;
a light emission control module 102 for controlling whether the driving current passes through the light emitting element EL;
a data writing module 101 electrically connected to the driving transistor M0 for writing a data signal into the driving transistor M0;
the pixel driving circuit 10 further includes a first pixel driving circuit 20 and a second pixel driving circuit 30, and the first pixel driving circuit 20 and the second pixel driving circuit 30 are connected to the first power signal terminal PVDD in different manners; the organic light emitting display panel 100 includes a first driving mode and a second driving mode;
in the first driving mode, the first pixel driving circuit 20 and the second pixel driving circuit 30 both receive a light emitting power supply voltage signal; in the second driving mode, when the first pixel driving circuit 20 receives the light emitting power supply voltage signal, the second pixel driving circuit 30 receives the non-light emitting power supply voltage signal; when the second pixel driving circuit 30 receives the light emitting power voltage signal, the first pixel driving circuit 20 receives the non-light emitting power voltage signal. Therefore, in the present application, in the second driving mode, one of the first pixel driving circuit and the second pixel driving circuit receives the light emitting power voltage signal to emit light, and the other of the first pixel driving circuit and the second pixel driving circuit receives the non-light emitting power voltage signal to not emit light, so that the number of sub-pixels at the light emitting time is reduced, and the power consumption of the display panel is reduced.
Further, the organic light emitting display panel 100 provided by the present application includes a plurality of gate lines GL extending along the first direction x and arranged along the second direction y and a plurality of data lines DL extending along the second direction y and arranged along the first direction x, where the gate lines GL and the data lines DL intersect to define a plurality of pixel units P, each pixel unit P may include a light emitting element EL and a pixel driving circuit 10 connected to the light emitting element EL, and the pixel driving circuit 10 includes a first pixel driving circuit 20 and a second pixel driving circuit 30, which are different from each other in a connection manner between the first pixel driving circuit 20 and the first power signal terminal PVDD and in a connection manner between the second pixel driving circuit 30 and the first power signal terminal PVDD. As shown in fig. 4 to 5, the pixel driving circuit 10 may include a data writing module 101, a light emitting control module 102, and a driving transistor M0. The driving transistor M0 is used for generating a driving current and driving the light emitting element EL to emit light, the light emitting control module 102 is used for controlling whether the driving current passes through the light emitting element EL, and the data writing module 101 is electrically connected to the driving transistor M0 and is used for writing a data signal into the driving transistor M0.
Currently, many electronic devices have idle mode, such as a watch in a wearable device, and the electronic device in the idle mode can display at a lower frequency. In an embodiment of the present application, the organic light emitting display panel 100 includes a first driving mode and a second driving mode, optionally, the display panel is driven at a first frequency in the first driving mode, and the display panel is driven at a second frequency in the second driving mode, and the first frequency is greater than the second frequency, that is, the first driving mode is a normal display mode, and the second driving mode is a low frequency display mode; in the present application, the first frequency f1 is greater than 50Hz and less than 90Hz, and the second frequency f2 is equal to or less than 50Hz, for example, f1 is equal to 60Hz, and f2 is equal to 15 Hz.
When the display panel 100 is in the first driving mode, the first pixel driving circuit 20 and the second pixel driving circuit 30 both receive the light emitting power voltage signal; when the display panel 100 is in the second driving mode, the first pixel driving circuit 20 receives the light-emitting power voltage signal and the second pixel driving circuit 30 receives the non-light-emitting power voltage signal, or the first pixel driving circuit 20 receives the non-light-emitting power voltage signal and the second pixel driving circuit 30 receives the light-emitting power voltage signal, that is, in the second driving mode, at least a part of the light-emitting elements EL are not lit, so that the power consumption of the display panel 100 in the second driving mode is effectively reduced.
It should be noted that fig. 1 to 5 only exemplarily show one arrangement of the pixel units P in the display panel 100, and the arrangement of the pixel units P may be designed by a person skilled in the art according to practical situations.
Optionally, with continued reference to fig. 2 and 4, the first power signal terminal PVDD includes a first sub power signal terminal PVDD1 and a second sub power signal terminal PVDD2, the first pixel driving circuit 20 is electrically connected to the first sub power signal terminal PVDD1, and the second pixel driving circuit 30 is electrically connected to the second sub power signal terminal PVDD 2; the organic light emitting display panel 100 further includes a second power signal terminal PVEE, and the light emitting element EL includes a first pole and a second pole, wherein the first pole is electrically connected to the second power signal terminal PVEE, and the second pole is electrically connected to the output terminal of the light emitting control module 102;
in the first driving mode, the first and second sub power signal terminals PVDD1 and PVDD2 each provide a first power signal;
in the second driving mode, the second sub power signal terminal PVDD2 provides the second power signal when the first sub power signal terminal PVDD1 provides the first power signal, and the second sub power signal terminal PVDD2 provides the first power signal when the first sub power signal terminal PVDD1 provides the second power signal; the voltage of the second power signal is smaller than the sum of the on voltage of the light emitting element EL and the voltage of the second power signal terminal PVEE.
Specifically, the first power signal terminal PVDD includes a first sub power signal terminal PVDD1 and a second sub power signal terminal PVDD 2; the connection modes of the first pixel driving circuit 20 and the second pixel driving circuit 30 and the first power signal terminal PVDD may be different: the first pixel driving circuit 20 is electrically connected to the first sub power signal terminal PVDD1, and the second pixel driving circuit 30 is electrically connected to the second sub power signal terminal PVDD 2. When the display panel 100 is in the first driving mode, the first sub power signal terminal PVDD1 and the second sub power signal terminal PVDD2 both provide the first power signal, and since the first pole of the light emitting element EL is electrically connected to the second power signal terminal PVEE and the second pole is electrically connected to the output terminal of the light emitting control module 102, the voltage value of the first power signal needs to be greater than the sum of the on voltage of the light emitting element EL and the voltage of the second power signal terminal PVEE, so that when the light emitting control module 102 controls the driving current to pass through the light emitting element EL, all the light emitting elements EL in the display panel 100 can realize display.
On the other hand, when the display panel 100 is in the second driving mode, the first sub power signal terminal PVDD1 provides the first power signal, the second sub power signal terminal PVDD2 provides the second power signal, or the first sub power signal terminal PVDD1 provides the second power signal, and the second sub power signal terminal PVDD2 provides the first power signal, the present application can ensure that the light emitting element EL in the second pixel driving circuit 30 cannot be driven to emit light by setting the voltage value of the second power signal to be smaller than the sum of the on voltage of the light emitting element EL and the voltage of the second power signal terminal PVEE, thereby effectively reducing the power consumption of the display panel 100, reducing the light emitting time of the light emitting element EL, and being beneficial to prolonging the service life of the display panel 100.
Alternatively, with continued reference to fig. 1 and fig. 2, the organic light emitting display panel 100 includes a first pixel column group P1 and a second pixel column group P2, the first pixel column group P1 and the second pixel column group P2 are alternately arranged along the first direction x, the light emitting element EL in the first pixel column group P1 is electrically connected to the first pixel driving circuit 20, and the light emitting element EL in the second pixel column group P2 is electrically connected to the second pixel driving circuit 30; or,
the light emitting element EL in the first pixel column group P1 is electrically connected to the second pixel driving circuit 30, and the light emitting element EL in the second pixel column group P2 is electrically connected to the second pixel driving circuit 20.
In this embodiment, the organic light emitting display panel 100 includes a first pixel column group P1 and a second pixel column group P2, each of the first pixel column group P1 and the second pixel column group P2 includes at least one pixel column, and each pixel column includes a plurality of pixel units P arranged along the second direction y. Since the light-emitting elements EL in the first pixel column group P1 are connected to the first pixel driving circuit 20 and the light-emitting elements EL in the second pixel column group P2 are connected to the second pixel driving circuit, the light-emitting elements EL in the first pixel column group P1 or the light-emitting elements EL in the second pixel column group P2 are not turned on when the display panel 100 is in the second driving mode. According to the display panel, the first pixel column group P1 and the second pixel column group P2 are arranged alternately in the first direction x, so that the power consumption of the display panel can be reduced, and the display effect of the display panel during low-frequency display is considered.
Of course, in addition to the design manner in which the light emitting element EL in the first pixel column group P1 is electrically connected to the first pixel driving circuit 20 and the light emitting element EL in the second pixel column group P2 is electrically connected to the second pixel driving circuit 30, in some other embodiments of the present application, a design manner in which the light emitting element EL in the first pixel column group P1 is electrically connected to the second pixel driving circuit 30 and the light emitting element EL in the second pixel column group P2 is electrically connected to the first pixel driving circuit 20 may also be adopted, and details thereof are not described here again.
With continued reference to fig. 1 and 2, each of the first pixel column group P1/the second pixel column group P2 in the present embodiment includes three columns of pixel cells P.
Specifically, each first pixel column group P1 may include three columns of pixel cells P, and each second pixel column group P2 may also include three columns of pixel cells P. Still taking the case where the light emitting elements EL in the first pixel column group P1 are connected to the first pixel driving circuit 20 and the light emitting elements EL in the second pixel column group P2 are connected to the second pixel driving unit as an example, since each row in each first pixel column group P1 includes a red light emitting element EL, a green light emitting element EL, and a blue light emitting element EL in the second direction y, when the display panel 100 is in the second driving mode, the first pixel driving circuit 20 receives a light emission power supply voltage signal, thereby realizing normal display. It should be understood that this design enables only half of the light emitting elements EL to be lit during the low frequency display, that is, the driving chip only needs to output data signals to half of the pixel driving circuits 10 when displaying each frame, thereby reducing the output power consumption of the driving chip and further reducing the power consumption of the display panel 100 during the low frequency display. In addition, the first pixel column group P1 and the second pixel column group P2 are alternately arranged, so that the display effect in the low-frequency display process is ensured.
Fig. 6 is a schematic partial structure diagram of an organic light emitting display panel provided in the embodiment of fig. 1. As shown in fig. 6, in some other embodiments of the present application, each of the first and second pixel column groups P1 and P2 includes only one column of pixel cells P. It should be noted that, those skilled in the art can design the first pixel column group P1 and the second pixel column group P2 according to practical requirements without limitation in the spirit of the embodiments of the present invention.
Fig. 7 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure. Further, referring to fig. 4, fig. 5 and fig. 7, the pixel driving circuit 10 includes a data writing module 101, a light emitting control module 102 and a driving transistor M0, and further includes a first reset module 103, a threshold compensation module 104 and a second reset module 105, wherein the light emitting control module 102 includes a first light emitting control module 102a and a second light emitting control module 102 b. Specifically, the first light emitting control module 102a includes a first transistor M1, a control terminal of the first transistor M1 is electrically connected to the light emitting signal input terminal Emit, a first terminal is electrically connected to the first power signal terminal PVDD, and a second terminal is electrically connected to the input terminal of the driving transistor M0; the DATA writing module 101 includes a second transistor M2, a control terminal of the second transistor M2 is electrically connected to the second control signal output terminal S2, a first terminal is electrically connected to the DATA signal input terminal DATA, and a second terminal is electrically connected to the input terminal of the driving transistor M0; the second light emission control module 102b includes a third transistor M3, a control terminal of the third transistor M3 is electrically connected to the light emission signal input terminal Emit, a first terminal is electrically connected to the output terminal of the driving transistor M0, and a second terminal is electrically connected to the first pole of the light emitting element EL; the first reset module 103 includes a fourth transistor M4, a control terminal of the fourth transistor M4 is electrically connected to the first control signal output terminal S1, a first terminal is electrically connected to the reference voltage signal input terminal Vref, and a second terminal is electrically connected to the control terminal of the driving transistor M0; the threshold compensation module 104 includes a fifth transistor M5, a control terminal of the fifth transistor M5 is electrically connected to the second control signal output terminal S2, a first terminal is electrically connected to the output terminal of the driving transistor M0, and a second terminal is electrically connected to the control terminal of the driving transistor M0; the second reset module 105 includes a sixth transistor M6, wherein a control terminal of the sixth transistor M6 is electrically connected to the second control signal output terminal S2, a first terminal thereof is electrically connected to the reference voltage signal input terminal Vref, and a second terminal thereof is electrically connected to the output terminal of the light emitting control module 102.
Fig. 8 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure. Alternatively, in this embodiment, the structure of the first pixel driving circuit 20 is as shown in fig. 6, and the structure of the second pixel driving circuit 30 is as shown in fig. 8. Referring to fig. 8, the second pixel driving circuit 30 further includes a switch transistor M7, a control terminal of the switch transistor M7 is electrically connected to the switch control signal output terminal SW, a first terminal is electrically connected to the first power signal terminal PVDD, and a second terminal is electrically connected to the input terminal of the light-emitting control module 102;
in the first driving mode, the switching transistor M7 is turned on, and in the second driving mode, the switching transistor M7 is turned off.
In this embodiment, the second pixel driving circuit 30 is additionally provided with a switching transistor M7 on the basis of the first pixel driving circuit 20, wherein a control terminal of the switching transistor M7 is electrically connected to the switching control signal output terminal SW, a first terminal is electrically connected to the first power signal terminal PVDD, and a second terminal is electrically connected to the input terminal of the first light-emitting control module 102 a. In this way, when the display panel 100 is in the second drive mode, the switching transistor M7 is turned off, and the power supply signal supplied from the first power supply signal terminal PVDD connected to the second pixel drive circuit 30 is cut off, so that the drive chip does not write a data signal to the second pixel drive circuit 30 any more, and further, the light emitting element EL connected to the second pixel drive circuit 30 does not display, and the circuit configuration is simple, and the difficulty in manufacturing the display panel can be reduced while reducing the power consumption of the display panel 100.
Optionally, in a further embodiment of the present application, the first pixel driving circuit 20 and the second pixel driving circuit 30 each include a switching transistor M7, and if the display panel 100 is in the first driving mode, the switching transistor M7 in the first pixel driving circuit 20 and the switching transistor M7 in the second pixel driving circuit are both turned on; if the display panel 100 is in the second driving mode, the switching transistor M7 of the second pixel driving circuit is turned off when the switching transistor M7 of the first pixel driving circuit 20 is turned on, or the switching transistor M7 of the second pixel driving circuit 30 is turned on when the switching transistor M7 of the first pixel driving circuit 20 is turned off, the power consumption of the display panel 100 can be reduced.
Note that the transistors in the pixel driving circuit 10 are Field Effect Transistors (FETs), and the transistors may be N-type or P-type, and usually the N-type transistors are turned on under the control of a high-level signal and turned off under the control of a low-level signal; the P-type transistor is turned on under the control of a low level signal and turned off under the control of a high level signal. Of course, the present application is not limited to the use of field effect transistors, and other types of transistors may be selected in other embodiments of the present application, as long as the switching function is satisfied. In addition, for the specific implementation form of the pixel driving circuit 10, a person skilled in the art can set the implementation form according to practical situations, and the implementation form is not limited herein.
Alternatively, with continued reference to fig. 3 or fig. 5, in any two adjacent light emitting elements EL, one light emitting element EL is electrically connected to the first pixel driving circuit 20, and the other light emitting element EL is electrically connected to the second pixel driving circuit 30.
In this embodiment, any two adjacent light emitting elements EL are connected to different pixel driving circuits 10, for example, when the light emitting elements EL are arranged in an array, the light emitting elements EL at odd positions in odd rows are connected to the first pixel driving circuit 20, the light emitting elements EL at even positions are connected to the second pixel driving circuit 30, the light emitting elements EL at odd positions in even rows are connected to the second pixel driving circuit 30, and the light emitting elements EL at even positions are connected to the first pixel driving circuit 20.
Fig. 9 is a schematic structural diagram of an organic light emitting display panel provided in an embodiment of the present application, and fig. 10 is a schematic structural diagram of a first display region in the organic light emitting display panel provided in the embodiment of fig. 9. Alternatively, referring to fig. 9 and 10, the organic light emitting display panel 100 includes a display area AA and a non-display area NA at least partially surrounding the display area AA, the display area AA includes a first display area AA1, an edge of the first display area AA1 includes an arc line segment, and the light emitting elements EL in the first display area AA1 are all connected to the first pixel driving circuit 20.
The organic light emitting display panel provided by the embodiment can comprise a special-shaped display area. Specifically, as shown in fig. 9, the display panel 100 includes a display area AA and a non-display area NA at least partially surrounding the display area AA, and the display area AA may be divided into a first display area AA1 and a second display area AA 2; wherein the edge of the first display area AA1 includes an arc-shaped line segment. It is understood that when the display panel 100 is in the second driving mode, the light emitting elements EL connected to the first pixel driving circuit 20 are turned on, and the light emitting elements EL connected to the second pixel driving circuit 30 are not turned on, because the first pixel column group P1 and the second pixel column group P2 are spaced in the first direction x, the design may generate a significant edge jaggy phenomenon at the position of the irregular edge of the display area AA. In order to solve the above problem, the present application provides that all the light emitting elements EL in the first display area AA1 are connected to the first pixel driving circuit 20, the light emitting elements EL in the second display area AA2 include the first pixel column group P1 and the second pixel column group P2, and the light emitting elements EL in the first pixel column group P1 are connected to the first pixel driving circuit 20, and the light emitting elements EL in the second pixel column group P2 are connected to the second pixel driving circuit 30, so that in the low frequency display state, all the light emitting elements EL in the first display area AA1 are lit, and half of the light emitting elements EL in the second display area AA2 are lit, which not only reduces the power consumption of the display panel 100, but also effectively improves the jaggy feeling of the display screen at the edge, and improves the display effect of the display panel 100 in the second driving mode.
With continued reference to fig. 1-5, the present application further provides a driving method of an organic light emitting display panel, which is applied to the organic light emitting display panel 100;
in the first driving mode, the first pixel driving circuit 20 and the second pixel driving circuit 30 both receive a light emitting power supply voltage signal;
in the second driving mode, when the first pixel driving circuit 20 receives the light emitting power supply voltage signal, the second pixel driving circuit 30 receives the non-light emitting power supply voltage signal; when the second pixel driving circuit 30 receives the light emitting power voltage signal, the first pixel driving circuit 20 receives the non-light emitting power voltage signal.
Specifically, the organic light emitting display panel 100 includes a first driving mode and a second driving mode, wherein the display panel is driven at a first frequency in the first driving mode, and the display panel is driven at a second frequency in the second driving mode, and the first frequency is greater than the second frequency, i.e., the first driving mode is a normal display mode, and the second driving mode is a low frequency display mode. For example, the display panel 100 may adopt a first driving mode when displaying a dynamic picture, and the display panel 100 may adopt a second driving mode when displaying a static picture. Further, in the present application, the first frequency f1 is greater than 50Hz and less than 90Hz, and the second frequency f2 is equal to or less than 50 Hz.
In this embodiment, the pixel unit P includes a light emitting element EL and a pixel driving circuit 10 connected thereto, and the pixel driving circuit 10 includes a data writing module 101, a light emitting control module 102, and a driving transistor M0; the driving transistor M0 is used for generating a driving current and driving the light emitting element EL to emit light, the light emitting control module 102 is used for controlling whether the driving current passes through the light emitting element EL, and the data writing module 101 is electrically connected to the driving transistor M0 and is used for writing a data signal into the driving transistor M0. Since, in the above-described driving method, when the display panel is in the second driving mode, the first pixel driving circuit 20 receives the light-emitting power supply voltage signal and the second pixel driving circuit 30 receives the non-light-emitting power supply voltage signal, or the second pixel driving circuit 30 receives the light-emitting power supply voltage signal and the first pixel driving circuit 20 receives the non-light-emitting power supply voltage signal, that is, in the second driving mode, at least a part of the light-emitting elements EL in the display panel 100 are not lit, the power consumption of the display panel 100 is reduced.
Fig. 11 is a schematic partial structure view of an organic light emitting display panel according to an embodiment of the present disclosure. Optionally, as shown in fig. 11, the organic light emitting display panel 100 further includes a driving chip 40, the DATA writing module 101 includes a DATA signal terminal DATA, and the driving chip 40 is electrically connected to the DATA signal terminal DATA;
in the second driving mode, the driving chip 40 does not output the data signal to the second pixel driving circuit 30.
Specifically, the organic light emitting display panel 100 further includes a driving chip 40, wherein the driving chip 40 is electrically connected to a DATA signal terminal DATA, and the DATA signal terminal DATA receives a DATA signal of the driving chip 40 and writes the DATA signal into the pixel unit P by the DATA writing module 101 in a DATA writing stage. In this embodiment, when the display panel 100 is in the second driving mode, only the light emitting element EL connected to the first pixel driving circuit 20 needs to be turned on, so the driving chip 40 does not need to output the DATA signal to the DATA signal terminal DATA in the second pixel driving circuit 30, and thus the driving chip 40 only outputs the DATA signal to half of the pixel driving circuits 10 when displaying each frame, thereby effectively reducing the output power consumption of the driving chip 40; in addition, when the driving chip 40 does not output the data signal to the second pixel driving circuit 30, charging and discharging of the parasitic capacitance on the data line is also avoided, and the power consumption of the driving chip and the display panel is further reduced.
Fig. 12 is a schematic diagram illustrating a connection of a demultiplexer in the organic light emitting display panel according to the embodiment of fig. 11. Alternatively, as shown in fig. 12, the organic light emitting display panel 100 further includes a plurality of DATA signal terminal groups DATA1 and a demultiplexer 50, the demultiplexer 50 being located between the driving chip 40 and each of the DATA signal terminal groups DATA 1; the DATA signal terminal set DATA1 includes a plurality of DATA signal terminals DATA, and the demultiplexer includes a strobe signal line L1, 1 st to n-th switching tubes (M8 to M14), and 1 st to n-th clock signal lines (CKH1 to CKH 6); the first end of the ith switch tube is electrically connected with a DATA signal end DATA, the second end of the ith switch tube is electrically connected with a gating signal line L1, the control end of the ith switch tube is electrically connected with the ith clock signal line, and i is more than or equal to 1 and less than or equal to n;
in the second driving mode, the clock signal line CKH electrically connected to the DATA signal terminal DATA in the second pixel driving circuit 30 outputs a dc off signal.
Specifically, the organic light emitting display panel 100 is further provided with a demultiplexer 50, the demultiplexer 50 is located between the driving chip 40 and the DATA signal terminal group DATA1, and the structure of the display panel can be as shown in fig. 11. In the following, each DATA signal terminal group DATA1 including 6 DATA signal terminals DATA will be described as an example. As shown in fig. 12, the demultiplexer 50 includes a gate signal line L1, switch tubes M8 to M13, and clock signal lines CKH1 to CKH6, wherein first ends of the switch tubes M8 to M13 are electrically connected to a DATA signal end DATA, second ends of the switch tubes M8 to M13 are connected to a gate signal line L1, and control ends of the switch tubes M8 to M13 are electrically connected to clock signal lines CKH1 to CKH6, respectively, when the pixel driving circuit 10 is configured as shown in fig. 2, the first pixel column group P1 includes three columns of pixel units P, the DATA signal lines DL corresponding to the three columns of pixel units P are connected to the clock signal lines CKH1, CKH2, and CKH3, respectively, the second pixel group P2 also includes three columns of pixel units P, and the DATA signal lines DL corresponding to the three columns of pixel units P are connected to the clock signal lines CKH4, CKH5, and CKH6, respectively. In the second driving mode, the clock signal lines CKH 1-CKH 3 are not changed, and CKH 4-CKH 6 provide dc cut signals, so that the driving chip 40 cannot output data signals to the second pixel driving circuit 30 through the demultiplexer 50, and the light emitting element EL electrically connected to the second pixel driving circuit 30 cannot be turned on, thereby reducing the power consumption of the display panel 100.
In some other embodiments of the present application, the clock signal line electrically connected to the demultiplexer may not output the clock signal, and further reduce the output power consumption of the driver chip 40.
Optionally, with continued reference to fig. 2 and 4, the first power signal terminal PVDD includes a first sub power signal terminal PVDD1 and a second sub power signal terminal PVDD2, the first pixel driving circuit 20 is electrically connected to the first sub power signal terminal PVDD1, and the second pixel driving circuit 30 is electrically connected to the second sub power signal terminal PVDD 2; the organic light emitting display panel 100 further includes a second power signal terminal PVEE, and the light emitting element EL includes a first pole and a second pole, wherein the first pole is electrically connected to the second power signal terminal PVEE, and the second pole is electrically connected to the output terminal of the light emitting control module 102;
in the first driving mode, the first and second sub power signal terminals PVDD1 and PVDD2 each provide a first power signal;
in the second driving mode, the second sub power signal terminal PVDD2 provides the second power signal when the first sub power signal terminal PVDD1 provides the first power signal, and the second sub power signal terminal PVDD2 provides the first power signal when the first sub power signal terminal PVDD1 provides the second power signal; the voltage of the second power signal is equal to or less than the sum of the on voltage of the light emitting element EL and the voltage of the second power signal terminal PVEE.
Specifically, the first power signal terminal PVDD includes a first sub power signal terminal PVDD1 and a second sub power signal terminal PVDD2, when the display panel 100 is in the first driving mode, the first sub power signal terminal PVDD1 and the second sub power signal terminal PVDD2 both provide the first power signal, and since the first electrode of the light emitting element EL is electrically connected to the second power signal terminal PVEE and the second electrode is electrically connected to the output terminal of the light emitting control module 102, the voltage of the first power voltage needs to be greater than the sum of the on voltage of the light emitting element EL and the voltage of the second power signal terminal PVEE, so that when the light emitting control module 102 controls the driving current to pass through the light emitting element EL, all the light emitting elements EL in the display panel 100 can implement display.
On the other hand, when the display panel 100 is in the second driving mode, the first sub power signal terminal PVDD1 provides the first power signal, and the second sub power signal terminal PVDD2 provides the second power signal, in this application, by setting the voltage value of the second power signal to be smaller than the sum of the on-voltage of the light emitting element EL and the voltage value of the second power signal terminal PVEE, it can be ensured that the light emitting element EL in the second pixel driving circuit 30 cannot be driven to emit light, at this time, since the driving chip 40 does not need to write data signals to all the pixel driving circuits 10 in the display panel 100, the power consumption of the display panel 100 in the low frequency display mode is effectively reduced, and the service life of the display panel 100 is prolonged.
Optionally, the voltage value of the first power signal is 4.6V, and the voltage value of the second power signal is 0V.
Based on the same inventive concept, the application also provides an organic light emitting display device comprising the organic light emitting display panel. Fig. 13 is a schematic structural diagram of an organic light emitting display device according to an embodiment of the present disclosure. As shown in fig. 13, the organic light emitting display device 200 provided in this embodiment includes the organic light emitting display panel 100 provided in the above embodiment. The display device 200 in the embodiment of fig. 13 is described by taking a mobile phone as an example, but it should be understood that the display device 200 provided in the embodiment of the present invention may be other organic light emitting display devices 200 having a display function, such as a smart watch, a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The organic light emitting display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 100 in the foregoing embodiments, which is not repeated herein.
As can be seen from the foregoing embodiments, the organic light emitting display panel, the driving method thereof, and the organic light emitting display device provided by the present invention at least achieve the following beneficial effects:
the organic light-emitting display panel comprises a plurality of pixel units which are arranged in an array mode, wherein each pixel unit comprises a light-emitting element and a pixel driving circuit connected with the light-emitting element, and the pixel driving circuit comprises a data writing module, a light-emitting control module and a driving transistor; when the display panel is in the second driving mode, one of the first pixel driving circuit and the second pixel driving circuit receives the light-emitting power supply voltage signal, and the other one receives the non-light-emitting power supply voltage signal, namely, only part of light-emitting elements in the display panel are lightened, so that the power consumption of the display panel and the display device is effectively reduced.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.