CN112599010A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN112599010A CN112599010A CN202011490056.1A CN202011490056A CN112599010A CN 112599010 A CN112599010 A CN 112599010A CN 202011490056 A CN202011490056 A CN 202011490056A CN 112599010 A CN112599010 A CN 112599010A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel includes: a substrate; the array circuit layer comprises an active layer and a plurality of metal layers; the first metal layer comprises a grid electrode of the driving transistor and a first polar plate of the storage capacitor, the second metal layer comprises a second polar plate of the storage capacitor, the third metal layer comprises a first metal wire, and the second polar plate is connected with a power supply voltage through the first metal wire; the first polar plate is also connected with an active layer, the multilayer metal layer also comprises a second metal wire, the second metal wire is connected with the first metal wire, the vertical projection of the second metal wire on the substrate is overlapped with the vertical projection of the active layer connected with the first polar plate on the substrate, and the vertical projection of the second metal wire on the substrate is separated from the vertical projections of the first polar plate and the second polar plate on the substrate. The technical scheme of the invention can increase the total storage capacitance of the pixel circuit, improve the flicker phenomenon of a display picture and optimize the display effect.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, people have higher and higher requirements for the performance of display devices. At present, the pixel circuit in the display panel has a common leakage problem, which causes the display brightness to change. Particularly, in the case of low-frequency driving, the problem of display brightness change caused by electric leakage also causes the flicker phenomenon of the display picture to be more easily recognized by human eyes, and the display effect of the display device is influenced.
Disclosure of Invention
Embodiments of the present invention provide a display panel and a display device, so as to increase a total storage capacitance in a pixel circuit, improve a flicker phenomenon of a display image, and optimize a display effect.
In a first aspect, an embodiment of the present invention provides a display panel, including:
a substrate;
the array circuit layer comprises an active layer and a plurality of metal layers which are stacked on one side of the substrate, a plurality of pixel circuits are formed in the array circuit layer, and each pixel circuit comprises a driving transistor and a storage capacitor electrically connected with the grid electrode of the driving transistor;
the multilayer metal layer comprises a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode; the first metal layer comprises a grid electrode of the driving transistor and a first plate electrode of the storage capacitor electrically connected with the grid electrode of the driving transistor, the second metal layer comprises a second plate electrode of the storage capacitor, the third metal layer comprises a first metal wire, and the second plate electrode is connected with a power supply voltage through the first metal wire; the first polar plate is further connected with the active layer, the multilayer metal layer further comprises a second metal wire, the second metal wire is connected with the first metal wire, the vertical projection of the second metal wire on the substrate is overlapped with the vertical projection of the active layer connected with the first polar plate on the substrate, and the vertical projection of the second metal wire on the substrate is separated from the vertical projections of the first polar plate and the second polar plate on the substrate.
Further, a dielectric constant between the second metal line and the active layer is greater than a dielectric constant between the first metal line and the active layer.
Further, the active layer overlapping the second metal line includes a body portion extending in a first direction, a dimension of the body portion in the second direction is larger than a dimension of the other active layers extending in the first direction, wherein the first direction is perpendicular to the second direction, and the first direction is parallel to an extending direction of the first metal line;
preferably, the active layer overlapping the second metal line further includes a branch portion extending in the second direction, the branch portion being contiguous with the body portion;
preferably, the size of the branch portion in the first direction is larger than the size of the other active layers extending in the second direction in the first direction, and the size of the branch portion in the second direction is larger than the size of the other active layers extending in the first direction in the second direction.
Furthermore, the second metal line is located in the second metal layer, and the first metal line and the second metal line are electrically connected through a via hole.
Further, the first metal line extends along a first direction, the multilayer metal layer further includes a third metal line and a fourth metal line extending along a second direction, the third metal line is connected to a first scanning signal, the fourth metal line is connected to a second scanning signal, and the fourth metal line is located on one side of the third metal line in the first direction, where the first direction is perpendicular to the second direction;
the vertical projections of the first polar plate and the second polar plate on the substrate are positioned on one side of the fourth metal wire far away from the third metal wire, and the vertical projection of the second metal wire on the substrate is positioned between the vertical projections of the third metal wire and the fourth metal wire on the substrate.
Furthermore, the first metal lines extend along a first direction, the first metal lines include first routing portions and second routing portions which are alternately arranged, two adjacent first routing portions in each first metal line are switched over through the second routing portion between the two first routing portions, the first routing portions are located on the third metal layer, and the second routing portions are located on other metal layers in the multilayer metal layer;
the first routing part is electrically connected with the second metal wire through a via hole.
Furthermore, the second routing portion is located on the second metal layer, and the first routing portion is electrically connected with the second routing portion through a via hole;
preferably, the second pole plate serves as the second routing portion.
Further, the third metal layer further comprises a third polar plate, the third polar plate is electrically connected with the first polar plate through a via hole, and vertical projections of the third polar plate and the second polar plate on the substrate are overlapped;
preferably, the first plate is multiplexed as a gate of the driving transistor.
Furthermore, a fifth metal wire is further included in the third metal layer, one end of the fifth metal wire is electrically connected to the active layer connected to the first electrode plate, and the other end of the fifth metal wire is electrically connected to the third electrode plate;
preferably, the active layer is a polysilicon layer.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel according to the first aspect.
The display panel and the display device provided by the embodiment of the invention are provided with a plurality of metal layers, wherein the metal layers comprise a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode, the first metal layer comprises a grid electrode of a driving transistor and a first polar plate of a storage capacitor, the second metal layer comprises a second polar plate of the storage capacitor, the third metal layer comprises a first metal wire, and the second polar plate is connected with power supply voltage through the first metal wire; the first polar plate is further connected with an active layer, the multilayer metal layer further comprises a second metal wire, the second metal wire is connected with the first metal wire, the vertical projection of the second metal wire on the substrate is overlapped with the vertical projection of the active layer on the substrate, and the vertical projection of the second metal wire on the substrate is separated from the vertical projections of the first polar plate and the second polar plate on the substrate. According to the technical scheme of the embodiment of the invention, the capacitor is formed by overlapping the second metal wire and the active layer, the second metal wire is electrically connected with the second plate of the storage capacitor through the first metal wire, and the active layer is electrically connected with the first plate of the storage capacitor, so that the capacitor formed by overlapping the second metal wire and the active layer can be used as an additional capacitor to form a parallel structure with the storage capacitor, the total capacitor obtained by connecting the additional capacitor and the storage capacitor in parallel can be used as the total storage capacitor in the pixel circuit to store the gate potential of the driving transistor, namely the capacitance value of the total storage capacitor in the pixel circuit is increased, and the gate potential of the driving transistor can be better maintained. And the overlapping area of the second metal wire and the active layer can be increased, so that the pixel circuit has larger total storage capacitance, the stability of the grid potential of the driving transistor is promoted by increasing the total storage capacitance, the phenomenon of display image flicker in the prior art is improved, and the display effect is optimized.
Drawings
Fig. 1 is a top view of a display panel according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a display panel according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of another display panel provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 5 is an enlarged view of a portion of FIG. 1;
FIG. 6 is a top view of another display panel provided in accordance with an embodiment of the present invention;
fig. 7 is a cross-sectional view of another display panel provided in an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the conventional display device has the problems of display brightness attenuation and display image flicker caused by the leakage of the pixel circuit, which affect the display effect of the display device. The inventors found that the above problems occur due to the following reasons: the pixel circuit in the display device includes a plurality of thin film transistors, each of which includes a driving transistor and a switching transistor, and due to various reasons such as the characteristics of the thin film transistors, the thin film transistors cannot be completely turned off, so that a leakage path is formed between the gate of the driving transistor and the switching transistor connected thereto, thereby increasing the gate voltage of the driving transistor and reducing the display brightness of a frame of display screen. Particularly, under the condition of low-frequency driving, the grid voltage of the driving transistor is refreshed more slowly, so that the time of display brightness decay is longer, the display brightness decay amplitude in one frame is larger, human eyes can more easily recognize the flicker phenomenon of a display picture, and the display effect of the display device is influenced.
In view of the foregoing problems, embodiments of the present invention provide a display panel. Fig. 1 is a top view of a display panel according to an embodiment of the present invention, wherein fig. 1 schematically shows only a partial structure of an active layer and a plurality of metal layers; fig. 2 is a cross-sectional view of a display panel according to an embodiment of the present invention, which may be specifically a cross-sectional view of the display panel shown in fig. 1 cut along a cross-sectional line aa'; fig. 3 is a cross-sectional view of another display panel provided in an embodiment of the present invention, which may be specifically a cross-sectional view of the display panel shown in fig. 1 taken along a cross-sectional line bb'; fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. With reference to fig. 1 to 4, a display panel according to an embodiment of the present invention includes a substrate 10 and an array circuit layer, the array circuit layer includes an active layer 20 and a plurality of metal layers stacked on one side of the substrate 10, a plurality of pixel circuits 100 are formed in the array circuit layer, and each pixel circuit 100 includes a driving transistor DT and a storage capacitor Cst electrically connected to a gate electrode G of the driving transistor DT; the multi-layer metal layer comprises a first metal layer M1, a second metal layer M2 and a third metal layer M3 which are arranged in a stacked mode; the first metal layer M1 includes a gate electrode G of the driving transistor DT and a first plate C1 of the storage capacitor Cst electrically connected to the gate electrode G of the driving transistor DT, the second metal layer M2 includes a second plate C2 of the storage capacitor Cst, the third metal layer M3 includes a first metal line 110, and the second plate C2 is connected to a power supply voltage through the first metal line 110; the first plate C1 is further connected with the active layer 20, the multi-layered metal layer further includes a second metal line 120, the second metal line 120 is connected with the first metal line 110, a vertical projection of the second metal line 120 on the substrate 10 overlaps a vertical projection of the active layer 20 connected with the first plate C1 on the substrate 10, and a vertical projection of the second metal line 120 on the substrate 10 is separated from vertical projections of the first plate C1 and the second plate C2 on the substrate 10.
The substrate 10 may provide buffering, protection, or support for the display panel. The substrate 10 may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of these materials. The substrate 10 may be a hard substrate formed of glass or the like. The active layer 20 may include a source region doped with n-type or p-type impurities, a drain region, and a channel region for connecting the source region and the drain region. The active layer 20 is formed of a semiconductor material, and for example, the active layer 20 may be formed of a material such as polysilicon (Psi), amorphous Silicon (α -Si), an oxide semiconductor, or an organic semiconductor. This embodiment and the following embodiments are described by taking an example in which the active layer 20 is formed of polysilicon Psi.
The array circuit layer is formed with a plurality of pixel circuits, which may be formed by thin film transistors and storage capacitors, electrically connected to the light emitting devices. The thin film transistor includes a driving transistor for generating a driving current to drive the light emitting device to emit light and a switching transistor for switching. The Light Emitting devices may be Organic Light-Emitting diodes (OLEDs), each of which includes an anode, a Light-Emitting layer, and a cathode, and each of the Light Emitting devices is electrically connected to the pixel circuit such that the pixel circuit provides a driving current to the Light Emitting device to drive the Light Emitting device to emit Light.
In the present embodiment and the following embodiments, the pixel circuit 100 in the display panel is a pixel circuit composed of seven thin film transistors and one storage capacitor, which is described with reference to fig. 1 to 4. Fig. 4 schematically illustrates only an example in which each transistor is a P-channel transistor, and in actual use, each transistor may be a P-channel transistor or an N-channel transistor. Exemplarily, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst. In the initialization stage, the third transistor T3 is turned on under the control of the first scan signal S1, and the initialization signal Vref on the initialization signal line 160 is written into the storage capacitor Cst and the gate G of the driving transistor DT, so that the storage capacitor and the gate potential of the driving transistor are initialized; the fourth transistor T4 is turned on under the control of the third scan signal S3, and writes the initialization signal Vref to the anode of the light emitting device D1, thereby performing initialization of the anode potential of the light emitting device. In the data writing phase, the first transistor T1 and the second transistor T2 are turned on under the control of the second scan signal S2, the first transistor T1 writes the data voltage signal Vdata on the data line 170 into the storage capacitor Cst through the driving transistor DT and the second transistor T2, and the second transistor T2 compensates for the threshold voltage of the driving transistor DT. In the light emitting period, the fifth transistor T and the sixth transistor T6 are turned on under the control of the light emission control signal EM on the light emission control signal line 180, the first power voltage VDD is written to the first electrode of the driving transistor DT, the second power voltage VSS is written to the cathode of the light emitting device D1, the driving transistor DT generates a driving current, and the light emitting device D1 is driven to emit light.
Referring to fig. 1 to 4, for example, among the plurality of metal layers, a first metal layer M1, a second metal layer M2, and a third metal layer M3 are sequentially stacked and formed on a side of the active layer 20 away from the substrate 10. The first and second plates C1 and C2 constitute two plates of the storage capacitor Cst. The first metal line 110 in the third metal layer M3 may be a power line, for example, the first metal line 110 is connected to the first power voltage VDD and transmits the first power voltage VDD to the pixel circuit 100. The second plate C2 is connected to a power voltage through the first metal line 110, and can be implemented by electrically connecting the second plate C2 to the first metal line 110. The third metal layer M3 generally includes a plurality of first metal lines 110 extending along the first direction, and a plurality of data lines 170 extending along the first direction, wherein the data lines 170 are used for transmitting data voltage signals Vdata into the pixel circuit 100, so that the third metal layer M3 has a limited wiring space, and the second metal lines 120 may be disposed in other metal layers except the third metal layer M3 to save the wiring space of the third metal layer M3.
The vertical projection of the second metal line 120 on the substrate 10 overlaps the vertical projection of the active layer 20 on the substrate 10, which means that the second metal line 120 and the active layer 20 are located on different layers in the display panel, but there is an overlapping area in a direction perpendicular to the substrate 10. The second metal line 120 is disposed to overlap the active layer 20 such that a capacitance is formed between the second metal line 120 and the overlapped active layer 20. The second metal wire 120 is further electrically connected to the first metal wire 110, the first metal wire 110 is further electrically connected to the second plate C2, and the active layer 20 is further electrically connected to the first plate C1, so that a capacitor formed by overlapping the second metal wire 120 and the active layer 20 can be used as an additional capacitor to form a parallel structure with the storage capacitor Cst, for example, as shown in fig. 4, the second metal wire 120 and the active layer 20 are overlapped to form an additional capacitor C10, and a total capacitor C20 obtained by connecting the additional capacitor C10 in parallel with the storage capacitor Cst can be used as a total storage capacitor in the pixel circuit to store the gate potential of the driving transistor, which is equivalent to increase the capacitance value of the total storage capacitor in the pixel circuit, so that the gate potential of the driving transistor can be better maintained.
The vertical projection of the second metal line 120 on the substrate 10 is separated from the vertical projections of the first plate C1 and the second plate C2 on the substrate 10, which means that the second metal line 120 is located in different regions of the display panel from the first plate C1 and the second plate C2, for example, as shown in the top view of the display panel in fig. 1, the first plate C1 and the second plate C2 are located in the same region of the display panel, the second metal line 120 is located in another region of the display panel, and the second metal line 120 is located separately from the first plate C1 and the second plate C2. The vertical projection of the second metal line 120 on the substrate 10 overlaps the vertical projection of the active layer 20 connected to the first plate C1 on the substrate 10, and the second metal line 120 is separately disposed from the first plate C1 and the second plate C2, respectively, so that the second metal line 120 and the active layer 20 have a larger overlapping space in the display panel, which helps to form an additional capacitor with a larger capacitance value by increasing the area of the active layer 20 in the region where the second metal line 120 overlaps the active layer 20, thereby further increasing the capacitance value of the total storage capacitor of the pixel circuit.
The formula for the change in the gate voltage of the driving transistor DT caused by the leakage is generally expressed as:
wherein Δ U is a gate voltage variation, I is a gate leakage current, Δ t is a leakage time, and C is a capacitance value of the storage capacitor Cst. According to the technical scheme of the embodiment of the invention, the capacitance value of the total storage capacitor of the pixel circuit can be increased, and the capacitance value of the total storage capacitor can be increased to reduce the grid voltage variation according to the grid voltage variation formula, so that the grid voltage of the driving transistor DT is kept stable, the driving transistor DT can generate stable driving current to drive the light-emitting device to emit light, the phenomenon of display image flicker in the prior art is favorably improved, and the display effect is optimized. In addition, compared with the scheme of increasing the storage capacitance by arranging the multilayer capacitance in the prior art, the scheme does not need to additionally increase too much mask process or ion implantation process, is favorable for simplifying the process of the display panel and savesAbout the production cost.
According to the technical scheme of the embodiment of the invention, the multiple metal layers comprise a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode, the first metal layer comprises a grid electrode of a driving transistor and a first polar plate of a storage capacitor, the second metal layer comprises a second polar plate of the storage capacitor, the third metal layer comprises a first metal wire, and the second polar plate is connected with power supply voltage through the first metal wire; the first polar plate is further connected with an active layer, the multilayer metal layer further comprises a second metal wire, the second metal wire is connected with the first metal wire, the vertical projection of the second metal wire on the substrate is overlapped with the vertical projection of the active layer on the substrate, and the vertical projection of the second metal wire on the substrate is separated from the vertical projections of the first polar plate and the second polar plate on the substrate. According to the technical scheme of the embodiment of the invention, the capacitor is formed by overlapping the second metal wire and the active layer, the second metal wire is electrically connected with the second plate of the storage capacitor through the first metal wire, and the active layer is electrically connected with the first plate of the storage capacitor, so that the capacitor formed by overlapping the second metal wire and the active layer can be used as an additional capacitor to form a parallel structure with the storage capacitor, the total capacitor obtained by connecting the additional capacitor and the storage capacitor in parallel can be used as the total storage capacitor in the pixel circuit to store the gate potential of the driving transistor, namely the capacitance value of the total storage capacitor in the pixel circuit is increased, and the gate potential of the driving transistor can be better maintained. And the overlapping area of the second metal wire and the active layer can be increased, so that the pixel circuit has larger total storage capacitance, the stability of the grid potential of the driving transistor is promoted by increasing the total storage capacitance, the phenomenon of display image flicker in the prior art is improved, and the display effect is optimized.
With reference to fig. 1 to 4, on the basis of the above embodiments, optionally, the dielectric constant between the second metal line 120 and the active layer 20 is set to be greater than the dielectric constant between the first metal line 110 and the active layer 20. The dielectric medium can generate induced charges when an electric field is applied to the medium to weaken the electric field, and the ratio of the original applied electric field to the electric field in the final medium is the dielectric constant. The capacitance can be calculated by C ═ S/d, where e is the dielectric constant of the dielectric between the capacitor plates, S is the area of the capacitor plates, and d is the distance between the capacitor plates. The dielectric constant between the second metal line 120 and the active layer 20, which is greater than the dielectric constant between the first metal line 110 and the active layer 20, may be achieved by disposing the second metal line 120 in a region between the third metal layer M3 and the active layer 20 such that the insulating dielectric layer between the second metal line 120 and the active layer 20 is less than the insulating dielectric layer between the third metal layer M3 and the active layer 20. Thus, compared with the capacitor formed by overlapping the first metal line 110 and the active layer 20, the capacitance value of the capacitor formed by overlapping the second metal line 120 and the active layer 20 is larger, which is beneficial to forming larger additional capacitor, so that the pixel circuit has larger total storage capacitor, which is beneficial to improving the stability of the gate potential of the driving transistor by increasing the total storage capacitor, improving the flicker phenomenon and optimizing the display effect.
With reference to fig. 1 to 4, optionally, the second metal line 120 is disposed on the second metal layer M2, and the first metal line 110 and the second metal line 120 are electrically connected through a via. The second metal line 120 is disposed on the second metal layer M2, such that the distance between the second metal line 120 and the active layer 20 is closer, and there are fewer insulating dielectric layers between the second metal line 120 and the active layer 20, which helps to increase the dielectric constant between the second metal line 120 and the active layer 20, according to the capacitance calculation formula C ═ S/d, when the dielectric constant ∈ is larger and the distance d between the capacitor plates is smaller, the overlap of the second metal line 120 and the active layer 20 can form a larger additional capacitance, which helps to increase the total storage capacitance of the pixel circuit.
Fig. 5 is a partial enlarged view of fig. 1, which may be specifically an enlarged view of a region a where the second metal line 120 overlaps the active layer 20 in a top view of the display panel shown in fig. 1. With reference to fig. 1, 3 and 5, optionally, the active layer 20 disposed to overlap the second metal line 120 includes a main body portion 20a extending along a first direction Y, and a dimension of the main body portion 20a in a second direction X is greater than a dimension of other active layers 20 extending along the first direction Y in the second direction X, wherein the first direction Y is perpendicular to the second direction X, and the first direction Y is parallel to the extending direction of the first metal line 110.
The other active layers 20 extending along the first direction Y refer to the active layers 20 extending along the first direction Y without overlapping the second metal line 120, for example, the active layers 20 overlapping the first metal line 110 and not overlapping the second metal line 120 over the area a. Illustratively, the width d1 of the body portion 20a in the second direction X is greater than the width d2 of the active layer 20 in the second direction X above the region a, which overlaps the first metal line 110 but does not overlap the second metal line 120. The advantage of this configuration is that the size of the active layer 20 overlapped with the second metal line 120 can be increased to increase the overlapping area of the second metal line 120 and the active layer 20, so as to increase the additional capacitance formed by the overlapping of the second metal line 120 and the active layer 20, so that the pixel circuit has a larger total storage capacitance, and further, the gate potential of the driving transistor is kept stable, so as to improve the flicker phenomenon, and optimize the display effect.
With reference to fig. 1, 3 and 5, on the basis of the above embodiment, optionally, the active layer 20 disposed to overlap the second metal line 120 further includes a branch portion 20b extending along the second direction X, and the branch portion 20b is connected to the main body portion 20 a. This has the advantage that the size of the active layer 20 overlapping the second metal line 120 can be further increased, thereby increasing the capacitance formed by the second metal line 120 overlapping the active layer 20. On the basis, the dimension d3 of the branch portion 20b in the second direction X and the dimension d4 of the branch portion 20b in the first direction Y may also be set according to requirements, for example, the dimension d4 of the branch portion 20b in the first direction Y is set to be larger than the dimensions of the other active layers 20 extending in the second direction X in the first direction Y, and the dimension d3 of the branch portion 20b in the second direction X is set to be larger than the dimension d2 of the other active layers 20 extending in the first direction Y in the second direction X, so as to increase the dimension of the active layers 20 overlapping with the second metal lines 120 and obtain larger additional capacitance.
With reference to fig. 1 to fig. 4, optionally, the first metal line 110 is arranged to extend along a first direction Y, the multi-layer metal layer further includes a third metal line 130 and a fourth metal line 140 extending along a second direction X, the third metal line 130 is connected to the first scanning signal S1, the fourth metal line 140 is connected to the second scanning signal S2, and the fourth metal line 140 is located on one side of the third metal line 130 in the first direction Y, where the first direction Y is perpendicular to the second direction X; the perpendicular projections of the first plate C1 and the second plate C2 on the substrate 10 are located at a side of the fourth metal line 140 away from the third metal line 130, and the perpendicular projection of the second metal line 120 on the substrate 10 is located between the perpendicular projections of the third metal line 130 and the fourth metal line 140 on the substrate 10.
Illustratively, the third metal line 130 is a signal line connected to the gate of the third transistor T3 in the pixel circuit, and is used to transmit the first scan signal S1 to the third transistor T3, and the first scan signal S1 is used to control the third transistor T3 to be turned on or off. The fourth metal line 140 is a signal line connecting the gate of the first transistor T1 and the gate of the second transistor T2 in the pixel circuit, for transmitting the second scan signal S2, the second scan signal S2, to the first transistor T1 and the second transistor T2, for controlling the first transistor T1 and the second transistor T2 to be turned on or off. The third metal line 130 and the fourth metal line 140 may be both disposed in the first metal layer M1, and in the first metal layer M1, the third metal line 130 and the fourth metal line 140 are separated from each other in the first direction Y. In the first direction Y, the first plate C1 and the second plate C2 are both located on a side of the fourth metal line 140 away from the third metal line 130, and the second metal line 120 is located between the third metal line 130 and the fourth metal line 140, i.e., the second metal line 120 and the first plate C1 and the second plate C2 are distributed in different regions of the display panel. This has the advantage that the second metal line 120 and the active layer 20 have a larger overlapping space in the display panel, which helps to increase the area of the active layer 20 in the area where the second metal line 120 overlaps the active layer 20, so that the area where the second metal line 120 overlaps the active layer 20 is larger to form an additional capacitor with a larger capacitance value, thereby further increasing the capacitance value of the total storage capacitor in the pixel circuit.
Fig. 6 is a top view of another display panel provided in an embodiment of the invention, where fig. 6 only schematically shows a partial structure of the second metal layer and the third metal layer; fig. 7 is a cross-sectional view of another display panel according to an embodiment of the present invention, which may be a cross-sectional view of the display panel shown in fig. 6 taken along a cross-sectional line cc'. With reference to fig. 6 and 7, optionally, the first metal lines 110 are arranged to extend along the first direction Y, the first metal lines 110 include first routing portions 110a and second routing portions 110b arranged alternately, two adjacent first routing portions 110a in each first metal line 110 are transited by the second routing portion 110b therebetween, the first routing portions 110a are located at the third metal layer M3, and the second routing portions 110b are located at other metal layers in the multilayer metal layer; the first wire portion 110a and the second metal line 120 are electrically connected through a via.
Illustratively, the first metal line 110 extends along a first direction Y, and the first metal line 110 is connected to a first power voltage VDD for transmitting the first power voltage VDD to the pixel circuit 100. Wherein the first direction Y may be a column direction in which the pixel circuits are arranged in the display panel, i.e., a direction parallel to the extending direction of the data lines 170. Two adjacent first wire routing portions 110a in each first metal wire 110 are switched through the second wire routing portion 110b between the two first wire routing portions, the first wire routing portions 110a are located in the third metal layer M3, the second wire routing portions 110b are located in other metal layers, so that the two adjacent first wire routing portions 110a in the third metal layer M3 are electrically connected through the second wire routing portions 110b in other metal layers, and the first wire routing portions 110a and the second wire routing portions 110b are alternated to form complete first metal wires 110. Since the third metal layer M3 includes both the first metal line 110 and the data line 170, the third metal layer M3 has a limited wiring space, and this embodiment has the advantage of reducing the area occupied by the first metal line 110 in the third metal layer M3, thereby increasing the wiring space in the third metal layer M3.
With reference to fig. 6 and 7, on the basis of the above-mentioned embodiment, optionally, the second wire traces 110b are disposed on the second metal layer M2, and the first wire traces 110a and the second wire traces 110b are electrically connected through vias. Illustratively, one side of the second wire trace portion 110b is electrically connected to the adjacent first wire trace portion 110a of the side through a via 111, and the other side of the second wire trace portion 110b is electrically connected to the adjacent first wire trace portion 110a of the side through a via 112. The adjacent first wire routing parts 110a in the third metal layer M3 are switched through the second wire routing parts 110b in the second metal layer M2, so that the number of wire routing in the third metal layer M3 is reduced, and the increase of the wiring space in the third metal layer M3 is facilitated.
In conjunction with fig. 6 and 7, on the basis of the above-described embodiment, optionally, the second plate C2 is provided as the second routing portion 110 b. Specifically, the first metal line 110 is a power line, and the second metal layer M2 includes a plurality of upper plates corresponding to the storage capacitors Cst of each pixel circuit, i.e. the second plate C2, and the second plate C2 is used as the second wire trace 110b, so that not only the electrical connection between the upper plates of the storage capacitors Cst and the power line is realized, but also the first wire trace 110a in the first metal line is switched in the second metal layer M2, and the second wire trace 110b does not need to be additionally disposed in the second metal layer M2, which is beneficial to simplifying the process of the display panel.
With reference to fig. 1 to 2 and fig. 6 to 7, on the basis of the above embodiment, optionally, providing the third metal layer M3 further includes a third plate C3, where the third plate C3 is electrically connected to the first plate C1 through a via, and vertical projections of the third plate C3 and the second plate C2 on the substrate 10 overlap.
Specifically, the third plate C3 is electrically connected to the first plate C1 through a via hole, such that the first plate C1 and the third plate C3 form one plate of the storage capacitor Cst, the second plate C2 forms the other plate of the storage capacitor Cst, and the third plate C3 overlaps the second plate C2, which is equivalent to increase the overlapping area between the two plates of the storage capacitor Cst, and is beneficial to increase the capacitance of the storage capacitor Cst, thereby improving the stability of the gate potential of the driving transistor, improving the flicker phenomenon, and optimizing the display effect. In addition, since the adjacent first wire traces 110a in the third metal layer M3 are connected by the second wire traces 110b disposed in other metal layers, and the wiring space in the third metal layer M3 is increased, the third plate C3 is disposed in the third metal layer M3, and the wiring space in other metal layers is not additionally occupied, and the third plate C3 and the first metal wires 110 can be manufactured in the same process flow without adding a mask process, which is beneficial to simplifying the process flow of the display panel.
On the basis of the above schemes, the first plate C1 is optionally multiplexed as the gate G of the driving transistor DT. Specifically, in the pixel circuit, since the lower plate (i.e., the first plate C1) of the storage capacitor Cst is electrically connected to the gate G of the driving transistor DT, the first plate C1 can be reused as the gate G of the driving transistor DT, the first plate C1 can be used as both the lower plate of the storage capacitor Cst and the gate G of the driving transistor DT, and the first plate C1 and the gate G of the driving transistor DT do not need to be separately formed in the first metal layer M1, which is beneficial to increasing the wiring space of the first metal layer M1, so that the area of the first plate C1 can be set larger, and the storage capacitor with a larger capacitance value can be obtained.
Referring to fig. 1 or 6, optionally, a fifth metal line 150 is further included in the third metal layer M3, one end of the fifth metal line 150 is electrically connected to the active layer 20 connected to the first plate C1, and the other end of the fifth metal line 150 is electrically connected to the third plate C3. Illustratively, a region where the active layer 20 is electrically connected to the fifth metal line 150 may be below the region a shown in fig. 1, one end of the fifth metal line 150 may be electrically connected to the active layer 20 of the region through a via, and the other end is electrically connected to the third plate C3, and since the third plate C3 is also electrically connected to the first plate C1 through a via, electrical connection between the first plate C1 and the active layer 20 is achieved. And the second metal wire 120 is also electrically connected to the second plate C2 through the first metal wire 110, so that an additional capacitor C10 formed by the second metal wire 120 and the active layer 20 is connected in parallel with the storage capacitor Cst formed by the first plate C1 and the second plate C2, so that the pixel circuit has a larger total storage capacitor, and the capacitance of the total storage capacitor is increased.
On the basis of the above solutions, the source layer 20 is optionally provided as a polysilicon layer. Polysilicon is an important thin film semiconductor material for forming transistors, and has excellent conductive properties. The active layer 20 is a polysilicon layer, and when the polysilicon layer is used for forming the thin film transistor, the active layer 20 and the second metal wire 120 can be overlapped to form a capacitor, so that the pixel circuit has a total storage capacitor with a larger capacitance value, the stability of the gate potential of the driving transistor is improved by increasing the storage capacitor, the phenomenon of display image flicker in the prior art is improved, and the display effect is optimized.
The embodiment of the invention also provides a display device, and fig. 8 is a schematic structural diagram of the display device provided by the embodiment of the invention. The display device may be a mobile phone, a computer, a tablet computer, a smart wearable device, or other electronic devices with a display function, and fig. 8 schematically illustrates a case where the display device 200 is a mobile phone. The display device provided by the embodiment of the present invention includes the display panel provided by any of the above embodiments of the present invention, and thus has a corresponding structure and beneficial effects of the display panel, which are not described herein again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising:
a substrate;
the array circuit layer comprises an active layer and a plurality of metal layers which are stacked on one side of the substrate, a plurality of pixel circuits are formed in the array circuit layer, and each pixel circuit comprises a driving transistor and a storage capacitor electrically connected with the grid electrode of the driving transistor;
the multilayer metal layer comprises a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode; the first metal layer comprises a grid electrode of the driving transistor and a first plate electrode of the storage capacitor electrically connected with the grid electrode of the driving transistor, the second metal layer comprises a second plate electrode of the storage capacitor, the third metal layer comprises a first metal wire, and the second plate electrode is connected with a power supply voltage through the first metal wire; the first polar plate is further connected with the active layer, the multilayer metal layer further comprises a second metal wire, the second metal wire is connected with the first metal wire, the vertical projection of the second metal wire on the substrate is overlapped with the vertical projection of the active layer connected with the first polar plate on the substrate, and the vertical projection of the second metal wire on the substrate is separated from the vertical projections of the first polar plate and the second polar plate on the substrate.
2. The display panel according to claim 1, wherein a dielectric constant between the second metal line and the active layer is larger than a dielectric constant between the first metal line and the active layer.
3. The display panel according to claim 1, wherein the active layer overlapping the second metal line includes a body portion extending in a first direction, and a size of the body portion in a second direction is larger than a size of other active layers extending in the first direction in the second direction, wherein the first direction is perpendicular to the second direction, and the first direction is parallel to an extending direction of the first metal line.
4. The display panel according to claim 1 or 2, wherein the second metal line is located in the second metal layer, and the first metal line and the second metal line are electrically connected by a via.
5. The display panel according to claim 1 or 2, wherein the first metal line extends along a first direction, the multi-layer metal layer further comprises a third metal line and a fourth metal line extending along a second direction, the third metal line is connected to a first scanning signal, the fourth metal line is connected to a second scanning signal, the fourth metal line is located on one side of the third metal line in the first direction, and the first direction is perpendicular to the second direction;
the vertical projections of the first polar plate and the second polar plate on the substrate are positioned on one side of the fourth metal wire far away from the third metal wire, and the vertical projection of the second metal wire on the substrate is positioned between the vertical projections of the third metal wire and the fourth metal wire on the substrate.
6. The display panel according to claim 1, wherein the first metal lines extend along a first direction, the first metal lines include first routing portions and second routing portions that are alternately arranged, two adjacent first routing portions in each first metal line are switched over by the second routing portion therebetween, the first routing portions are located in the third metal layer, and the second routing portions are located in other metal layers in the multi-layer metal layer;
the first routing part is electrically connected with the second metal wire through a via hole.
7. The display panel according to claim 6, wherein the second trace portion is located on the second metal layer, and the first trace portion and the second trace portion are electrically connected through a via.
8. The display panel of claim 6, wherein the third metal layer further comprises a third plate, the third plate is electrically connected to the first plate through a via, and vertical projections of the third plate and the second plate on the substrate overlap.
9. The display panel according to claim 8, wherein a fifth metal line is further included in the third metal layer, one end of the fifth metal line is electrically connected to the active layer connected to the first electrode plate, and the other end of the fifth metal line is electrically connected to the third electrode plate.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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| CN112599010B (en) | 2022-08-09 |
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