CN112597087B - High-reliability low-power-consumption data-consistency satellite-borne processor interconnection structure - Google Patents
High-reliability low-power-consumption data-consistency satellite-borne processor interconnection structure Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
- G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a high-reliability low-power-consumption data-consistency satellite-borne processor interconnection structure which comprises a low-power-consumption management unit, a high-reliability management unit and a data-consistency management unit. The low-power consumption management unit realizes the low-power consumption design of the interconnection structure through methods such as a low data inversion algorithm, a multi-frequency domain design and the like; the high-reliability management unit mainly utilizes a bus separation transmission mechanism, a timing polling monitoring mechanism and an error response timely processing method to realize reliable transmission of data; the data consistency management unit realizes data intercommunication among a plurality of main devices of the interconnection structure in modes of arbitration, request redistribution, monitoring filtration, monitoring cache and the like, and ensures the consistency of data.
Description
Technical Field
The invention relates to an interconnection structure, in particular to a highly reliable low-power-consumption data-consistent satellite-borne processor interconnection structure, and belongs to the field of integrated circuit bus interconnection structure design.
Background
With the continued development of semiconductor and integrated circuit technology, various bus interconnect structures have been proposed in order to ensure higher performance and more reliable data transmission. Currently, the mainstream bus protocol specifications in the world include IBM's CoreConnect bus, ARM's AMBA bus, and Altera's Avalon bus, among others.
However, with the continuous expansion of applications, the processor integrates more and more master-slave devices, the complexity of data access between the master-slave interfaces is continuously increased, and when a plurality of master devices initiate access operation to the same address space, access data may be inconsistent due to internal cache, so that the final processing result is in error; in order to meet the requirements of higher performance and higher bandwidth, the data bit width of the internal interconnection structure is expanded from the original 32 bits to 64 bits, 128 bits or even 256 bits, and when the data access bit width is excessively inverted twice continuously, the power consumption overhead of the interconnection structure is increased; the reliability of data transmission is greatly affected by different application scenes, and the data can be overturned due to electromagnetic interference in the transmission process or transmission errors caused by other interference. In summary, the current single bus design cannot meet the requirements of the embedded processor for low power consumption and high reliability data transmission.
In the design of a processor, requirements on performance, power consumption and reliability of an interconnection structure caused by application diversification need to be met, and meanwhile, as the complexity of communication between interconnection structure devices is improved, problems of data consistency and the like are also involved. Therefore, improvement is needed in the aspect of high-reliability low-delay interconnection structure design, the reliability of data transmission is improved, the transmission power consumption is reduced, and meanwhile, the requirements of transmission performance and data consistency are met.
Disclosure of Invention
The technical solution of the invention is that: the defects of the existing interconnection structure are overcome, and the high-reliability low-power-consumption data-consistency satellite-borne processor interconnection structure is provided, and transmission power consumption is reduced by a multi-clock gating method, a low-data overturning method and the like; the data transmission reliability is improved by introducing a bus separation transmission, timing polling detection and error timely response processing method; and the techniques of arbitration, request redistribution, monitoring filtration, monitoring cache and the like are utilized to ensure the consistency of data transmission of the interconnection structure, and simultaneously, the transmission performance requirement is considered.
The technical scheme of the invention is as follows:
the interconnection structure of the high-reliability low-power-consumption data-consistency satellite-borne processor comprises a low-power-consumption management unit, a high-reliability management unit and a data-consistency management unit;
data consistency management unit: monitoring data transmission of a plurality of devices and caching the data, so as to ensure the consistency of the data among the plurality of devices;
a low power consumption management unit: performing interconnection structure clock and power consumption management;
high reliability management unit: to handle data transmission errors in real time and to prevent bus deadlock.
The high-reliability management unit performs data transmission by using a bus separation transmission mechanism, an error timely detection processing method and a timing polling monitoring mechanism, so that high reliability of data is ensured.
The error timely detection processing method is realized in the following manner:
a check error detection mechanism is added in the bus structure, so that one check bit is added when data is transmitted;
when the data leave the bus, firstly, decoding and checking are carried out, if the checking result is correct, the transmission is continued, and if the checking result is incorrect, the feedback retransmission request is transmitted to the previous stage, so that the data transmission error is timely processed, and the error occurrence which cannot be corrected and detected due to error transmission is avoided.
The bus separation transmission mechanism is realized as follows:
when a certain bus bridge in the interconnection structure receives a data transmission request of a main device, a separation request signal is sent to the main device when the bus which is needed to be used for the data transmission and other buses used for transmission are found to be interlocked, the bus which is requested by the main device but occupied by the data transmission is reserved and temporarily released, so that the other bus bridge interlocked with the bus bridge can obtain the use right of the bus, and after the other bus bridge finishes the data transmission and releases the bus, the current bus bridge finishes the data transmission of the main device, thereby solving the problem of bus deadlock.
The timing polling monitoring mechanism can make special mark for storage slave device access in the interconnection structure, and the special mark is set when the storage slave interface generates read-write access operation; the bus timing inquires the special mark bit, if no setting is found during inquiry, the interconnection structure feeds back to the main device and requests the storage slave device to be accessed in a supplementary mode, so that the storage device can be accessed in the timing time, and the error correction and detection mechanism of the storage device is combined to prevent the accumulation of error overturn and improve the reliability of data in the interconnection structure.
The low-power consumption management unit realizes clock management by using the multi-stage clock gating unit and realizes power consumption management by using a low-data inversion algorithm.
The multi-stage clock gating unit adopts a switching signal to switch the clock state, starts the clock when in work, and cuts off the clock when in idle so as to reduce the power consumption, and comprises a special clock gating unit and an enhanced clock gating unit.
The low data inversion algorithm sets a data polarity indication signal, and when data is transmitted through the interconnection structure, comparison judgment is carried out on the current data and the last transmitted data, and when the data inversion exceeds a preset bit number, the data polarity indication signal is set, and meanwhile polarity inversion is carried out on the current transmitted data.
The low-power consumption management unit adopts a multi-frequency domain design mode, the multi-frequency domain design mode is provided with a plurality of frequency domains, and the interface equipment is hung on the corresponding frequency domain according to the highest frequency requirement of the interface equipment, so that the overall power consumption expenditure of the interconnection structure is reduced under the condition of meeting the interface time sequence requirement;
in the concrete implementation, the high-speed equipment is hung on a high-speed bus, so that the high-speed high-bandwidth transmission requirement is met; hanging medium-speed interface equipment on a medium-speed bus to meet interface time sequence; the low speed device is hung on the low speed bus.
The data consistency management unit realizes consistency of communication data among a plurality of main devices through the arbitration module, the request redistribution module, the monitoring filtering module and the monitoring cache module;
the arbitration module arbitrates the requests according to different priorities, and sends arbitration results to the request reassignment module; the request re-allocation module re-orders and allocates the requests, so that the access with high priority can be responded in the shortest time;
when a master device initiates a data transmission request, a monitoring filter module judges whether monitoring is needed according to the type of a transmission access address space, if the transmission access address space is shared, monitoring requests are sent to all master devices, if other master devices have relevant address data, the data are acquired closely, and the data are sent to a monitoring cache module for caching; if the address space is exclusive, a snoop request is not initiated.
Compared with the prior art, the invention has the beneficial effects that:
(1) The invention provides a high-reliability low-power-consumption interconnection structure, which improves the reliability of data transmission of the interconnection structure, reduces the power consumption of data transmission and simultaneously considers the consistency and the transmission performance of data transmission among a plurality of master-slave devices through a power consumption management unit and a high-reliability management unit.
(2) The invention provides a low data inversion algorithm, which is characterized in that a data polarity indication signal is added, inversion bit number judgment is carried out by comparing current transmission data with last data, and when the number exceeds a preset bit number, the indication signal is pulled up and the data polarity is inverted to reduce the number of data inversion bits, so that partial data transmission power consumption is reduced.
(3) The invention provides a deadlock-preventing interconnection structure, which can effectively avoid deadlock of a data transmission bus by adding a bus separation transmission mechanism and utilizing different equipment type classification hanging modes.
(4) The invention provides a method for timely detecting and processing errors, which comprises the steps of adding a check error detection mechanism into a bus structure, adding a small number of check bits, carrying out error check on data, immediately transmitting feedback to the previous stage and requesting retransmission if errors are found, ensuring the timely processing of the data transmission errors, and avoiding error transmission.
(5) The invention provides an interconnection structure timing polling mechanism, which is added with a timing read-write access identification bit, the interconnection structure performs polling access at timing, if the identification bit is not high, the storage interface is not accessed recently, at the moment, the interconnection structure feeds back to a main device and requests the main device to access the storage device, and by combining an external memory error correction and detection mechanism, the accumulation of error overturn can be effectively prevented, and the reliability of the interconnection structure data is improved.
(6) The invention provides a monitoring filtering and data caching interconnection structure, which judges whether monitoring is needed or not according to the access request type of a main device, and carries out secondary processing of data transmission according to the monitoring result, namely: the operations such as fetching the data from the cache unit of the interconnection structure or fetching the data from the external memory and updating the cache unit are performed, so that the consistency of the data in the interconnection structure is ensured, the external memory access times are reduced, and the data transmission performance is improved.
Drawings
FIG. 1 is a block diagram of an interconnect architecture for a high reliability low power data coherent on-board processor of the present invention;
FIG. 2 is a schematic diagram of polarity inversion of the low data inversion algorithm of the present invention;
FIG. 3 is a schematic diagram of bus specific clock gating of the present invention;
FIG. 4 is a schematic diagram of enhanced clock gating of the present invention;
fig. 5 is a schematic diagram of an example bus deadlock of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in FIG. 1, the high-reliability low-power-consumption data-consistency satellite-borne processor interconnection structure mainly comprises a low-power-consumption management unit, a high-reliability management unit and a data-consistency management unit.
The high-reliability management unit mainly comprises a bus separation transmission mechanism, an error detection processing method and a timing polling detection mechanism, and is used for processing data transmission errors in real time and preventing bus deadlock, so that high reliability of data is ensured; the low-power consumption management unit mainly utilizes a multi-stage clock gating and low-data overturning algorithm to realize the effect of reducing the power consumption of data transmission; the data consistency management unit realizes the consistency of the communication data of a plurality of main devices through the monitoring filtering and the monitoring cache, ensures that the access with high priority can be responded in the shortest time, and gives consideration to the transmission performance of the bus.
The error timely detection processing method is realized in the following way:
a check error detection mechanism is added in the bus structure, so that one check bit is added when data is transmitted;
when the data leave the bus, firstly, decoding and checking are carried out, if the checking result is correct, the transmission is continued, and if the checking result is incorrect, the feedback retransmission request is transmitted to the previous stage, so that the data transmission error is timely processed, and the error occurrence which cannot be corrected and detected due to error transmission is avoided.
A bus deadlock diagram is shown in fig. 5. There are two buses a and B in the figure. The A bus is provided with two Master devices (MA 1 and MA 3) and one Slave device (SA 1). The B bus has two Master devices (MB 1 and MB 3) and one Slave device (SB 1). A. The two buses B are connected through two bus bridges AB and BA. When MA3 and MB3 access SB1 and SA1 through bridges AB and BA simultaneously, MA3 and MB3 occupy bus a and bus B, respectively, and then bridges BA and AB request bus a and B, since the bus is already occupied by MA3 and MB3, they cannot respond to both bridges, resulting in that the bridges cannot feed back data to MA3 and MB3, and at this time, since there is no feedback, a and B cannot continue to transmit data, and continue to occupy the bus, resulting in bus deadlock. Aiming at the deadlock situation, the high-reliability management unit of the invention is added with a bus separation transmission function, when the bridge AB or BA receives a data transmission request of a main device, and discovers that a bus which is needed to be used for the data transmission at this time is interlocked with buses which are used for other transmission, a separation request signal is sent to the main device, the bus which is requested by the main device but occupied by the data transmission at this time is reserved and temporarily released, so that the other bus bridge interlocked with the bus bridge can obtain the use right of the bus, and after the other bus bridge finishes the data transmission of the main device, the current bus bridge finishes the data transmission of the bus, thereby solving the problem of bus deadlock. All devices supporting separate transmission are hung on one side of the support, and other devices are hung on the other side, so that bus deadlock can be prevented.
The timing polling monitoring mechanism can make special mark for storage slave device access in the interconnection structure, and the special mark is set when the storage slave interface generates read-write access operation; the bus timing inquires the special mark bit, if no setting is found during inquiry, the interconnection structure feeds back to the main device and requests the storage slave device to be accessed in a supplementary mode, so that the storage device can be accessed in the timing time, and the error correction and detection mechanism of the storage device is combined to prevent the accumulation of error overturn, so that the reliability of data in the interconnection structure is improved.
As shown in fig. 3 and fig. 4, the low-power management unit in the interconnection structure switches the clock state by adopting a switch signal, and starts the clock during working and cuts off the clock during idle so as to reduce power consumption. Specifically, the low-power consumption management unit is added with a plurality of gating units such as special bus clock gating and enhanced clock gating to perform multi-stage clock management. Power consumption is reduced by input-output exclusive-or gate processing and switching activity to reduce enable signals. Meanwhile, different clock frequency designs are adopted for interfaces with different rates, so that the data transmission power consumption can be effectively reduced while the functions and the data transmission performance are ensured.
The invention provides a low data bit flipping algorithm, which reduces the power consumption overhead caused by flipping by reducing the number of data flipping bits. The low data inversion algorithm sets a data polarity indication signal, and when data is transmitted through the interconnection structure, comparison and judgment are carried out on the current data and the last transmitted data, and when the data inversion exceeds a preset bit number (generally half of the data bit number), the data polarity indication signal is set, and meanwhile, the polarity of the current transmitted data is inverted. So as to reduce the high power consumption overhead caused by excessive inversion bit numbers in the data transmission process.
Taking 64-bit data as an example, from 0 xFFFFFFFFFFFFFFFFFF to 0x000000000000, all 64-bit data transitions. Since the power consumption overhead caused by hopping is very large, reducing the number of bus flip bits as much as possible is an effective measure to reduce the power consumption. The invention adds a polarity indication signal to carry out redundant signal transmission, when the main equipment transmits data through the interconnection structure, decision is carried out between the current transmission data and the last transmission data, and the decision result shows that when the bus turns over to exceed a preset bit number during the transmission of the current data, the polarity indication signal is pulled up, and meanwhile, the high and low levels of each bit of the current transmission data are changed. As shown in fig. 2, the master transmits DATA from DATA1:0x5555555555555555 becomes DATA2:0x55AAAAAAAAAAAAAA, a 56bits signal needs to be flipped, while only an 8bits signal is unchanged. At this time, by deciding that the DATA is flipped more than a predetermined number of times, the master device changes the polarity indication signal while also changing the DATA to DATA3:0xAA55555555555555, so that only 9 data lines need to be flipped in practice. Because the data line is longer in wiring and more in load, the turnover of the data line is reduced in the dense transmission process, and the effect of reducing the power consumption can be achieved.
The low-power consumption management unit adopts a multi-frequency domain design mode, sets a plurality of frequency domains according to different interface equipment requirements, and reduces the overall power consumption expenditure of the interconnection structure under the condition of meeting interface time sequence requirements.
In the concrete implementation, high-speed equipment (such as PCIe, SRIO, DDR and the like) is hung on a high-speed bus, so that the high-speed high-bandwidth transmission requirement is met; hanging medium-speed interface (such as Ethernet) equipment on a medium-speed bus to meet interface time sequence; low-speed devices (e.g., UART, SPI, 1553B, etc.) are hung on the low-speed bus.
The data consistency management unit realizes the consistency of communication data among a plurality of main devices through the arbitration module, the request redistribution module, the monitoring filtering module and the monitoring cache module.
The arbitration module arbitrates the requests according to different priorities, and sends arbitration results to the request reassignment module; the request re-allocation module re-orders and allocates the requests, ensuring that accesses with high priority can be responded in the shortest time.
When a master device initiates a data transmission request, a monitoring filter module judges whether monitoring is needed according to the type of a transmission access address space, if the transmission access address space is shared, monitoring requests are sent to all master devices, if other master devices have relevant address data, the data are acquired closely, and the data are sent to a monitoring cache module for caching; if the address space is exclusive, a snoop request is not initiated.
Through filtering, monitoring and caching, the data consistency of all devices of the interconnection structure is guaranteed, the access frequency to external storage is reduced, and the transmission performance of the interconnection structure is improved.
The invention is not described in detail in part as being well known in the art.
Claims (6)
1. The utility model provides a high reliable low-power consumption data unanimity star carries treater interconnection structure which characterized in that: the system comprises a low-power consumption management unit, a high-reliability management unit and a data consistency management unit;
data consistency management unit: monitoring data transmission of a plurality of devices and caching the data, so as to ensure the consistency of the data among the plurality of devices;
a low power consumption management unit: performing interconnection structure clock and power consumption management;
high reliability management unit: the method is used for processing data transmission errors in real time and preventing bus deadlock;
the high-reliability management unit performs data transmission by using a bus separation transmission mechanism, an error timely detection processing method and a timing polling monitoring mechanism, so that high reliability of data is ensured;
the timing polling monitoring mechanism can make special mark for storage slave device access in the interconnection structure, and the special mark is set when the storage slave interface generates read-write access operation; the bus timing inquires the special mark bit, if no setting is found during inquiry, the interconnection structure feeds back to the main equipment and requests the storage slave equipment to be accessed in a supplementary mode, so that the storage equipment can be accessed in the timing time, and the error correction and detection mechanism of the storage equipment is combined to prevent the accumulation of error overturn and improve the reliability of data in the interconnection structure;
the low-power consumption management unit realizes clock management by using a multi-stage clock gating unit and realizes power consumption management by using a low-data inversion algorithm;
the data consistency management unit realizes consistency of communication data among a plurality of main devices through the arbitration module, the request redistribution module, the monitoring filtering module and the monitoring cache module;
the arbitration module arbitrates the requests according to different priorities, and sends arbitration results to the request reassignment module; the request re-allocation module re-orders and allocates the requests, so that the access with high priority can be responded in the shortest time;
when a master device initiates a data transmission request, a monitoring filter module judges whether monitoring is needed according to the type of a transmission access address space, if the transmission access address space is shared, monitoring requests are sent to all master devices, if other master devices have relevant address data, the data are acquired closely, and the data are sent to a monitoring cache module for caching; if the address space is exclusive, a snoop request is not initiated.
2. The high-reliability low-power-consumption data-consistency satellite-borne processor interconnection structure according to claim 1, wherein the error timely detection processing method is realized by the following steps:
a check error detection mechanism is added in the bus structure, so that one check bit is added when data is transmitted;
when the data leave the bus, firstly, decoding and checking are carried out, if the checking result is correct, the transmission is continued, and if the checking result is incorrect, the feedback retransmission request is transmitted to the previous stage, so that the data transmission error is timely processed, and the error occurrence which cannot be corrected and detected due to error transmission is avoided.
3. The high reliability low power consumption data coherent on-board processor interconnect structure of claim 1, wherein said bus split transport mechanism is implemented as follows:
when a certain bus bridge in the interconnection structure receives a data transmission request of a main device, a separation request signal is sent to the main device when the bus which is needed to be used for the data transmission and other buses used for transmission are found to be interlocked, the bus which is requested by the main device but occupied by the data transmission is reserved and temporarily released, so that the other bus bridge interlocked with the bus bridge can obtain the use right of the bus, and after the other bus bridge finishes the data transmission and releases the bus, the current bus bridge finishes the data transmission of the main device, thereby solving the problem of bus deadlock.
4. The interconnect structure of high reliability and low power consumption data-consistent satellite-borne processor according to claim 1, wherein the multi-stage clock gating unit switches clock states by using switching signals, and switches clocks on during operation and off during idle to reduce power consumption, and comprises a dedicated clock gating unit and an enhanced clock gating unit.
5. The interconnect structure of a highly reliable low power consumption data-compliant satellite-borne processor of claim 1, wherein the low data inversion algorithm sets a data polarity indication signal that determines when data is being transferred through the interconnect structure, and sets the data polarity indication signal when the data is being inverted beyond a predetermined number of bits, and simultaneously inverts the polarity of the data being transferred.
6. The interconnection structure of the highly reliable low-power-consumption data-consistent satellite-borne processor according to claim 1, wherein the low-power-consumption management unit adopts a multi-frequency domain design mode, the multi-frequency domain design mode is provided with a plurality of frequency domains, and the interface equipment is hung on the corresponding frequency domain according to the highest frequency requirement of the interface equipment, so that the overall power consumption expenditure of the interconnection structure is reduced under the condition of meeting the interface time sequence requirement;
in the concrete implementation, the high-speed equipment is hung on a high-speed bus, so that the high-speed high-bandwidth transmission requirement is met; hanging medium-speed interface equipment on a medium-speed bus to meet interface time sequence; the low speed device is hung on the low speed bus.
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| CN101833536A (en) * | 2010-04-16 | 2010-09-15 | 北京航空航天大学 | Reconfigurable on-board computer of redundancy arbitration mechanism |
| CN102929832A (en) * | 2012-09-24 | 2013-02-13 | 杭州中天微系统有限公司 | Cache-coherence multi-core processor data transmission system based on no-write allocation |
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