CN112596976A - Method for monitoring effectiveness of processor between redundancies - Google Patents
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- CN112596976A CN112596976A CN202011491298.2A CN202011491298A CN112596976A CN 112596976 A CN112596976 A CN 112596976A CN 202011491298 A CN202011491298 A CN 202011491298A CN 112596976 A CN112596976 A CN 112596976A
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Abstract
The application provides a method for monitoring the effectiveness of a multi-channel processor, which comprises the following steps: monitoring the running state of the channel processor, and outputting a mark that the channel processor is valid or invalid according to the running state of the channel processor; monitoring the running states of other channel processors except the channel processor, and outputting the marks that the other channel processors are valid or the other channel processors are invalid according to the running states of the other channel processors; when the mark of the channel processor and the mark of at least one other channel processor are simultaneously satisfied, outputting the calculation result of the channel processor; otherwise, the calculation result of the channel processor is not output; and repeating the steps to monitor the calculation results of the other channels. The method provided by the application can realize self-detection of the channel processor and self-detection results of other channels in the multi-channel processor, judge whether the channel is in fault or not together, and improve the accuracy of fault detection.
Description
Technical Field
The application belongs to the technical field of processor self-detection, and particularly relates to a method for monitoring processor effectiveness between redundancies.
Background
In the field of aircraft control, a flight key system generally adopts a computer to complete signal acquisition and processing, and in order to improve the reliability and safety of the system, a redundant processor system architecture is generally adopted. When a single-channel or multi-channel processor fails, a wrong signal can be output after voting, so that the system fails, and the reliability of the system is reduced.
In order to overcome the above problems, a method for determining whether a processor is valid according to a detection signal of the processor and a mutual monitoring result between channels is needed.
Disclosure of Invention
It is an object of the present application to provide a method of monitoring the effectiveness of a multi-channel processor that addresses or mitigates at least one of the problems of the background art.
The technical scheme of the application is as follows: a method of monitoring the effectiveness of a multi-channel processor, the method comprising:
monitoring the running state of the channel processor, and outputting a mark that the channel processor is valid or invalid according to the running state of the channel processor;
monitoring the running states of other channel processors except the channel processor, and outputting the marks that the other channel processors are valid or the other channel processors are invalid according to the running states of the other channel processors;
when the mark of the channel processor and the mark of at least one other channel processor are simultaneously satisfied, outputting the calculation result of the channel processor; otherwise, the calculation result of the channel processor is not output;
and repeating the steps to monitor the calculation results of the other channels.
Further, the output of the valid flags of the present channel processor is satisfied: the instruction of the channel processor is effective, and the self-detection normality of the channel processor and the detection normality of the channel bus are simultaneously met;
otherwise, outputting the invalid mark of the processor of the channel.
Further, the effective judgment method of the channel processor instruction is as follows: the channel reads the instructions of other channels through data mutual transmission, and whether the instructions of the channel are effective is detected through majority voting.
Further, the method for judging whether the detection of the channel bus is normal comprises the following steps: and judging whether the function of the bus for receiving and transmitting data is effective or not through the bus module of the channel.
Further, the judgment method for the self-detection normality of the channel processor comprises the following steps: the channel processor judges whether the calculation function of the channel processor is effective or not through any one or more calculation processes of four arithmetic operations, shifting and negation.
Further, the other channels include at least two channels.
Further, outputting the valid flags for other channel processors is required to satisfy: the instruction validity of other channels and the mutual transmission monitoring validity between other channels are met simultaneously;
otherwise, outputting the invalid mark of the processor of the other channel.
Further, the effective judgment method of the instructions of other channels is as follows: the channel processor reads the instructions of other channel processors, compares whether the instructions of the channel processor are consistent with the instructions of the other channel processors, if so, the instructions of the other channel processors are considered to be valid, otherwise, the instructions of the other channel processors are invalid.
Further, the effective judgment method for mutual transmission monitoring among other channels is as follows: the channel checks the validity of data sent by other channels, if the data is valid, the corresponding other channels are judged to be valid for mutual transmission monitoring, otherwise, the corresponding other channels are judged to be invalid for mutual transmission monitoring.
Further, when the calculation result of the channel processor is judged to be valid, the method further includes:
and judging whether a processor monitoring module which is used for transmitting periodic data with the channel processor is effective or not, and judging that the calculation result of the channel processor is effective when the processor monitoring module outputs effective marks at the same time.
The method provided by the application can realize self-detection of the channel processor and self-detection results of other channels in the multi-channel processor, judge whether the channel is in fault or not together, and improve the accuracy of fault detection.
Drawings
In order to more clearly illustrate the technical solutions provided by the present application, the following briefly introduces the accompanying drawings. It is to be expressly understood that the drawings described below are only illustrative of some embodiments of the invention.
FIG. 1 is a schematic diagram of a method for monitoring the effectiveness of a multi-channel processor according to the present application.
FIG. 2 is a schematic diagram of the effective logic of the channel processor of the present application.
FIG. 3 is a schematic diagram of other channel processor logic implementations of the present application.
FIG. 4 is a schematic diagram of the effective logic of the channel numbering machine of the present application.
Detailed Description
In order to make the implementation objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the drawings in the embodiments of the present application.
As shown in FIG. 1, the method for monitoring the validity of a multi-channel processor provided by the present application is mainly the present channel processor valid (CPUV) logic, other channel processor valid (DPX/Y) logic, and digital computer valid (DPV) logic. The CPUV is used for monitoring whether the channel processor is effective or not, the DPX/Y is used for monitoring whether other channel processors are effective or not, and the DPV is used for integrating the detection results of the CPUV and the DPX/Y and judging whether the channel outputs a calculation result or not.
Taking a three-channel processor system as an example for explanation, the three channels are respectively marked as A, B, C channels, and hereinafter, taking a channel as an example, the channel B, C is not described in detail.
CPUV logic: monitoring the running state of the CPU of the channel, if the CPU of the channel is normal, outputting that the channel is effective, namely CPUV is 1; if the CPU of the channel fails, the output channel is invalid, namely CPUV is equal to 0.
The channel CPUV effective indicates effective, bus self-test normal and CPU self-test normal (& symbol denotes "and", the same applies below), which is shown in fig. 2 in detail.
The effective judgment process of the channel instruction is as follows: the channel A reads the instructions of the channel B and the channel C through data mutual transmission, and whether the instructions of the channel are effective is detected through majority voting;
the effective judgment process of bus self-detection is as follows: the method is realized by a bus module of the channel A, and whether the data receiving and transmitting function of the channel A bus is effective or not is judged;
the effective judgment process of the CPU self-detection is as follows: the CPU of the channel A judges whether the self calculation function of the processor is effective or not through calculation processes of four arithmetic operations, shifting, negation and the like, wherein the calculation process can be any one operation process or a plurality of operation processes.
DPX/Y logic: monitoring the running states of other channel processors, outputting a DPX (X channel) and a DPY (Y channel) as a monitoring result, and outputting the DPX/Y as 1 when at least one of the X/Y channels is normal; when the X/Y channels are all in failure, the output DP/Y is equal to 0. And the monitoring result is sent to the X/Y channel through a hard wire.
The DPX/Y valid is X/Y channel instruction valid and X/Y channel mutual transmission monitoring is valid, which is detailed in fig. 3.
The X/Y channel instruction is valid: the channel A reads CPU instructions of the channel B and the channel C, compares whether the CPU instruction of the channel B/C is consistent with the instruction of the channel A, and judges that the CPU instruction of the channel B/C is effective if the CPU instruction of the channel B/C is consistent with the instruction of the channel A;
the X/Y channel mutual transmission monitoring is effective: and the channel A checks the validity of the data sent by the channel B and the channel C, if the data are valid, the corresponding channel mutual transmission monitoring is judged to be valid, and if not, the corresponding channel mutual transmission monitoring is judged to be invalid.
DPV logic: and monitoring the channel and other channel processors, and judging whether the channel outputs a calculation result. When the DPV is 1, the channel outputs; when the DPV is equal to 0, the channel does not output.
When monitoring the effectiveness of the processor, a processor monitoring module, such as a Watchdog (WD), is usually provided, and the processor (CPU) periodically sends and receives data to the watchdog, and determines that the CPU is faulty when the data sent or received is abnormal.
Therefore, in this embodiment, when a CPU fault (CPUV ═ 0) of the own channel, a watchdog fault (WDV ═ 0) or a remote channel monitoring fault (DPX ═ 0 and DPY ═ 0) occurs, it is determined that the DPV of the own channel is disabled, the DPV ═ 0 is output, and the calculation result of the own channel is not output; when the CPU of the local channel is normal (CPUV is 1) and the watchdog is normal (WDV is 1), and the remote channel monitors more than one normal, it is determined that the DPV of the local channel is valid, and the output DPV is 1, which is shown in fig. 4.
The external circuit of the channel A reads a CPUV self-detection result and a Watchdog (WDV) detection result to judge whether the channel processor is effective or not;
an external circuit of the A channel reads DPX/Y logic to judge whether other channels consider the channel to be effective or not;
the DPV logic truth table is shown in Table 1.
TABLE 1DPV logic truth table
| CPUV | WDV | DPX | DPY | DPV |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
| 0 | - | - | - | 0 |
| - | 0 | - | - | 0 |
| 1 | 1 | 0 | 0 | 0 |
According to the method, for the multi-channel processor system, whether the channel is in fault or not can be judged together according to self-detection results of the channel processor and self-detection results of other channels, and the accuracy of fault detection is improved.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of monitoring the effectiveness of a multi-channel processor, the method comprising:
monitoring the running state of the channel processor, and outputting a mark that the channel processor is valid or invalid according to the running state of the channel processor;
monitoring the running states of other channel processors except the channel processor, and outputting the marks that the other channel processors are valid or the other channel processors are invalid according to the running states of the other channel processors;
when the mark of the channel processor and the mark of at least one other channel processor are simultaneously satisfied, outputting the calculation result of the channel processor; otherwise, the calculation result of the channel processor is not output;
and repeating the steps to monitor the calculation results of the other channels.
2. A method for monitoring the validity of a multi-channel processor as claimed in claim 1, wherein outputting the indicia of validity of the multi-channel processor is performed by: the instruction of the channel processor is effective, and the self-detection normality of the channel processor and the detection normality of the channel bus are simultaneously met;
otherwise, outputting the invalid mark of the processor of the channel.
3. The method of monitoring the validity of a multi-channel processor as set forth in claim 2, wherein the instruction validity determination method of the multi-channel processor is: the channel reads the instructions of other channels through data mutual transmission, and whether the instructions of the channel are effective is detected through majority voting.
4. The method for monitoring the effectiveness of a multi-channel processor as claimed in claim 2, wherein the method for judging the detection normality of the bus of the channel is as follows: and judging whether the function of the bus for receiving and transmitting data is effective or not through the bus module of the channel.
5. The method for monitoring the effectiveness of a multi-channel processor as claimed in claim 2, wherein the method for judging the self-test normality of the multi-channel processor comprises the following steps: the channel processor judges whether the calculation function of the channel processor is effective or not through any one or more calculation processes of four arithmetic operations, shifting and negation.
6. A method of monitoring the effectiveness of a multi-channel processor as defined in claim 1, wherein the other channels include at least two channels.
7. A method for monitoring the validity of a multi-channel processor as claimed in claim 3, wherein the output of the flags indicating the validity of the other channel processors is such that: the instruction validity of other channels and the mutual transmission monitoring validity between other channels are met simultaneously;
otherwise, outputting the invalid mark of the processor of the other channel.
8. A method for monitoring the effectiveness of a multi-channel processor as defined in claim 7 wherein the instruction effectiveness of the other channels is determined by: the channel processor reads the instructions of other channel processors, compares whether the instructions of the channel processor are consistent with the instructions of the other channel processors, if so, the instructions of the other channel processors are considered to be valid, otherwise, the instructions of the other channel processors are invalid.
9. The method of claim 7, wherein the determination that the inter-communication monitoring between other channels is valid is: the channel checks the validity of data sent by other channels, if the data is valid, the corresponding other channels are judged to be valid for mutual transmission monitoring, otherwise, the corresponding other channels are judged to be invalid for mutual transmission monitoring.
10. The method for monitoring the validity of a multi-channel processor as claimed in claim 1, wherein when the calculation result of the present channel processor is judged to be valid, the method further comprises:
and judging whether a processor monitoring module which is used for transmitting periodic data with the channel processor is effective or not, and judging that the calculation result of the channel processor is effective when the processor monitoring module outputs effective marks at the same time.
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