CN112596367A - Electronic clock calibration method and device - Google Patents
Electronic clock calibration method and device Download PDFInfo
- Publication number
- CN112596367A CN112596367A CN202011598349.1A CN202011598349A CN112596367A CN 112596367 A CN112596367 A CN 112596367A CN 202011598349 A CN202011598349 A CN 202011598349A CN 112596367 A CN112596367 A CN 112596367A
- Authority
- CN
- China
- Prior art keywords
- time
- test
- electronic clock
- processor
- test terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G5/00—Setting, i.e. correcting or changing, the time-indication
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Electric Clocks (AREA)
Abstract
The invention discloses a method and a device for calibrating an electronic clock, wherein the electronic clock comprises a processor, and the method comprises the following steps: providing a test terminal, acquiring first test time from a standard time source, and establishing a first synchronous signal generated at the first test time with a processor; based on the first synchronous signal, the electronic clock starts synchronous travel time recording, when a preset test time passes, the test terminal and the processor establish a second synchronous signal, and record second test time obtained from a standard time source when the second synchronous signal is established; calculating the difference value between the second test time and the first test time to obtain a standard time difference; calculating the difference between the standard time difference and the preset test time passed by the electronic clock to obtain the travel time error of the current electronic clock; compensating the travel time of the electronic clock by adopting the travel time error; by the electronic clock calibration method, the time difference calibration can be automatically carried out only by connecting the test terminal with the electronic clock, and the calibration speed is high and accurate.
Description
Technical Field
The invention relates to the technical field of clock calibration, in particular to an electronic clock calibration method and device capable of eliminating clock travel time errors.
Background
An electronic clock is a clock using power supply as driving source and electronic frequency signal as time reference signal, and the electronic clock in the market at present has a common quartz clock, and the frequency generated by a quartz crystal oscillator is provided to a processor, so as to generate a frequency signal to make the clock travel. The clock has the characteristics of easy production and low cost, and has the defects that the travel time is difficult to avoid due to an oscillation source, the monthly error is different from a few seconds to a few minutes, and the error is accumulated, so that the more the clock travels, the larger the error is. In addition, other forms of electronic clocks, such as electric wave clocks and clocks that receive time reference signals through WIFI modules and bluetooth modules, are also on the market.
For an electronic clock, because an electronic time reference signal deviates from a standard time, the clock has an error, the error per month is different from plus or minus a few seconds to a few minutes, and the errors are accumulated, so that the error is larger when the clock goes farther. Therefore, after the electronic clock is assembled, the electronic clock needs to be calibrated, however, the current electronic clock calibration method is generally complicated, and the calibration result is not ideal.
Therefore, there is a need for improvements to existing electronic clock calibration methods.
Disclosure of Invention
The present invention is directed to solving the above-mentioned problems, and provides a method and an apparatus for calibrating an electronic clock with simple operation and accurate timing
In order to achieve the above object, the present invention discloses an electronic clock calibration method, the electronic clock including a processor for processing a time signal, the calibration method including:
providing a test terminal, and electrically connecting the test terminal with the processor;
the test terminal acquires first test time from a standard time source and establishes a first synchronous signal which occurs at the first test time with the processor;
based on the first synchronous signal, when the electronic clock starts to synchronize the travel time record and after the predetermined test time is passed,
the test terminal and the processor establish a second synchronous signal and record second test time obtained from the standard time source when the second synchronous signal is established;
calculating the difference value between the second test time and the first test time to obtain a standard time difference;
calculating the difference between the standard time difference and the preset test time passed by the electronic clock to obtain the current travel time error of the electronic clock;
and compensating the travel time of the electronic clock by adopting the travel time error.
Compared with the prior art, the electronic clock calibration method comprises the steps that a test terminal capable of obtaining standard time from a standard time source is electrically connected with a processor of an electronic clock to be calibrated, the test terminal firstly obtains first test time from the standard time source and establishes a first synchronous signal with the electronic clock, the electronic clock starts to travel according to the first synchronous signal, when the travel time of the electronic clock passes through preset test time, the test terminal establishes a second synchronous signal with the electronic clock, the test terminal records second test time according to the second synchronous signal, and then the accurate time of the preset test time passed by the electronic clock, namely standard time difference, is calculated according to the first test time and the second test time, so that the travel time error of the electronic clock is calculated according to the standard time difference and the preset test time; therefore, by the electronic clock calibration method, the travel time error can be automatically obtained only by connecting the test terminal with the electronic clock, and then the electronic clock can be separated from the test terminal after one or more error tests to obtain the more accurate travel time error, and the time difference calibration is carried out regularly or in real time through the obtained travel time error, so that the calibration speed is high, and the calibration is accurate.
Preferably, the test terminal sends the first synchronization signal to the processor while acquiring the first test time, and the processor controls the electronic clock to test the time according to the first synchronization signal;
the processor sends the second synchronous signal to the test terminal after detecting that the electronic clock passes the preset test time;
the test terminal acquires the current second test time according to the second synchronous signal;
and the test terminal calculates the travel time error according to the first test time, the second test time and the preset test time, and sends the travel time error to the processor.
Preferably, the test terminal sends the first synchronization signal to the processor while acquiring the first test time, and the processor reads and records the first test time in the test terminal and controls the electronic clock to test the time according to the first synchronization signal;
the processor sends the second synchronous signal to the test terminal after detecting that the electronic clock passes the preset test time, and the test terminal records the second test time based on the second synchronous signal;
and the processor reads the second test time in the test terminal, and then the processor calculates the travel time error according to the first test time, the second test time and the preset test time.
Preferably, a charged erasable programmable read only memory electrically connected to the processor is disposed in the electronic clock, and the measured travel time error is stored in the charged erasable programmable read only memory.
Preferably, a built-in storage battery electrically connected to the processor is disposed in the electronic clock, and the electronic clock uses the first test time or the second test time as a standard time.
Preferably, the method for compensating the travel time of the electronic clock by using the travel time error comprises:
and taking the preset test time as a compensation interval, and adjusting the current time of the electronic clock once by adopting the travel time error every time the compensation interval passes.
Preferably, the method for compensating the travel time of the electronic clock by using the travel time error comprises:
and adopting the travel time error to compensate and adjust the time length of each second of the electronic clock.
The invention also discloses an electronic clock calibration device, wherein the electronic clock comprises a processor for processing the time signal, and the calibration device comprises a test terminal and a standard time source electrically connected with the test terminal; the test terminal is used for detecting the travel time error of the electronic clock and comprises a control module, a connection module, a synchronization module and a standard time acquisition module, wherein the connection module is electrically connected with the control module, the synchronization module is used for establishing electrical connection with the processor, the synchronization module is used for establishing a synchronization signal between the test terminal and the processor, and the standard time acquisition module is used for acquiring standard time for testing from the standard time source; the processor is preset with preset test time, and the test terminal or the processor obtains the travel time error of the electronic clock according to the standard time difference in the preset test time.
The invention also includes an electronic clock calibration apparatus comprising one or more processors, memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the electronic clock calibration method as described above.
The present invention also discloses a computer readable storage medium comprising a computer program for testing, the computer program being executable by a processor to perform the electronic clock calibration method as described above.
Drawings
Fig. 1 is a schematic flow chart of an electronic clock calibration method according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating a specific coordination between a test terminal and a processor according to an embodiment of the present invention.
FIG. 3 is a flow chart illustrating the detailed cooperation between the test terminal and the processor according to another embodiment of the present invention.
Fig. 4 is a schematic diagram of an electronic structure of the test terminal and the electronic clock according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of an internal principle of the test terminal in the embodiment of the present invention.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 and 4, the present embodiment discloses a method for calibrating an electronic clock, which includes a processor 100 for processing a time signal provided by a quartz oscillator 101 electrically connected to the processor 100. Specifically, the calibration method comprises the following steps:
s1: providing a test terminal 200 for testing the travel time error of the electronic clock, and electrically connecting the test terminal 200 with the processor 100; in this embodiment, the test terminal 200 and the processor 100 may be connected in a wired or wireless manner;
s2: the test terminal 200 obtains the first test time T from the standard time source 201c1E.g., 2020/12/12/8:30:05, and establishes with processor 100 a first synchronization signal that occurs at a first test time; the standard time source 201 in this embodiment is a satellite signal receiver, such as a GPS module and a beidou module;
s3: based on the first synchronous signal, the electronic clock to be calibrated starts to synchronously record the travel time and passes through the preset test time Ty0After (for example, 24h), the reaction solution is mixed,
s4: the test terminal 200 establishes a second synchronization signal with the processor 100, and records a second test time T acquired from the standard time source 201 when the second synchronization signal is establishedc2E.g., 2020/12/13/8:30: 08;
s5: calculating the difference between the second test time and the first test time to obtain the standard time difference Tc0，Tc0＝Tc2-Tc1＝24:00:03；
S6: calculating the standard time difference Tc0Predetermined test time T elapsed from the passage of the electronic clocky0Difference between them to obtain the travel time error delta T of current electronic clock, where delta T is Tc0-Ty0(ii) a When delta t is zero, the current electronic clock is runningAnd when the delta t is less than zero, the electronic clock travel block is at the standard time. In addition, considering the problem of actual precision, when Δ t is within a certain value range, it can be set that there is no error when the current electronic clock runs. In the present embodiment, Δ t is 3S, which represents that the accumulated error of the current electronic clock within 24h is 3S;
s7: and compensating the travel time of the electronic clock by adopting the travel time error delta t.
The method for compensating the travel time of the electronic clock by adopting the travel time error delta t comprises two methods:
the compensation method 1: and taking the preset test time as a compensation interval, and adjusting the current time of the electronic clock once by adopting the travel time error every time the compensation interval passes. Taking the data in the above embodiment as an example, every 24h passes, the processor 100 drives the pointer driver 103 and the display screen driver 104 to adjust the pointer time or the display time of the current electronic clock forward by 3S.
The compensation method 2 comprises the following steps: and compensating and adjusting the time length of each second of the electronic clock by adopting the travel time error. Still taking the data in the above embodiment as an example, since the time error of the current electronic clock at 24h is 3S, the error of the electronic clock per second is 1/28800, and the frequency of the quartz oscillator 101 in the same group of circuits is adjusted to 1/28800 faster.
It should be noted that, in the above embodiments, both the first synchronization signal and the second synchronization signal are pulse trigger signals.
More specifically, as to the way of cooperation between the test terminal 200 and the processor 100, the present invention discloses the following two specific embodiments:
1. as shown in fig. 2 and 4, the calculation process of the travel time error is completed in the test terminal 200, which is as follows:
s10: the test terminal 200 sends a first synchronization signal to the processor 100 while acquiring the first test time;
s11: the processor 100 controls the electronic clock to test the travel time according to the first synchronization signal;
s12: the processor 100 sends a second synchronization signal to the test terminal 200 after detecting that the electronic clock passes the predetermined test time;
s13: the test terminal 200 obtains a current second test time according to the second synchronization signal;
s14: the test terminal 200 calculates a travel time error according to the first test time, the second test time, and the predetermined test time, and transmits the travel time error to the processor 100.
In this embodiment, a first synchronization signal is sent by the test terminal 200, the processor 100 controls the electronic clock to enter the test mode and start the test timing according to the first synchronization signal, when the test timing ends, the processor 100 sends a second synchronization signal to the test terminal 200, the test terminal 200 records a standard time when the test timing ends, that is, a second test time according to the second synchronization signal, and then the test terminal 200 calculates a timing error and sends the timing error to the processor 100.
2. As shown in fig. 3 and 4, the calculation process of the travel time error is completed in the processor 100, which is as follows:
s20: the test terminal 200 sends a first synchronization signal to the processor 100 while acquiring the first test time;
s21: the processor 100 reads and records a first test time in the test terminal 200, and controls the electronic clock to test the time according to the first synchronization signal;
s22: the processor 100 sends a second synchronization signal to the test terminal 200 after detecting that the electronic clock passes the predetermined test time;
s23: the test terminal 200 records a second test time based on the second synchronization signal;
s24: the processor 100 reads the second test time in the test terminal 200, and then the processor 100 calculates the travel time error according to the first test time, the second test time and the predetermined test time.
In this embodiment, the first synchronization signal is still sent by the test terminal 200, when the processor 100 receives the first synchronization signal, the processor 100 reads a first test time generated in the test terminal 200 at the same time as the first synchronization signal, and simultaneously controls the electronic clock to enter the test mode, when the test is started, after the test travel time is finished, the processor 100 sends a second synchronization signal, reads a second test time generated in the test terminal 200 at the same time as the second synchronization signal, and then, the processor 100 generates a desired travel time error based on the data.
In another preferred embodiment of the electronic clock calibration method of the present invention, when the electronic clock is not equipped with a built-in battery, the electronic clock may be provided with a charged erasable programmable read only memory (EEPROM) electrically connected to the processor 100, and the detected travel time error is stored in the charged erasable programmable read only memory (EEPROM), so that the processor 100 may automatically invoke the travel time error data in the EEPROM to calibrate the electronic clock during the use process of the electronic clock.
In addition, a built-in battery electrically connected to the processor 100 and the quartz oscillator 101 may be provided for the electronic clock, so that the electronic clock is always in a charged state, and the timing error measured during the calibration process is stored in the processor 100. In this embodiment, the electronic clock may start the travel time with the first test time or the second test time as the standard time.
According to the electronic clock calibration method, the test terminal is connected with the electronic clock, the travel time error can be automatically obtained, the electronic clock can be separated from the test terminal after one or more error tests are carried out to obtain the accurate travel time error, the time difference compensation is carried out regularly or in real time through the obtained travel time error, namely, the electronic clock can carry out time difference calibration on the clock by using the obtained travel time error after a period of time or in each second time period in the subsequent travel time separated from the test terminal, and the calibration speed is high and accurate.
The invention also discloses an electronic clock calibration device, the electronic clock comprises a processor 100 for processing the time signal, the calibration device comprises a test terminal 200 and a standard time source 201 electrically connected with the test terminal 200; the test terminal 200 is used for detecting a timing error of an electronic clock, and includes a control module 202, a connection module 203 electrically connected to the control module 202, a synchronization module 204, and a standard time obtaining module 205, where the connection module 203 is used for establishing an electrical connection with the processor 100, the synchronization module 204 is used for establishing a synchronization signal between the test terminal 200 and the processor 100, and the standard time obtaining module 205 is used for obtaining a standard time for a test from the standard time source 201. The processor 100 is preset with a predetermined test time, and the test terminal 200 or the processor 100 obtains the time-lapse error of the electronic clock according to the standard time difference in the predetermined test time. The specific working principle and working mode of the electronic clock calibration device in this embodiment are detailed in the above electronic clock calibration method, and are not described herein again.
The present invention also discloses an electronic clock calibration apparatus comprising one or more processors 100, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors 100, the programs comprising instructions for performing the electronic clock calibration method as described above.
The present invention also discloses a computer readable storage medium comprising a computer program for testing, which is executable by the processor 100 to perform the electronic clock calibration method as described above.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, therefore, the present invention is not limited by the appended claims.
Claims (10)
1. A method of calibrating an electronic clock, said electronic clock comprising a processor for processing a time signal, said method comprising:
providing a test terminal, and electrically connecting the test terminal with the processor;
the test terminal acquires first test time from a standard time source and establishes a first synchronous signal which occurs at the first test time with the processor;
based on the first synchronous signal, when the electronic clock starts to synchronize the travel time record and after the predetermined test time is passed,
the test terminal and the processor establish a second synchronous signal and record second test time obtained from the standard time source when the second synchronous signal is established;
calculating the difference value between the second test time and the first test time to obtain a standard time difference;
calculating the difference between the standard time difference and the preset test time passed by the electronic clock to obtain the current travel time error of the electronic clock;
and compensating the travel time of the electronic clock by adopting the travel time error.
2. The method according to claim 1, wherein the test terminal sends the first synchronization signal to the processor while acquiring the first test time, and the processor controls the electronic clock to perform test timing according to the first synchronization signal;
the processor sends the second synchronous signal to the test terminal after detecting that the electronic clock passes the preset test time;
the test terminal acquires the current second test time according to the second synchronous signal;
and the test terminal calculates the travel time error according to the first test time, the second test time and the preset test time, and sends the travel time error to the processor.
3. The method according to claim 1, wherein the test terminal sends the first synchronization signal to the processor while acquiring the first test time, the processor reads and records the first test time in the test terminal, and controls the electronic clock to perform test timing according to the first synchronization signal;
the processor sends the second synchronous signal to the test terminal after detecting that the electronic clock passes the preset test time, and the test terminal records the second test time based on the second synchronous signal;
and the processor reads the second test time in the test terminal, and then the processor calculates the travel time error according to the first test time, the second test time and the preset test time.
4. The method according to claim 1, wherein a powered erasable programmable read only memory electrically connected to the processor is provided in the electronic clock, and the measured timing error is stored in the powered erasable programmable read only memory.
5. The method according to claim 1, wherein a built-in battery electrically connected to the processor is provided in the electronic clock, and the electronic clock uses the first test time or the second test time as a standard time.
6. The method of calibrating an electronic clock according to claim 1, wherein the step of compensating the travel time of the electronic clock using the travel time error comprises:
and taking the preset test time as a compensation interval, and adjusting the current time of the electronic clock once by adopting the travel time error every time the compensation interval passes.
7. The method of calibrating an electronic clock according to claim 1, wherein the step of compensating the travel time of the electronic clock using the travel time error comprises:
and adopting the travel time error to compensate and adjust the time length of each second of the electronic clock.
8. An electronic clock calibration device, characterized in that, the electronic clock comprises a processor for processing time signals, the calibration device comprises a test terminal and a standard time source electrically connected with the test terminal; the test terminal is used for detecting the travel time error of the electronic clock and comprises a control module, a connection module, a synchronization module and a standard time acquisition module, wherein the connection module is electrically connected with the control module, the synchronization module is used for establishing electrical connection with the processor, the synchronization module is used for establishing a synchronization signal between the test terminal and the processor, and the standard time acquisition module is used for acquiring standard time for testing from the standard time source; the processor is preset with preset test time, and the test terminal or the processor obtains the travel time error of the electronic clock according to the standard time difference in the preset test time.
9. An electronic clock calibration device, comprising:
one or more processors;
a memory;
and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the electronic clock calibration method of any of claims 1 to 7.
10. A computer-readable storage medium comprising a test computer program executable by a processor to perform the method of electronic clock calibration according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011598349.1A CN112596367A (en) | 2020-12-29 | 2020-12-29 | Electronic clock calibration method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011598349.1A CN112596367A (en) | 2020-12-29 | 2020-12-29 | Electronic clock calibration method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112596367A true CN112596367A (en) | 2021-04-02 |
Family
ID=75203512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011598349.1A Pending CN112596367A (en) | 2020-12-29 | 2020-12-29 | Electronic clock calibration method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112596367A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1122622A1 (en) * | 2000-02-01 | 2001-08-08 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method for adjusting an internal clock |
| CN1801008A (en) * | 2004-12-30 | 2006-07-12 | 昆达电脑科技(昆山)有限公司 | Automatic time correction method for electronic device |
| US20090016167A1 (en) * | 2007-07-09 | 2009-01-15 | Seiko Epson Corporation | Time Adjustment Device, Timekeeping Device with a Time Adjustment Device, and a Time Adjustment Method |
| CN102722099A (en) * | 2012-06-13 | 2012-10-10 | 东莞市洲进钟表有限公司 | Clock correction system with error computing function and correction method |
| CN103257570A (en) * | 2012-02-15 | 2013-08-21 | 安凯(广州)微电子技术有限公司 | Electronic clock and electronic clock speed rectifying method |
| CN107894703A (en) * | 2017-11-15 | 2018-04-10 | 广东乐心医疗电子股份有限公司 | Wearable device time calibration method and wearable device |
| CN108037656A (en) * | 2017-11-13 | 2018-05-15 | 深圳还是威健康科技有限公司 | Real-time timepiece chip calibration method, device and terminal device |
-
2020
- 2020-12-29 CN CN202011598349.1A patent/CN112596367A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1122622A1 (en) * | 2000-02-01 | 2001-08-08 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method for adjusting an internal clock |
| CN1801008A (en) * | 2004-12-30 | 2006-07-12 | 昆达电脑科技(昆山)有限公司 | Automatic time correction method for electronic device |
| US20090016167A1 (en) * | 2007-07-09 | 2009-01-15 | Seiko Epson Corporation | Time Adjustment Device, Timekeeping Device with a Time Adjustment Device, and a Time Adjustment Method |
| CN103257570A (en) * | 2012-02-15 | 2013-08-21 | 安凯(广州)微电子技术有限公司 | Electronic clock and electronic clock speed rectifying method |
| CN102722099A (en) * | 2012-06-13 | 2012-10-10 | 东莞市洲进钟表有限公司 | Clock correction system with error computing function and correction method |
| CN108037656A (en) * | 2017-11-13 | 2018-05-15 | 深圳还是威健康科技有限公司 | Real-time timepiece chip calibration method, device and terminal device |
| CN107894703A (en) * | 2017-11-15 | 2018-04-10 | 广东乐心医疗电子股份有限公司 | Wearable device time calibration method and wearable device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7548600B2 (en) | Apparatus and method for compensating the drift of a local clock used as sampling frequency | |
| US8797827B2 (en) | Seismic acquisition system | |
| JP4190348B2 (en) | Position encoder delay compensation system and method | |
| CN107228719B (en) | Temperature calibration method, module to be tested and temperature calibration device | |
| US20110050495A1 (en) | Methods and apparatus for obtaining gnss time in a gnss receiver | |
| CN110311673B (en) | Frequency calibration method, terminal and storage medium | |
| RU2634733C9 (en) | Method and device for determining scattering matrix parameters of test frequency converting device | |
| CN110460505B (en) | Parallel bus time sequence calibration method and device and receiving end equipment | |
| JP2007078405A (en) | Timing program of software timepiece | |
| EA015659B1 (en) | Method for reducing cumulative timing error of oscillator frequency by adjusting clock frequency | |
| CN112543078A (en) | Network time server calibration method and device based on satellite common view | |
| US20100007392A1 (en) | Crystal auto-calibration method and apparatus | |
| CN107566105B (en) | Time synchronization equipment compensation method, device, storage medium and computer equipment thereof | |
| KR101214666B1 (en) | Positioning device, positioning method and storage medium storing program | |
| CN113377054B (en) | Data synchronization method and device | |
| CN112596367A (en) | Electronic clock calibration method and device | |
| JP5666428B2 (en) | Method and apparatus for obtaining GNSS time in GNSS receiver | |
| CN105137751A (en) | Calibration system for measuring production scheduling platform time value and calibration method thereof | |
| CN112433469B (en) | 1PPS time synchronization system and method based on feedback mechanism | |
| JP2002217722A (en) | Reference frequency generator | |
| US10422809B2 (en) | Electronic apparatus and program | |
| CN101488751B (en) | Measurement system and method for temperature frequency correcting apparatus | |
| CN113267186B (en) | Data synchronous acquisition system and data synchronous acquisition method | |
| CN114978403A (en) | Method and device for measuring clock holding phase deviation value | |
| JP2007292662A (en) | Data recording apparatus and time calibrating method of same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |