CN112596315B

CN112596315B - Array substrate, preparation method thereof and display device

Info

Publication number: CN112596315B
Application number: CN202011480791.4A
Authority: CN
Inventors: 崔贤植; 梁蓬霞; 方正; 石戈; 杨松; 李鸿鹏; 孙艳六; 韩佳慧
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-12-15
Filing date: 2020-12-15
Publication date: 2022-09-09
Anticipated expiration: 2040-12-15
Also published as: CN112596315A

Abstract

The patent refers to the field of 'semiconductor devices and electric solid state devices'. The array substrate comprises a substrate, a plurality of scanning signal lines, a plurality of data signal lines and a pixel unit, wherein the plurality of scanning signal lines, the plurality of data signal lines and the pixel unit are arranged on the substrate, the pixel unit comprises a plate electrode and a slit electrode, the slit electrode is arranged on one side, far away from the substrate, of the plate electrode, the slit electrode comprises a first edge area and a second edge area, the first edge area and the second edge area are arranged in the first direction, a third edge area and a fourth edge area are arranged in the second direction, the first edge area, the second edge area, the third edge area and the fourth edge area enclose a slit area, the slit area comprises a first slit, the end portion of the first slit is close to the first edge area, and a second slit, the end portion of the second slit is close to the second edge area, and the first slit penetrates through the first edge area or the second slit penetrates through the second edge area. The disclination lines are avoided by breaking the symmetrical electric field formed by the first and second edge regions.

Description

Array substrate, preparation method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.

Background

The liquid crystal panel can be classified into: twisted Nematic (TN) type, In Plane Switching (IPS) type, Advanced Super Dimension Switch (ADS) type, and the like. The liquid crystal panel in the ADS display mode forms a multidimensional electric field through an electric field generated by the edge area of the slit electrode in the same plane and an electric field generated between the slit electrode and the plate electrode layer, so that all liquid crystal molecules between the electrodes and right above the electrodes rotate. The liquid crystal panel in the ADS display mode has the advantages of high picture quality, high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no ripple (push Mura), and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

An embodiment of the present invention provides an array substrate, including: the pixel unit comprises a plate electrode and a slit electrode arranged on one side of the plate electrode far away from the substrate, the slit electrode corresponds to the position of the plate electrode, the slit electrode comprises a first edge area and a second edge area arranged in the first direction, a third edge area and a fourth edge area arranged in the second direction, the first edge area, the second edge area, the third edge area and the fourth edge area enclose a slit area, and the slit area comprises a first slit with the end part close to the first edge area and a second slit with the end part close to the second edge area, the first slit penetrates the first edge region or the second slit penetrates the second edge region.

In some exemplary embodiments, the slit regions include a first slit region and a second slit region arranged in the second direction, each of the first slit region and the second slit region includes a plurality of first slits and a plurality of second slits arranged in parallel, and an extending direction of the slits of the first slit region intersects an extending direction of the slits of the second slit region.

In some exemplary embodiments, the slits of the first slit region and the second slit region are symmetrically disposed with respect to a center line of the slit electrode in the second direction.

In some exemplary embodiments, the slit electrode is a common electrode provided to supply a common voltage signal, and the plate electrode is provided as a pixel electrode to supply a pixel voltage signal.

In some exemplary embodiments, the array substrate further includes a shielding layer, the shielding layer is located on a side of the data signal line away from the base, the shielding layer is connected to the common signal line connected to the common electrode, an overlapping region exists between an orthographic projection of the shielding layer on the base and an orthographic projection of the data signal line on the base, and the shielding layer is configured to shield the data signal line and prevent an electric field from being formed between the data signal line and the slit electrode.

In some exemplary embodiments, the data signal lines include a first data signal line positioned at one side of the pixel unit in the first direction and a second data signal line positioned at the other side of the pixel unit in the first direction, the first edge region being adjacent to the first data signal line;

the second slit penetrates through the second edge area, an overlapping area exists between the orthographic projection of the first edge area on the substrate and the orthographic projection of the first data signal line on the substrate, and the shielding layer is arranged in an area corresponding to the overlapping area; or the like, or, alternatively,

the first slit penetrates through the first edge area, an overlapping area exists between the orthographic projection of the second edge area on the substrate and the orthographic projection of the second data signal line on the substrate, and the shielding layer is arranged to be an area corresponding to the overlapping area of the second edge area.

In some exemplary embodiments, the shielding layer extends in the second direction and is spaced apart from the slit electrode in the first direction.

In some exemplary embodiments, the shielding layer is disposed in the same layer as the slit electrode.

In some exemplary embodiments, a width of the overlap region is equal to a width of the data signal line in the first direction, and a length of the overlap region is greater than or equal to a length of the slit electrode in the second direction.

In some exemplary embodiments, the common signal line is disposed in the same layer as the scan signal line; alternatively, the common signal line and the data signal line are provided in the same layer.

The embodiment of the invention also provides a display device which comprises the array substrate provided by the embodiment.

The embodiment of the invention also provides a preparation method of the array substrate, which comprises the following steps: forming a plurality of scanning signal lines and a plurality of data signal lines on a substrate, and a pixel unit defined by the plurality of scanning signal lines and the plurality of data signal lines crossing each other, the plurality of scanning signal lines extending along a first direction and spaced apart in a second direction, the plurality of data signal lines extending along the second direction and spaced apart in the first direction, the first direction and the second direction crossing each other, the pixel unit including a plate electrode and a slit electrode disposed at a side of the plate electrode away from the substrate, the slit electrode corresponding to the plate electrode in position, the slit electrode including a first edge region and a second edge region disposed in the first direction, and a third edge region and a fourth edge region disposed in the second direction, the first edge region, the second edge region, the third edge region, and the fourth edge region enclosing a slit region, the slit region including a first slit having an end portion adjacent to the first edge region and a second slit having an end portion adjacent to the second edge region, the first slit penetrates the first edge region or the second slit penetrates the second edge region.

In some exemplary embodiments, forming a plurality of scan signal lines and a plurality of data signal lines on a substrate and pixel units defined by the plurality of scan signal lines and the plurality of data signal lines crossing each other includes:

forming a gate metal layer on a substrate, wherein the gate metal layer comprises a gate electrode and a plurality of scanning signal lines;

forming a first insulating layer on one side of the gate metal layer far away from the substrate;

the active layer is arranged on one side, far away from the gate metal layer, of the first insulating layer;

forming a source drain metal layer on one side of the active layer, which is far away from the substrate, wherein the source drain metal layer comprises a first pole, a second pole, a plurality of data signal lines and a plurality of common signal lines;

forming a pixel electrode on one side of the source drain metal layer, which is far away from the substrate, wherein the pixel electrode is a plate electrode;

forming a second insulating layer on one side of the pixel electrode, which is far away from the substrate, wherein the second insulating layer is provided with a first through hole for exposing the common signal line;

forming a common electrode on one side of the second insulating layer, which is far away from the substrate, wherein the common electrode is a slit electrode and is connected with a common signal line through a first through hole;

wherein, form the second insulating layer in the pixel electrode keeps away from one side of basement, still include:

forming a second via hole exposing the common signal line on the second insulating layer;

forming a common electrode on the side of the second insulating layer far away from the substrate, and further comprising: forming a shielding layer on one side of the second insulating layer, which is far away from the substrate;

an overlapping region exists between the orthographic projection of the shielding layer on the substrate and the orthographic projection of the data signal line on the substrate.

According to the array substrate, the preparation method thereof and the display device provided by the embodiment of the invention, the first slit on the slit electrode penetrates through the first edge region or the second slit penetrates through the second edge region, and the driving conditions of the first edge region and the second edge region are changed, so that reverse electric fields are not generated between the first edge region and the plate electrode and between the second edge region and the plate electrode, liquid crystals at the positions of the first edge region and the second edge region are prevented from deflecting oppositely to generate collision regions, a disclination line is further avoided, the display contrast is improved, and the display effect is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Other aspects will be apparent upon reading and understanding the attached figures and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and are not intended to limit the invention.

FIG. 1 is a structural diagram of a display panel;

FIG. 2 is a plan view of a common electrode and a pixel electrode of the display panel shown in FIG. 1;

FIG. 3 is a display state diagram of the display panel;

fig. 4 is a structural view of an array substrate according to an exemplary embodiment of the present invention;

FIG. 5 is a cross-sectional view taken at the location A-A in FIG. 4;

FIG. 6 is a structural diagram of another display panel;

fig. 7 is a structural view of another array substrate according to an exemplary embodiment of the present invention;

FIG. 8 is a cross-sectional view taken at the location A-A in FIG. 7;

fig. 9 is a display state diagram of a display panel to which the array substrate of fig. 7 is applied;

FIG. 10 is a schematic structural view after a via pattern is formed in accordance with an exemplary embodiment of the present invention;

fig. 11 is a cross-sectional view taken at a-a of fig. 10.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

Fig. 1 is a structural diagram of a display panel, fig. 2 is a plan view of a common electrode and a pixel electrode in the display panel shown in fig. 1, and fig. 3 is a display state diagram of the display panel. The display panel 1 includes an array substrate 10 and a color filter substrate 20 which are arranged in a box-to-box manner, and a liquid crystal 30 arranged between the array substrate 10 and the color filter substrate 20. The array substrate 10 includes a substrate 100, a gate 101 and a pixel electrode 102 disposed on the substrate 100, a first insulating layer 103 disposed on a side of the gate 101 away from the substrate 100, an active layer 104 disposed on a side of the first insulating layer 103 away from the gate 101, a first pole 105 and a second pole 106 disposed on a side of the active layer 104 away from the first insulating layer 103, a second insulating layer 107 covering the first pole 105, the second pole 106 and the active layer 104, and a common electrode 108 and a connection electrode 109 disposed on a side of the second insulating layer 107 away from the pixel electrode 102, the gate 101 corresponds to the active layer 104, an end of the first pole 105 adjacent to the second pole 106 overlaps the active layer 104, an end of the second pole 106 adjacent to the first pole 105 overlaps the active layer 104, the first pole 105 may be a source electrode, the second pole 106 may be a drain electrode, a via hole exposing the second pole 106 and the pixel electrode 102 is disposed on the second insulating layer 107, the connection electrode 109 is connected to the second electrode 106 and the pixel electrode 102 through a via hole, and the common electrode 108 corresponds to the pixel electrode 102. The common electrode 108 is a slit electrode, and the pixel electrode 102 is a plate electrode. The electric field generated by the edge area of the slit electrode and the electric field generated between the slit electrode and the plate electrode form a multidimensional electric field. The common electrode 108 includes a first edge region 110 and a second edge region 111 disposed in a first direction X, which is an extending direction of a scan signal line of a display region of the array substrate 10, and a third edge region 112 and a fourth edge region 113 disposed in a second direction Y, which is an extending direction of a data signal line of the display region of the array substrate 10. The first edge region 110, the second edge region 111, the third edge region 112 and the fourth edge region 113 enclose a slit region 11, and the slit region 11 is provided with a slit. The orthographic projection of the slit region 11 on the substrate 100 is located within the range of the orthographic projection of the pixel electrode 102 on the substrate 100. The liquid crystal 30 is a negative liquid crystal, the liquid crystal 30 is vertically aligned, when the display panel 1 operates, since the driving electric fields of the first edge region 110 and the second edge region 111 are symmetrical, that is, an electric field which is right and vertical to the alignment direction of the liquid crystal is generated between the first edge region 110 and the pixel electrode 102, the liquid crystal 30 is deflected to the right by the action of the right vertical electric field, an electric field which is left and vertical to the alignment direction of the liquid crystal 30 is generated between the second edge region 111 and the pixel electrode 102, the liquid crystal 30 is deflected to the left by the action of the left vertical electric field, the liquid crystal 30 at the positions of the first edge region 110 and the second edge region 111 are deflected in opposite directions, the liquid crystal 30 in the area where collision occurs is pressed by the liquid crystal 30 at both sides, so that the liquid crystal maintains vertical alignment, cannot be driven, and the backlight cannot penetrate, so that the black disclination (or phase dislocation) line 2 as shown in fig. 3 occurs, causing the reduction of the display contrast, causing poor display.

The embodiment of the invention provides an array substrate, a preparation method of the array substrate and a display device. The array substrate comprises a substrate, a plurality of scanning signal lines and a plurality of data signal lines which are arranged on the substrate, and a pixel unit defined by the plurality of scanning signal lines and the plurality of data signal lines in a crossed manner, wherein the plurality of scanning signal lines extend along a first direction and are spaced in a second direction, the plurality of data signal lines extend along the second direction and are spaced in the first direction, the first direction and the second direction are intersected, the pixel unit comprises a plate electrode and a slit electrode which is arranged on one side, far away from the substrate, of the plate electrode, the slit electrode corresponds to the plate electrode in position, the slit electrode comprises a first edge area and a second edge area which are arranged in the first direction, a third edge area and a fourth edge area which are arranged in the second direction, the first edge area, the second edge area, the third edge area and the fourth edge area enclose a slit area, the slit area comprises a first slit with the end part close to the first edge area and a second slit with the end part close to the second edge area, the first slit penetrates the first edge region or the second slit penetrates the second edge region.

According to the array substrate, the preparation method thereof and the display device provided by the embodiment of the invention, the slits on the slit electrodes are arranged to penetrate through the first edge area or the second edge area, and the symmetrical driving electric field formed by the first edge area and the second edge area is damaged, so that the liquid crystals at the positions of the first edge area and the second edge area are prevented from deflecting oppositely to generate a collision area, a disclination line is further prevented from being generated, the display contrast is improved, and the display effect is improved.

The technical solution of the embodiments of the present invention is exemplarily described below with reference to the accompanying drawings.

Fig. 4 is a structural view of an array substrate according to an exemplary embodiment of the present invention, and fig. 5 is a cross-sectional view taken along a-a of fig. 4. In some exemplary embodiments, as shown in fig. 4 and 5, the array substrate 10 includes a base 100 and a plurality of scan signal lines 116 and a plurality of data signal lines 117 disposed on the base 100 and pixel units defined by the plurality of scan signal lines 116 and the plurality of data signal lines 117 crossing each other, the plurality of scan signal lines 116 extend in a first direction X and are spaced apart in a second direction Y, the plurality of data signal lines 117 extend in the second direction Y and are spaced apart in the first direction X, and the first direction X intersects the second direction Y, for example, the first direction X and the second direction Y may be perpendicular. The pixel unit comprises a plate electrode 118 and a slit electrode 119 arranged on the side of the plate electrode 118 far away from the substrate 100, wherein the slit electrode 119 corresponds to the plate electrode 118. The slit electrode 119 includes a first edge region 110 and a second edge region 111 disposed in the first direction X, and a third edge region 112 and a fourth edge region 113 disposed in the second direction Y, the first edge region 110, the second edge region 111, the third edge region 112, and the fourth edge region 113 enclose a slit region 11, the slit region 11 includes a first slit 114 having an end portion adjacent to the first edge region 110, and a second slit 115 having an end portion adjacent to the second edge region 111, and the second slit 115 penetrates the second edge region 111. In an exemplary implementation, the first slit 114 penetrates the first edge region 110. In other exemplary embodiments, the slit region 11 further includes a third slit having one end adjacent to the first edge region 110 and the other end adjacent to the second edge region 111 in the extending direction thereof, that is, the third slit is both the first slit 114 and the second slit 115.

According to the array substrate 10 provided by the exemplary embodiment of the present invention, the first slits 114 on the slit electrodes 119 penetrate through the first edge region 110 or the second slits 115 penetrate through the second edge region 111, and the symmetric driving electric field formed by the first edge region 110 and the second edge region 111 is destroyed, so that the direction of the electric field generated between the first edge region 110 and the plate-shaped electrode 118 is not opposite to the direction of the electric field generated between the second edge region 111 and the plate-shaped electrode 118, and the liquid crystals 30 at the positions of the first edge region 110 and the second edge region 111 are prevented from deflecting towards each other to generate a collision region, thereby avoiding generation of disclination lines, improving display contrast, and improving display effect.

In some exemplary embodiments, as shown in fig. 4, the slit region 11 includes a first slit region 11a and a second slit region 11b arranged along the second direction Y, each of the first slit region 11a and the second slit region 11b includes a plurality of first slits 114 and a plurality of second slits 115 arranged in parallel, and an extending direction of the slits of the first slit region 11a intersects with an extending direction of the slits of the second slit region 11 b. The extending direction of the slits of the first slit region 11a and the extending direction of the slits of the second slit region 11b may both intersect the first direction X and the second direction Y. In an example, the slits of the first slit region 11a and the second slit region 11b are symmetrically arranged with respect to the central line L of the slit electrode 119 in the second direction Y, and the extending direction of the slits of the first slit region 11a and the extending direction of the slits of the second slit region 11b form an angle of 60 ° to 150 °, such as 90 ° or 120 °. In another example, the width of the first slits 114 is 5 to 10 micrometers and the pitch of the first slits 114 is 2 to 4 micrometers in a direction perpendicular to the extending direction of the first slits 114. The width of the second slits 115 is 5 to 10 micrometers in a direction perpendicular to the extending direction of the second slits 115, and the pitch of the second slits 115 is 2 to 4 micrometers.

In some exemplary embodiments, as shown in fig. 4 and 5, the array substrate 10 includes a thin film transistor and a common signal line 120 disposed on the substrate 100, the thin film transistor includes a gate 101, a first pole 105 and a second pole 106, the gate 101 is connected to the scan signal line 116, the first pole 105 is connected to the data signal line 117, the second pole 106 is connected to the plate electrode 118, and the common signal line 120 is connected to the slit electrode 119. The first electrode 105 may be one of a source electrode and a drain electrode, the second electrode 106 may be the other of the source electrode and the drain electrode, and the plate electrode 118 is connected to the second electrode 106 for supplying a pixel voltage signal, and thus, the plate electrode 118 is the pixel electrode 102, and the slit electrode 119 is connected to the common signal line 120 for supplying a common voltage, and thus, the slit electrode 119 is the common electrode 108, and at this time, the array substrate 10 is in a HADS (High Aperture ratio Advanced-Super Dimensional Switching) mode. In one example, the array substrate 10 includes a gate metal layer disposed on a substrate 100, a first insulating layer 103 disposed on a side of the gate metal layer away from the substrate 100, an active layer 104 disposed on a side of the first insulating layer 103 away from a gate electrode 101, a source drain metal layer and a pixel electrode 102 disposed on a side of the active layer 104 away from the first insulating layer 103, a cover pixel electrode 102, the pixel structure comprises a source-drain metal layer, a second insulating layer 107 of the active layer 104 and a common electrode 108 arranged on one side of the second insulating layer 107 far away from the pixel electrode 102, the gate metal layer comprises a gate 101, a scanning signal line 116 and a common signal line 120, the source-drain metal layer comprises a first pole 105, a second pole 106 and a data signal line 117, the active layer 104, the gate 101, the first pole 105 and the second pole 106 form a thin film transistor, the common electrode 108 is connected with the common signal line 120 through a through hole arranged on the second insulating layer 107, and the common signal line 120 is parallel to the scanning signal line 116. In another example, the common signal line 120 is disposed in the same layer as the source-drain metal layer, and the common signal line 120 is parallel to the data signal line 117.

In other exemplary embodiments, the array substrate 10 includes a thin film transistor and a common signal line 120 disposed on the substrate 100, the thin film transistor includes a gate 101, a first pole 105 and a second pole 106, the gate 101 is connected to the scan signal line 116, the first pole 105 is connected to the data signal line 117, the second pole 106 is connected to the slit electrode 119, and the common signal line 120 is connected to the plate electrode 118. The first electrode 105 may be one of a source electrode and a drain electrode, the second electrode 106 may be the other of the source electrode and the drain electrode, and the slit electrode 119 is connected to the second electrode 106 for supplying a pixel voltage signal, and thus, the slit electrode 119 is the pixel electrode 102, and the plate electrode 118 is connected to the common signal line 120 for supplying a common voltage, and thus, the plate electrode 118 is the common electrode 108, and at this time, the array substrate 10 is in the ADS mode. In one example, the common signal line 120 is disposed at the same layer as the gate electrode 101, and the common signal line 120 is parallel to the scan signal line 116. In another example, the common signal line 120 is disposed in the same layer as the first and

second poles

105 and 106, and the common signal line 120 is parallel to the data signal line 117.

In some exemplary embodiments, as shown in fig. 4 and 5, the array substrate 10 further includes a shielding layer (left area of the two-dot chain line in fig. 4) 121, the shielding layer 121 is located on a side of the data signal line 117 away from the substrate 100, the shielding layer 121 is connected to the common signal line 120 connected to the common electrode 108, there is an overlapping area between an orthographic projection of the shielding layer 121 on the substrate 100 and an orthographic projection of the data signal line 117 on the substrate 100, and the shielding layer 121 is configured to shield the data signal line 117 to prevent an electric field from being formed between the data signal line 117 and the slit electrode 119. Fig. 6 shows a structural view of another display panel. As shown in fig. 6, the voltage of the data signal line 117 continuously varies according to a control signal output from a Timing Controller (T-con). An electric field E is generated between the data signal line 117 and the slit electrode 119 due to a voltage difference, and the liquid crystal 30 at the right side of the slit electrode 119 is deflected leftward, and the liquid crystal 30 deflected leftward collides with the liquid crystal 30 deflected rightward from the left side of the slit electrode 119, thereby generating a disclination line. In this example, the shielding layer 121 can shield the data signal line 117, so as to prevent an electric field from being formed between the slit electrode 119 and the data signal line 117 when the voltage of the data signal line 117 varies, thereby preventing the liquid crystal 30 on the side of the slit electrode 119 adjacent to the data signal line 117 from colliding with the normally deflected liquid crystal 30, and preventing disclination lines from being generated. In one example, in the first direction X, the width of the overlapping area is equal to the width of the data signal line 117, and in the second direction Y, the length of the overlapping area is greater than or equal to the length of the slit electrode 119.

In some exemplary embodiments, as shown in fig. 4, the data signal line 117 includes a first data signal line 117a on one side of the pixel unit in the first direction X and a second data signal line 117b on the other side of the pixel unit in the first direction X, the first edge region 110 is adjacent to the first data signal line 117a, the second slit 115 penetrates through the second edge region 111, an overlapping region exists between a forward projection of the first edge region 110 on the substrate 100 and a forward projection of the first data signal line 117a on the substrate 100, and the shielding layer 121 is disposed as a region of the first edge region 110 corresponding to the overlapping region, wherein a width of the overlapping region is equal to a width of the second data signal line 117b in the first direction X, and a length of the overlapping region is equal to a length of the first edge region 110 in the second direction Y. In another example, the first slit 114 penetrates the first edge region 110, an overlapping region exists between an orthogonal projection of the second edge region 111 on the substrate 100 and an orthogonal projection of the second data signal line 117b on the substrate 100, and the shielding layer 121 is disposed as a region of the second edge region 110 corresponding to the overlapping region. Wherein, in the first direction X, the width of the overlapping area is equal to the width of the first data signal line 117a, and in the second direction Y, the length of the overlapping area is equal to the length of the second margin region 111. In this example, by extending the first edge region 110 or the second edge region 111 which is not penetrated by the slit such that the first edge region 110 or the second edge region 111 overlaps the data signal line 117, the first edge region 110 or the second edge region 111 functions to shield the data signal line 117.

In some exemplary embodiments, unlike the array substrate 10 shown in fig. 4, the common signal line 120 is disposed in the same layer as the data signal line 117, and the common signal line 120 is parallel to the data signal line 117.

Fig. 7 is a structural view of another array substrate according to an exemplary embodiment of the present invention, fig. 8 is a cross-sectional view taken at a position a-a in fig. 7, and fig. 9 is a display state diagram of a display panel to which the array substrate shown in fig. 7 is applied. In some exemplary embodiments, as shown in fig. 7 and 8, the plate electrode 118 is the pixel electrode 102, the slit electrode 119 is the common electrode 121, the shielding layer 121 extends in the second direction Y and is spaced apart from the slit electrode 119 in the first direction X, and the shielding layer 121 is connected to the common signal line 120. In an exemplary embodiment, the array substrate 10 includes a substrate 100 and a gate electrode 101 disposed on the substrate 100, a first insulating layer 103 disposed on a side of the gate electrode 101 away from the substrate 100, an active layer 104 disposed on a side of the first insulating layer 103 away from the substrate 100, a first pole 105, a second pole 106, a data signal line 117, and a common signal line 120 disposed on a side of the active layer 104 away from the substrate 100, and a pixel electrode 102, a second insulating layer 107 covering the first pole 105, the second pole 106, the data signal line 117, and the common signal line 120, and the pixel electrode 102, and a common electrode 108 and a shielding layer 121 disposed on a side of the second insulating layer 107 away from the pixel electrode 102, the pixel electrode 102 is connected to the second pole 106 of the thin film transistor, the pixel electrode 102 is a plate electrode 118, the common electrode 108 is connected to the common signal line 120 through a via hole (not shown) disposed on the second insulating layer 107, the common electrode 108 is a slit electrode 119. The shield layer 121 extends in the second direction Y and is spaced apart from the slit electrode 119 in the first direction X. The shield layer 121 is disposed on the same layer as the slit electrode 119, and the shield layer 121 is connected to the common signal line 120 through a via hole disposed on the second insulating layer 107. When the slit electrode 119 is used as the shielding layer 121, a capacitance is formed between the slit electrode 119 and the data signal line 117, and in the process of continuous variation of the voltage on the data signal line 117, the common voltage on the slit electrode 119 is changed, and a voltage coupling (Vcom coupling) phenomenon is generated, thereby causing Greenish display and uneven horizontal gray (X-talk). In this example, the independent shielding layer 121 is used to prevent Vcom coupling phenomenon when the slit electrode 119 is used as the shielding layer 121, and the shielding layer 121 is connected to the common signal line 120, and the voltage on the shielding layer 121 is the same as that of the slit electrode 119, so that abnormal deflection of the liquid crystal 30 due to voltage difference generated between the shielding layer 121 and the slit electrode 119 is further avoided, as shown in fig. 9, the display panel to which the array substrate 10 according to the exemplary embodiment of the present invention is applied does not generate a decoupling line during displaying.

The following is an exemplary description of the fabrication process of the array substrate. In the manufacturing process, the "patterning process" includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist and the like for a metal material, an inorganic material or a transparent conductive material, and processes of coating an organic material, mask exposure, development and the like for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The phrase "A and B are disposed in the same layer" means that A and B are formed simultaneously by the same patterning process.

In an exemplary embodiment, the preparation process of the array substrate includes:

(1) and forming a gate metal layer pattern. Forming the gate metal layer pattern includes: a first metal thin film is deposited on the substrate 100 and patterned, and then, as shown in fig. 10 and 11, a gate metal layer is patterned. The gate metal layer pattern includes a plurality of gate electrodes 101 and a plurality of scan signal lines 116 correspondingly connected to the gate electrodes 101, and the plurality of scan signal lines 116 extend in the first direction X and are spaced apart in the second direction Y.

(2) An active layer pattern is formed. The forming of the active layer pattern includes: on the substrate 100 on which the aforementioned patterns are formed, a first insulating film and an active layer film are deposited, and after a patterning process, as shown in fig. 10 and 11, an active layer 104 pattern is formed, the first insulating film forms a first insulating layer 103, and the first insulating layer 103 may also be referred to as a gate insulating layer. The active layer 104 pattern includes an active layer 104 corresponding to the position of the gate electrode 101.

(3) And forming a source drain metal pattern. Forming the source drain metal pattern includes: on the substrate 100 with the aforementioned pattern formed thereon, a second metal film is deposited, and a source-drain metal pattern is formed through a patterning process, as shown in fig. 10 and 11. The source-drain metal pattern includes a first electrode 105, a second electrode 106, a data signal line 117, and a common signal line 120. An end of the first pole 105 adjacent to the second pole 106 overlaps the active layer 104, an end of the second pole 106 adjacent to the first pole 105 overlaps the active layer 104, and a portion of the active layer 104 between the first pole 105 and the second pole 106 forms a conductive channel. The first electrode 105 may be a source electrode connected to the data signal line 117, and the second electrode 106 may be a drain electrode. The data signal line 117 includes a plurality of lines, and extends in the second direction Y and is spaced apart in the first direction X. The plurality of data signal lines 117 and the plurality of scanning signal lines 116 intersect to define a plurality of pixel units. The common signal line 120 includes a plurality of common signal lines 120 and data signal lines 117 connected to the same pixel unit, and extends in the second direction Y and is spaced apart in the first direction X, one of the common signal line 120 and the data signal line 117 is disposed at one side of the pixel unit in the first direction X, and the other of the common signal line 120 and the data signal line 117 is disposed at the other side of the pixel unit in the first direction X. For example, the common signal line 120 is disposed on the left side of the pixel unit in the first direction X, and the data signal line 117 is disposed on the right side of the pixel unit in the first direction X.

(4) Forming a pixel electrode pattern. Forming the pixel electrode pattern includes: on the substrate 100 on which the foregoing pattern is formed, a first transparent conductive film is deposited, and a pixel electrode 102 pattern is formed through a patterning process, as shown in fig. 10 and 11. The pixel electrode 102 is connected to the second pole 106. The pixel electrode 102 is a plate electrode 118. The pixel electrode 102 is provided on a common signal line 120 and a data signal line 117 which connect the same pixel unit.

(5) And forming a via hole pattern. Forming the via pattern includes: a second insulating film is deposited on the substrate 100 on which the pattern is formed, and a via hole pattern is formed after a patterning process. The via hole pattern includes a first via hole K1 and a second via hole K2 exposing the common signal line 120, and the second insulating film forms the second insulating layer 107. Fig. 10 is a schematic structural view after a via hole pattern is formed according to an exemplary embodiment of the present invention, and fig. 11 is a cross-sectional view taken at a position a-a in fig. 10.

(6) A common electrode and a shield layer pattern are formed. Forming the common electrode and the shielding layer pattern includes: on the substrate 100 formed with the aforementioned pattern, a second transparent conductive film is deposited, and after a patterning process, as shown in fig. 6 and 7, a common electrode 108 and a shield layer 121 are patterned. The common electrode 108 is connected to the common signal line 120 through a first via hole. The shield layer 121 is connected to the common signal line 120 through a second via hole. The common electrode 108 is a slit electrode 119. The slit electrode 119 includes a first edge region 110 and a second edge region 111 disposed in the first direction X, and a third edge region 112 and a fourth edge region 113 disposed in the second direction Y, the first edge region 110 being adjacent to the common signal line 120, the second edge region 111 being adjacent to the data signal line 117, the first edge region 110, the second edge region 111, the third edge region 112, and the fourth edge region 113 enclosing a slit region 11, the slit region 11 including a first slit 114 having an end adjacent to the first edge region 110 and a second slit 115 having an end adjacent to the second edge region 111, the second slit 115 penetrating the second edge region 111, and in other exemplary embodiments, the first slit 114 penetrating the first edge region 110. The shielding layer 121 extends along the second direction Y and is spaced from the slit electrode 119 in the first direction X, an overlapping region exists between an orthogonal projection of the shielding layer 121 on the substrate 100 and the data signal line 117, that is, in the first direction X, a common signal line 120, the data signal line 117, and the shielding layer 121 are disposed between adjacent pixel units, the shielding layer 121 is connected to the common signal line 120 through a via hole, and an overlapping region exists between the orthogonal projection on the substrate 100 and the data signal line 117, where the overlapping region may be a region between two dotted lines on the shielding layer 121. The width of the overlapping region is equal to the width of the data signal line 117 in the first direction X, and the length of the overlapping region is greater than or equal to the length of the slit electrode 119 in the second direction Y.

In some exemplary embodiments, the first and second insulating

layers

103 and 107 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer 103 is referred to as a Gate Insulating (GI) layer, and the second insulating layer 107 is referred to as a Passivation (PVX) layer. The first metal thin film and the second metal thin film may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, or the like. The thin film of the active layer 104 may be formed of various materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, and polythiophene, and the array substrate 10 is suitable for a transistor manufactured based on Oxide technology, silicon technology, and organic technology. The first transparent conductive film and the second transparent conductive film may employ any one or more of metal oxides such as indium-doped tin oxide (ITO) and aluminum-doped zinc oxide (AZO).

As can be seen from the manufacturing process of the array substrate 10 according to the exemplary embodiment of the present invention, the first edge region 110 of the slit electrode 119 is communicated with the first slit 114 or the second edge region 111 is communicated with the second slit 115, so that electric fields in opposite directions are not generated between the first edge region 110 and the plate electrode 118 and between the second edge region 111 and the plate electrode 118 in the process of driving the liquid crystal 30 to deflect, the driving conditions of the first edge region 110 and the second edge region 111 are changed, and disclination lines caused by opposite deflection directions of the liquid crystal 30 are avoided. In addition, when the common electrode 108 is formed, the shielding layer 121 is synchronously formed, the shielding layer 121 is connected with the common signal line 120, so that the shielding layer 121 and the common electrode 108 are at the same electric potential, an overlapping area exists between the orthographic projection of the shielding layer 121 on the substrate 100 and the orthographic projection of the data signal line 117 on the substrate 100, the overlapping area covers the position of the data signal line 117 corresponding to the slit electrode 119, the data signal line 117 is shielded, the phenomenon that the deflection direction of the liquid crystal 30 is opposite to the normal deflection direction of the liquid crystal due to continuous voltage variation of the data signal line 117 and the generation of an electric field between the common electrode 108 is avoided, and the generation of disclination lines is further prevented.

The above-mentioned preparation process is only an illustration of the preparation process of the array substrate provided in the exemplary embodiment of the present invention, and the array substrates provided in other exemplary embodiments are not repeated. In addition, in the exemplary embodiment, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs, and the disclosure is not limited herein.

forming a common electrode on the side of the second insulating layer far away from the substrate, and further comprising: forming a shielding layer on one side of the second insulating layer far away from the substrate;

The embodiment of the invention also provides a display device, which comprises the array substrate 10 provided by the embodiment. The display device may include a cell phone, a television, a tablet computer, a notebook computer, or an e-book, etc.

In some exemplary embodiments, the display device further includes a color filter substrate disposed opposite to the cell, and a liquid crystal disposed between the array substrate and the color filter substrate. The color film substrate is provided with a plurality of color film units and a black matrix arranged between the color film units. The color film unit corresponds to the position of the pixel electrode.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An array substrate, comprising: the pixel unit comprises a plate electrode and a slit electrode arranged on one side of the plate electrode far away from the substrate, the slit electrode corresponds to the plate electrode in position, the slit electrode comprises a first edge area and a second edge area arranged in the first direction, and a third edge area and a fourth edge area arranged in the second direction, and the first edge area, the second edge area, the third edge area and the fourth edge area enclose a slit area, the slit region includes a first slit having an end portion adjacent to the first edge region and a second slit having an end portion adjacent to the second edge region, the first slit penetrating the first edge region or the second slit penetrating the second edge region.

2. The array substrate of claim 1, wherein: the slit region comprises a first slit region and a second slit region which are arranged along the second direction, the first slit region and the second slit region respectively comprise a plurality of first slits and a plurality of second slits which are arranged in parallel, and the extending direction of the slits of the first slit region is intersected with the extending direction of the slits of the second slit region.

3. The array substrate of claim 2, wherein: the slits of the first slit region and the second slit region are symmetrically arranged with respect to a center line of the slit electrode in the second direction.

4. The array substrate of claim 1, wherein: the slit electrode is a common electrode configured to provide a common voltage signal, and the plate electrode is configured to provide a pixel electrode of a pixel voltage signal.

5. The array substrate of claim 4, wherein: the array substrate further comprises a shielding layer, the shielding layer is located far away from the data signal line on one side of the base, the shielding layer is connected with a public signal line connected with the public electrode, an overlapping region exists between an orthographic projection of the shielding layer on the base and an orthographic projection of the data signal line on the base, the shielding layer is arranged to shield the data signal line, and the data signal line and the slit electrodes are prevented from forming an electric field.

6. The array substrate of claim 5, wherein: the data signal lines include a first data signal line positioned at one side of the pixel unit in the first direction and a second data signal line positioned at the other side of the pixel unit in the first direction, and the first edge region is adjacent to the first data signal line;

the second slit penetrates through the second edge region, an overlapping region exists between the orthographic projection of the first edge region on the substrate and the orthographic projection of the first data signal line on the substrate, and the shielding layer is arranged in a region corresponding to the overlapping region of the first edge region; or the like, or a combination thereof,

the first slit penetrates through the first edge area, an overlapping area exists between the orthographic projection of the second edge area on the substrate and the orthographic projection of the second data signal line on the substrate, and the shielding layer is arranged in an area corresponding to the overlapping area of the second edge area.

7. The array substrate of claim 5, wherein: the shielding layer extends along the second direction and is spaced from the slit electrode in the first direction.

8. The array substrate of claim 7, wherein: the shielding layer and the slit electrode are arranged on the same layer.

9. The array substrate according to any one of claims 5-8, wherein: in the first direction, a width of the overlap region is equal to a width of the data signal line, and in the second direction, a length of the overlap region is greater than or equal to a length of the slit electrode.

10. The array substrate according to any one of claims 5-8, wherein: the common signal line and the scanning signal line are arranged in the same layer; or, the common signal line and the data signal line are arranged in the same layer.

11. A display device comprising the array substrate according to any one of claims 1 to 10.

12. A preparation method of an array substrate is characterized by comprising the following steps: forming a plurality of scanning signal lines and a plurality of data signal lines and a plurality of pixel units defined by the scanning signal lines and the data signal lines crossing each other on a substrate, the scanning signal lines extending in a first direction and spaced apart in a second direction, the data signal lines extending in the second direction and spaced apart in the first direction, the first direction and the second direction crossing each other, the pixel units including plate electrodes and slit electrodes disposed on sides of the plate electrodes away from the substrate, the slit electrodes corresponding to the plate electrodes in position, the slit electrodes including first and second edge regions disposed in the first direction and third and fourth edge regions disposed in the second direction, the first, second, third and fourth edge regions enclosing a slit region, the slit region includes a first slit having an end portion adjacent to the first edge region and a second slit having an end portion adjacent to the second edge region, the first slit penetrating the first edge region or the second slit penetrating the second edge region.

13. The method of claim 12, wherein forming pixel cells defined by a plurality of scan signal lines and a plurality of data signal lines and crossing the plurality of scan signal lines and the plurality of data signal lines on a substrate comprises:

forming a first insulating layer on one side of the gate metal layer, which is far away from the substrate;

forming a second insulating layer on one side of the pixel electrode, which is far away from the substrate, wherein a first through hole for exposing the common signal line is formed in the second insulating layer;

forming a common electrode on one side of the second insulating layer, which is far away from the substrate, wherein the common electrode is a slit electrode and is connected with the common signal line through the first via hole;

wherein, form the second insulating layer on one side of the said pixel electrode far away from said basement, also include:

forming a common electrode on one side of the second insulating layer far away from the substrate, and further comprising: forming a shielding layer on one side of the second insulating layer far away from the substrate;