CN112583400B

CN112583400B - Low-current switching circuit from starting current generation to shutdown mode

Info

Publication number: CN112583400B
Application number: CN201910932267.7A
Authority: CN
Inventors: 邹臣
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2022-10-21
Anticipated expiration: 2039-09-29
Also published as: CN112583400A

Abstract

A starting current is generated to a small current switching circuit in a turn-off mode, different starting reference currents are formed through single or series combination of double starting resistors, the turn-off current in the turn-off mode can be small, and therefore safety of starting and turning-off of a chip circuit is facilitated.

Description

Low-current switching circuit from starting current generation to shutdown mode

Technical Field

The invention relates to a current switching technology in a chip circuit, in particular to a small current switching circuit from starting current generation to a shutdown mode.

Background

In a chip circuit, there are always cases of frequent start-up and shut-down. However, in the shutdown mode of the circuit in the prior art, the shutdown current is generally not too small, but the shutdown current is very small, which may cause the circuit to be complicated or require special process support. The inventor believes that, for a chip circuit, especially for a high-voltage product therein, providing a start reference current generation circuit with small current switching for a subsequent circuit to operate (the subsequent circuit can operate because of the start current), and the structure is simple and easy to implement, which is undoubtedly a contribution to the prior art. If different starting reference currents are formed by single or series combination of the double starting resistors, the turn-off current in the turn-off mode can be small, and therefore the safety of starting and turning off of a chip circuit is facilitated. In view of the above, the present inventors have completed the present invention.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides the low-current switching circuit from the generation of the starting current to the shutdown mode, different starting reference currents are formed by the independent or series combination of the double starting resistors, so that the shutdown current in the shutdown mode can be very small, and the safety of the startup and shutdown of a chip circuit is facilitated.

The technical scheme of the invention is as follows:

the small current switching circuit is characterized by comprising a reference current output end, wherein the reference current output end is connected with a drain electrode of a first PMOS (P-channel metal oxide semiconductor) tube, a source electrode of the first PMOS tube is connected with a power voltage end, a grid electrode of the first PMOS tube is connected with a drain electrode of a second PMOS tube after being interconnected, the source electrode of the second PMOS tube is connected with the power voltage end, a drain electrode of the second PMOS tube is connected with a drain electrode of a fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with a starting voltage node, the starting voltage node is connected with a grounding end through a first starting resistor and a second starting resistor which are connected in series, an intermediate node between the first starting resistor and the second starting resistor is connected with a drain electrode of a sixth NMOS tube, the grid electrode of the sixth NMOS tube is connected with an enabling end, and the source electrode of the sixth NMOS tube is connected with the grounding end.

When the enable end is at a high level, dividing the voltage value of the starting voltage node by the resistance value of the first starting resistor to obtain a first starting reference current; when the enable end is at a low level, dividing the voltage value of the starting voltage node by the sum of the resistance values of the first starting resistor and the second starting resistor to obtain a second starting reference current; the first start-up reference current is greater than the second start-up reference current.

The starting voltage node is connected with a grid electrode of a fifth NMOS tube, a source electrode of the fifth NMOS tube is connected with a grounding end, a drain electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube and one end of a third resistor, the other end of the third resistor is connected with the source electrode of the third NMOS tube, and the drain electrode of the third NMOS tube is connected with the power supply voltage end.

The third NMOS tube is a depletion type NMOS tube.

The fourth NMOS tube is an LDMOS tube.

The invention has the following technical effects: according to the low-current switching circuit from starting current generation to the shutdown mode, due to the fact that different starting reference currents are formed through single or series combination of the double starting resistors, the shutdown current in the shutdown mode can be small, and therefore safety of starting and shutdown of a chip circuit is facilitated.

Drawings

FIG. 1 is a schematic diagram of a low current switching circuit for generating a start-up current to an off mode according to the present invention.

The reference numbers are listed below: VCC-supply voltage or supply voltage terminal; EN-enable terminal; GND-ground; ib-generated reference current or reference current output (Ib is generated by mirroring the Isb through the mirroring tubes M1 and M2); isb-starting reference current; is-Start Current; rst1 — first start-up resistance (by which a large start-up reference current Isb is generated alone in combination with the gate-source voltage Vgs of M5, e.g., not less than 100nA, when the enable terminal EN is high, M6 is on); rst 2-a second start-up resistor (which, in series combination with Rst1, produces a small start-up reference current Isb, when the enable EN is low, M6 is off); r3 — third resistance (which produces the activation current Is by combination with M3); vgs-a gate-source voltage or start voltage node of a fifth NMOS transistor; m1-a first PMOS tube; m2-a second PMOS tube; m3-a third NMOS transistor or a depletion NMOS transistor or a high-voltage depletion NMOS transistor (which Is combined with R3 to generate a start-up current Is); m4-fourth NMOS tube or high voltage resistant LDMOS (Laterally Diffused Metal Oxide Semiconductor) tube (other high voltage resistant MOS tubes can also be adopted); m5-a fifth NMOS tube; m6-sixth NMOS transistor.

Detailed Description

The invention is described below with reference to the accompanying drawing (fig. 1).

FIG. 1 is a schematic diagram of a low current switching circuit for generating a start-up current to an off mode according to the present invention. As shown in fig. 1, a low current switching circuit from generation of a start current to an off mode includes a reference current output terminal Ib, the reference current output terminal Ib is connected to a drain of a first PMOS transistor M1, a source of the first PMOS transistor M1 is connected to a power voltage terminal VCC, a gate of the first PMOS transistor M1 and a gate of a second PMOS transistor M2 are connected to each other and then to a drain of the second PMOS transistor M2, a source of the second PMOS transistor M2 is connected to the power voltage terminal VCC, a drain of the second PMOS transistor M2 is connected to a drain of a fourth NMOS transistor M4, a source of the fourth NMOS transistor M4 is connected to a start voltage node Vgs, the start voltage node Vgs is connected to a ground terminal GND through a first start resistor Rst1 and a second start resistor Rst2 connected in series, an intermediate node between the first start resistor Rst1 and the second start resistor Rst2 is connected to a drain of a sixth NMOS transistor M6, a gate of the sixth NMOS transistor M6 is connected to an enable terminal EN, and a source of the sixth NMOS transistor M6 is connected to the ground terminal GND. When the enable terminal EN is at a high level, dividing the voltage value of the starting voltage node Vgs by the resistance value of the first starting resistor Rst1 to obtain a first starting reference current Isb1; when the enable terminal EN is at a low level, dividing the voltage value of the start voltage node Vgs by the sum of the resistance values of the first start resistor Rst1 and the second start resistor Rst2 to obtain a second start reference current Isb2; the first start-up reference current Isb1 is greater than the second start-up reference current Isb2. The starting voltage node Vgs is connected with a grid electrode of a fifth NMOS tube M5, a source electrode of the fifth NMOS tube M5 is connected with a ground terminal GND, a drain electrode of the fifth NMOS tube M5 is respectively connected with a grid electrode of a fourth NMOS tube M4, a grid electrode of a third NMOS tube M3 and one end of a third resistor R3, the other end of the third resistor R3 is connected with a source electrode of the third NMOS tube M3, and a drain electrode of the third NMOS tube M3 is connected with a power supply voltage terminal VCC. The third NMOS tube is a depletion type NMOS tube. The fourth NMOS tube is an LDMOS tube.

As shown in fig. 1, VGS of M5 (i.e. the gate-source voltage of the fifth NMOS transistor) is divided by Rst1 to be the start reference current, and EN is high at this time, and this current is large, and is generally greater than 100nA for safe operation during circuit design. This current is mirrored at this level, and the total current of such a circuit is typically on the order of tens of microamps. When EN is low, i.e. enters an off mode, high-voltage products all need current to exist, for example, an enable circuit (enabling circuit), a logic control circuit and the like are established, and current is mirrored from the starting reference current (M1 and M2 form a mirror tube), which is the source of all current, and only if it becomes small, other needed current becomes small, so that the final off current is small. The off-current is typically required to be less than 1uA, with a typical value around 0.2 uA. Rst2 is added when the circuit is turned off, the starting current is equal to VGS divided by (Rst 1+ Rst 2), and the current is small and safe because the circuit is in the off mode, so that the 100nA current can be changed into the 10nA level. Maintenance work requires 10 such branches, with an overall off current between 0.1uA and 0.2 uA.

For the starting reference current generating circuit of the high-voltage product, the current is generated very simply, and a subsequent circuit can work only when the starting current exists. The circuit is simple in current generation, the current value is accurate, and the circuit is very suitable for starting. The top of the left side of fig. 1 uses a repetition device (repetition NMOS transistor), which is usually a large resistor, so that the number of resistors can be reduced, the layout area can be reduced, and the current of the whole circuit can be smaller without changing with the power supply voltage. The Depletion device has process support. In a word, the invention has simple structure and is easy to realize.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.

Claims

1. The small current switching circuit is characterized by comprising a reference current output end, wherein the reference current output end is connected with a drain electrode of a first PMOS (P-channel metal oxide semiconductor) tube, a source electrode of the first PMOS tube is connected with a power voltage end, a grid electrode of the first PMOS tube is connected with a drain electrode of a second PMOS tube after being interconnected, the source electrode of the second PMOS tube is connected with the power voltage end, a drain electrode of the second PMOS tube is connected with a drain electrode of a fourth NMOS (N-channel metal oxide semiconductor) tube, the source electrode of the fourth NMOS tube is connected with a starting voltage node, the starting voltage node is connected with a grounding end through a first starting resistor and a second starting resistor which are connected in series, an intermediate node between the first starting resistor and the second starting resistor is connected with a drain electrode of a sixth NMOS tube, a grid electrode of the sixth NMOS tube is connected with an enabling end, and a source electrode of the sixth NMOS tube is connected with the grounding end.

2. The small current switching circuit from the start-up current generation to the shutdown mode according to claim 1, wherein when the enable terminal is at a high level, the voltage value of the start-up voltage node is divided by the resistance value of the first start-up resistor to obtain a first start-up reference current; when the enable end is at a low level, dividing the voltage value of the starting voltage node by the sum of the resistance values of the first starting resistor and the second starting resistor to obtain a second starting reference current; the first start-up reference current is greater than the second start-up reference current.

3. The circuit of claim 1, wherein the starting voltage node is connected to a gate of a fifth NMOS transistor, a source of the fifth NMOS transistor is connected to a ground terminal, a drain of the fifth NMOS transistor is connected to the gate of the fourth NMOS transistor, the gate of a third NMOS transistor, and one end of a third resistor, respectively, another end of the third resistor is connected to the source of the third NMOS transistor, and a drain of the third NMOS transistor is connected to the supply voltage terminal.

4. The small current switching circuit from start-up current generation to off mode of claim 3, wherein said third NMOS transistor is a depletion type NMOS transistor.

5. The circuit of claim 1, wherein the fourth NMOS transistor is an LDMOS transistor.