CN112583287A

CN112583287A - Control unit of active bridge rectifier circuit and rectifier device

Info

Publication number: CN112583287A
Application number: CN202011504887.XA
Authority: CN
Inventors: 钟大兴; 兰勇
Original assignee: China Great Wall Technology Group Co ltd
Current assignee: China Great Wall Technology Group Co ltd
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2021-03-30

Abstract

The application relates to the technical field of circuits and provides a control unit of an active bridge rectifier circuit and a rectifier circuit. In the control unit of the active bridge rectifier circuit, the detection clamping circuit can input corresponding driving signals to the first driver according to the characteristics of various voltage signals when the voltage signals are input, the first driver can input accurate control signals to the corresponding driving end of the active bridge rectifier circuit respectively according to the received driving signals, and input corresponding driving signals to the second driver, so that the second driver can simultaneously input accurate control signals to the corresponding driving end of the active bridge rectifier circuit, all loops of the active bridge rectifier circuit can be orderly conducted under the control of the control unit, various accessed voltage signals are respectively and correspondingly rectified, the corresponding rectifying device can be suitable for scenes powered by various voltage signals, and the flexibility of the rectifying device is effectively improved.

Description

Control unit of active bridge rectifier circuit and rectifier device

Technical Field

The application belongs to the technical field of circuits, and particularly relates to a control unit of an active bridge rectifier circuit and a rectifier device.

Background

With the increasing requirement of the switching power supply on efficiency, the conventional diode rectification shown in fig. 1 has a bottleneck that limits the improvement of the power supply efficiency due to excessive forward conduction loss, and it has been desired to use MOSFETs (metal-oxide semiconductor field effect transistors) to replace conventional diodes for rectification to greatly reduce the forward conduction loss of the diodes, but since MOSFETs are used to replace conventional diodes for rectification, it is necessary to ensure that 4 MOSFETs can be turned on individually in time when the current flows in the forward direction and turned off individually in time when the current flows in the reverse direction, and only in this way, the conduction loss can be reduced to the maximum extent, and the phenomenon of common damage of two adjacent MOSFETs can be prevented, and the conventional control circuit generally needs to detect the polarity of the input voltage and increase the dead zone between two adjacent MOSFETs for control, the control mode can not ensure the safety and reliability of MOSFET control under the condition that alternating current input voltage generates various distortions (such as the distortion is triangular wave or square wave) and can not meet the requirement that a power supply can be compatible with alternating current input and direct current input in more and more practical application occasions such as the current telecommunication room, and the like.

In recent years, although the problem of overlong dead time of a control circuit is solved to a certain extent by an active bridge rectifier controller, the active bridge rectifier controller only supports a rectification application scene when alternating current is input, and is difficult to meet application scenes when other voltage signals such as direct current are input, so that the control circuit of the traditional active bridge rectifier circuit has limitations.

Disclosure of Invention

An object of the application is to provide a control unit and a rectifying device of an active bridge rectifier circuit, and the problem that the control circuit of the traditional active bridge rectifier circuit is limited is solved.

A first aspect of an embodiment of the present application provides a control unit of an active bridge rectifier circuit, including:

the detection clamping circuit is connected with the first driver; the detection clamping circuit inputs a first driving signal to the first driver when a first input end of the detection clamping circuit receives a first voltage signal and a second input end of the detection clamping circuit receives a second voltage signal, and inputs a second driving signal to the first driver when the first input end of the detection clamping circuit receives the second voltage signal and the second input end of the detection clamping circuit receives the first voltage signal; the first voltage signal and the second voltage signal are the same kind of voltage signals with opposite polarities;

the first driver is respectively connected with the first driving end of the active bridge rectifier circuit, the second driving end of the active bridge rectifier circuit and the second driver; the first driver outputs a high level signal to the first driving end when receiving the first driving signal, outputs a third driving signal to the second driver, outputs a high level signal to the second driving end when receiving the second driving signal, and outputs a fourth driving signal to the second driver;

the second driver is respectively connected with the third driving end of the active bridge rectifier circuit and the fourth driving end of the active bridge rectifier circuit; and the second driver outputs a high-level signal to the third driving end when receiving the third driving signal so as to enable the first loop of the active bridge rectifier circuit to be conducted, and outputs a high-level signal to the fourth driving end when receiving the fourth driving signal so as to enable the second loop of the active bridge rectifier circuit to be conducted.

In one embodiment, a first output terminal of the detection clamp is connected to a first input terminal of the first driver, and a second output terminal of the detection clamp is connected to a second input terminal of the first driver; when the first input end of the detection clamping circuit receives a first voltage signal and the second input end of the detection clamping circuit receives a second voltage signal, the detection clamping circuit outputs a high level signal to the first output end of the detection clamping circuit and outputs a low level signal to the second output end of the detection clamping circuit; when the first input end of the first voltage signal receives the second voltage signal and the second input end of the first voltage signal receives the first voltage signal, the first output end of the first voltage signal outputs a low level signal and the second output end of the first voltage signal outputs a high level signal; the first driving signal comprises a high level signal received by a first input end in the first driver and a low level signal received by a second input end in the first driver; the second driving signal comprises a low level signal received by a first input end and a high level signal received by a second input end in the first driver;

a first output end of the first driver is respectively connected with the first driving end and a first input end of the second driver, and a second output end of the first driver is respectively connected with the second driving end and a second input end of the second driver; the first driver outputs a high level signal at a first output end thereof and outputs a low level signal at a second output end thereof when receiving the high level signal at a first input end thereof and receiving the low level signal at a second input end thereof; when the first input end of the high-level signal receives a high-level signal and the second input end of the low-level signal receives a low-level signal, the first output end of the high-level signal outputs a high-level signal; the third driving signal comprises a high level signal received by a first input terminal in the second driver and a low level signal received by a second input terminal in the second driver; the fourth driving signal comprises a low level signal received by a first input terminal in the second driver and a high level signal received by a second input terminal in the second driver;

a first output end of the second driver is connected with the third driving end, and a second output end of the second driver is connected with the fourth driving end; the second driver outputs a high level signal to the third driving terminal and outputs a low level signal to the fourth driving terminal when the first input terminal of the second driver receives the high level signal and the second input terminal of the second driver receives the low level signal, so that the first loop is conducted, and outputs a high level signal to the fourth driving terminal and outputs a low level signal to the third driving terminal when the second input terminal of the second driver receives the high level signal and the first input terminal of the second driver receives the low level signal, so that the second loop is conducted.

In one embodiment, the detection clamping circuit comprises a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, a third resistor and a fourth resistor;

the D pole of the first MOS tube is a second input end of the detection clamping circuit, the G pole of the first MOS tube is connected with the G pole of the second MOS tube, the S pole of the first MOS tube is respectively connected with the second input end of the first driver and one end of the second resistor through the first resistor, and the other end of the second resistor is grounded; the D pole of the second MOS transistor is the first input end of the detection clamping circuit, the S pole of the second MOS transistor is connected to the first input end of the first driver and one end of the fourth resistor through the third resistor, respectively, and the other end of the fourth resistor is grounded.

As an embodiment, when the D pole of the second MOS tube receives a first voltage signal and the D pole of the first MOS tube receives a second voltage signal, the second MOS tube is conducted, the S-pole voltage of the second MOS tube is divided by the third resistor and the fourth resistor, the voltage received by the first input end of the first driver reaches a driving threshold value, the first output end of the first driver outputs high level signals to the first driving end and the first input end of the second driver respectively, the first output end of the second driver outputs a high level signal to the third driving end, the first MOS tube is cut off, a second output end of the first driver outputs a low-level signal to the second driving end and a second input end of the second driver respectively, and a second output end of the second driver outputs a low-level signal to the fourth driving end;

when the D pole of the second MOS tube receives the second voltage signal and the D pole of the first MOS tube receives the first voltage signal, the first MOS tube is conducted, the S-pole voltage of the first MOS tube is divided by the first resistor and the second resistor, the voltage received by the second input end of the first driver reaches the driving threshold, the second output end of the first driver outputs high-level signals to the second driving end and the second input end of the second driver respectively, the second output end of the second driver outputs a high level signal to the fourth driving end, the second MOS tube is cut off, the first output end of the first driver outputs low level signals to the first driving end and the first input end of the second driver respectively, and the first output end of the second driver outputs low level signals to the third driving end.

As an embodiment, the control unit of the active bridge rectifier circuit further comprises:

the first power supply is used for supplying power to the first MOS transistor, the second MOS transistor, the first driver and a first power supply end of the second driver;

a second power supply for powering a second power supply terminal of the second driver;

a third power supply for powering a third power supply end of the second driver.

Specifically, the control unit of the active bridge rectifier circuit further includes:

a first capacitor connected between the first power supply and ground; the first capacitor is a filter capacitor of the first power supply;

a second capacitor connected between the second power supply and the first input of the detection clamp; the second capacitor is a filter capacitor of the second power supply;

a third capacitor connected between the third power supply and the second input of the detection clamp; the third capacitor is a filter capacitor of the third power supply.

In one embodiment, the active bridge rectifier circuit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor; the first loop comprises a fourth MOS tube and a fifth MOS tube; the second loop comprises a third MOS tube and a sixth MOS tube;

the control unit of the active bridge rectifier circuit further comprises:

a D pole of the seventh MOS transistor is connected to the first input end of the first driver, an S pole of the seventh MOS transistor is grounded, and a G pole of the seventh MOS transistor is connected to the second driving end; the seventh MOS tube is used for preventing two adjacent MOS tubes belonging to different loops in the active bridge rectification circuit from being conducted with each other when the second output end of the first driver outputs a high level signal;

a D pole of the eighth MOS transistor is connected to the second input end of the first driver, an S pole of the eighth MOS transistor is grounded, and a G pole of the eighth MOS transistor is connected to the first driving end; and the eighth MOS tube is used for preventing two adjacent MOS tubes belonging to different loops in the active bridge rectification circuit from being mutually conducted when the first output end of the first driver outputs a high-level signal.

In one embodiment, when the first voltage signal is an ac positive half cycle signal, the second voltage signal is an ac negative half cycle signal; when the first voltage signal is a direct-current positive voltage signal, the second voltage signal is a direct-current negative voltage signal.

A second aspect of the embodiments of the present application provides a rectifying device, including the active bridge rectifier circuit and the control unit of the active bridge rectifier circuit according to any one of the embodiments.

In one embodiment, the active bridge rectifier circuit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a fourth capacitor and a fifth resistor;

the S pole of the third MOS tube is respectively connected with the second input end of the detection clamping circuit and the D pole of the fifth MOS tube, the G pole of the third MOS tube is connected with the fourth driving end, and the D pole of the third MOS tube is connected with the D pole of the fourth MOS tube;

the S pole of the fourth MOS tube is respectively connected with the first input end of the detection clamping circuit and the D pole of the sixth MOS tube, the G pole of the fourth MOS tube is connected with the third driving end, and the D pole of the fourth MOS tube is respectively connected with the S pole of the sixth MOS tube through the fourth capacitor and the fifth resistor;

the G pole of the fifth MOS tube is connected with the first driving end, and the S pole of the fifth MOS tube is respectively connected with the S pole of the sixth MOS tube and the ground end;

and the G pole of the sixth MOS tube is connected with the second driving end.

The invention provides a control unit and a rectifying device of an active bridge rectifying circuit, wherein a first input end of a detection clamping circuit is adopted to receive one voltage signal (such as a first voltage signal) of a class of voltage signals, a second input end of the detection clamping circuit is adopted to receive the other voltage signal (such as a second voltage signal with the polarity opposite to that of the first voltage signal) of the class of voltage signals, a first driving signal or a second driving signal is input into a first driver, so that the first driver can input a third driving signal or a fourth driving signal into a second driver according to the signals received by the input ends of the detection clamping circuit, a high level signal is input into a first driving end of the active bridge rectifying circuit when the third driving signal is input into the second driver, and a high level signal is input into a second driving end of the active bridge rectifying circuit when the fourth driving signal is input into the second driver, correspondingly, when the second driver receives the third driving signal, a high level signal is input to the third driving end of the active bridge rectifier circuit, so that the first loop of the active bridge rectifier circuit is conducted, and when the second driver receives the fourth driving signal, a high level signal is input to the fourth driving end of the active bridge rectifier circuit, so that the second loop of the active bridge rectifier circuit is conducted.

Drawings

FIG. 1 is a schematic diagram of a conventional diode bridge rectifier circuit;

FIG. 2 is a schematic diagram of a first circuit of an active bridge rectifier circuit;

FIG. 3 is a schematic diagram of a second loop of an active bridge rectifier circuit;

fig. 4 is a schematic diagram of a control unit structure of an active bridge rectifier circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a control unit of an active bridge rectifier circuit according to another embodiment of the present application;

fig. 6 is a schematic diagram of a control unit of an active bridge rectifier circuit according to another embodiment of the present application;

fig. 7 is a schematic diagram of a control unit of an active bridge rectifier circuit according to another embodiment of the present application;

fig. 8 is a schematic diagram of a control unit of an active bridge rectifier circuit according to another embodiment of the present application;

fig. 9 is a schematic structural diagram of a control unit of an active bridge rectifier circuit according to another embodiment of the present application.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Referring to fig. 2 and 3, the active bridge rectifier circuit includes a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, a fourth capacitor C, and a fifth resistor RL, where AC _ L is a first input terminal and AC _ N is a second input terminal. Referring to fig. 2, the first input terminal AC _ L, the fourth MOS transistor Q4, the fifth resistor RL, the fifth MOS transistor Q5, and the second input terminal AC _ N form a first loop of the active bridge rectifier circuit, when an AC positive half cycle signal is input to the first input terminal, and when an AC negative half cycle signal is input to the second input terminal, the first loop is turned on, that is, the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are turned on, and the third MOS transistor Q3 and the sixth MOS transistor Q6 are turned off. Referring to fig. 3, the second input terminal AC _ N, the third MOS transistor Q3, the fifth resistor RL, the sixth MOS transistor Q6 and the first input terminal AC _ L form a second loop, and when an AC negative half cycle signal is input to the first input terminal and an AC positive half cycle signal is input to the second input terminal, the second loop is turned on, that is, the third MOS transistor Q3 and the sixth MOS transistor Q6 are turned on, and the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are turned off. The traditional active bridge rectifier circuit usually only supports the rectification application occasion when alternating current is input, cannot meet the application occasion when the direct current input is compatible, and has limitation in application.

The problem to traditional active bridge rectifier circuit application has the limitation, the embodiment of this application provides a control unit of active bridge rectifier circuit on the one hand, above-mentioned active bridge rectifier circuit includes first return circuit and second return circuit, and set up first drive end, the second drive end, these four drive ends of third drive end and fourth drive end (being the drive signal input part of each MOS pipe in the active bridge rectifier circuit), in active bridge rectifier circuit's course of operation, if first drive end and third drive end receive high level signal simultaneously, first return circuit switches on, if second drive end and fourth drive end receive high level signal simultaneously, the second return circuit switches on.

Referring to fig. 4, the control unit of the active bridge rectifier circuit includes a detection clamp circuit 10, a first driver 20 and a second driver 30; the above-described detection clamp 10 is provided with a first input terminal and a second input terminal. The detection clamping circuit 10 is connected with a second driver 30 through a first driver 20, the first driver 20 is further connected with a first driving end and a second driving end of an active bridge rectification circuit 40 respectively, and the second driver 30 is connected with a third driving end and a fourth driving end of the active bridge rectification circuit respectively.

The detection clamp circuit 10 inputs a first driving signal to the first driver 20 when a first input terminal thereof receives a first voltage signal and a second input terminal thereof receives a second voltage signal; inputting a second driving signal to the first driver 10 when the first input terminal thereof receives the second voltage signal and the second input terminal thereof receives the first voltage signal; the first voltage signal and the second voltage signal are the same kind of voltage signals with opposite polarities.

The first driver 20 outputs a high level signal to the first driving terminal when receiving the first driving signal, and outputs a third driving signal to the second driver 30; outputs a high level signal to the second driving terminal when receiving the second driving signal, and outputs a fourth driving signal to the second driver 30.

The second driver 30 outputs a high level signal to the third driving end when receiving the third driving signal, at this time, the first driving end and the third driving end of the active bridge rectifier circuit respectively receive the high level signal, and the first loop is conducted; and when the fourth driving signal is received, a high level signal is output to the fourth driving end, the second driving end and the fourth driving end of the active bridge rectifier circuit respectively receive the high level signal, and the second loop is conducted.

The voltage signals received by the first input terminal and the second input terminal of the detection clamp circuit 10 are the same type of voltage signals with opposite polarities (such as dc voltage signals or ac voltage signals), that is, the first voltage signal and the second voltage signal are the same type of voltage signals with opposite polarities, for example, if the first voltage signal is an ac positive half-cycle signal, the second voltage signal is an ac negative half-cycle signal, and if the first voltage signal is a dc positive voltage signal, the second voltage signal is a dc negative voltage signal.

In the present embodiment, the first input terminal of the detection clamp circuit 10 is used to receive one voltage signal (e.g. a first voltage signal) of a class of voltage signals, the second input terminal of the detection clamp circuit 10 is used to receive another voltage signal (e.g. a second voltage signal with a polarity opposite to that of the first voltage signal) of the class of voltage signals, the first driver 20 is input with the first driving signal or the second driving signal, so that the first driver 20 can input the third driving signal or the fourth driving signal to the second driver 30 according to the signals received by the respective input terminals of the detection clamp circuit 10, and input the high level signal to the first driving terminal of the active bridge rectifier circuit when the third driving signal is input to the second driver 30, and input the high level signal to the second driving terminal of the active bridge rectifier circuit when the fourth driving signal is input to the second driver 30, accordingly, when receiving a third driving signal, the second driver 30 inputs a high level signal to the third driving end of the active bridge rectifier circuit to make the first loop of the active bridge rectifier circuit 40 conducted, and when receiving a fourth driving signal, the second driver 30 inputs a high level signal to the fourth driving end of the active bridge rectifier circuit 40 to make the second loop of the active bridge rectifier circuit 40 conducted, so that the control unit of the active bridge rectifier circuit can respectively control the connected active bridge rectifier circuits when receiving various voltage signals, and the active bridge rectifier circuit can stably perform rectification operation when various voltage signals are supplied with power.

In one embodiment, referring to fig. 5, the detection clamp circuit 10 further provides a first output terminal and a second output terminal, the first driver 20 provides a first input terminal INA, a second input terminal INB, a first output terminal OUTA and a second output terminal OUTB, respectively, and the second driver 30 provides a first input terminal INA, a second input terminal INB, a first output terminal OUTA and a second output terminal OUTB, respectively; a first output end of the detection clamp circuit 10 is connected to a first input end INA of the first driver 20, and a second output end of the detection clamp circuit 10 is connected to a second input end INB of the first driver 20; a first output end OUTA of the first driver 20 is respectively connected with a first input end INA of the second driver 30 and a first driving end of the active bridge rectifier circuit 40, and a second output end OUTB of the first driver 20 is respectively connected with a second input end INB of the second driver 30 and a second driving end of the active bridge rectifier circuit 40; the first output terminal OUTA of the second driver 30 is connected to the third driving terminal of the active bridge rectifier circuit 40, and the second output terminal OUTB of the second driver 30 is connected to the fourth driving terminal of the active bridge rectifier circuit 40. The first driving signals include a high level signal received at a first input terminal INA of the first driver 20 and a low level signal received at a second input terminal INB of the first driver 20; the second driving signal includes a low level signal received at the first input terminal INA and a high level signal received at the second input terminal INB in the first driver 20; the third driving signal includes a high level signal received at the first input terminal INA in the second driver 30 and a low level signal received at the second input terminal INB in the second driver 30; the fourth driving signal includes a low level signal received at the first input terminal INA of the second driver 30 and a high level signal received at the second input terminal INB of the second driver 30.

As shown in fig. 5, when the first input terminal of the detection clamp circuit 10 receives the first voltage signal and the second input terminal thereof receives the second voltage signal, the detection clamp circuit outputs a high level signal to the first output terminal thereof and outputs a low level signal to the second output terminal thereof, and at this time, the first input terminal INA of the first driver 20 receives the high level signal and the second input terminal INB of the first driver 20 receives the low level signal; when the first input terminal of the detection clamp circuit 10 receives the second voltage signal and the second input terminal thereof receives the first voltage signal, the detection clamp circuit outputs a low level signal to the first output terminal thereof and outputs a high level signal to the second output terminal thereof, at this time, the first input terminal INA of the first driver 20 receives the low level signal, and the second input terminal INB of the first driver 20 receives the high level signal.

When the first input terminal INA of the first driver 20 receives a high level signal and the second input terminal INB thereof receives a low level signal, the first output terminal OUTA thereof outputs a high level signal and the second output terminal OUTB thereof outputs a low level signal, at this time, the first input terminal INA of the second driver 30 and the first driving terminal of the active bridge rectifier circuit 40 both receive a high level signal, and the second input terminal INB of the second driver 30 and the second driving terminal of the active bridge rectifier circuit 40 both receive a low level signal; when the first input terminal INA of the first driver 20 receives a low level signal and the second input terminal INB thereof receives a high level signal, the first driver outputs a low level signal to the first output terminal OUTA thereof and outputs a high level signal to the second output terminal OUTB, at this time, the first input terminal INA of the second driver 30 and the first driving terminal of the active bridge rectifier circuit 40 both receive a low level signal, and the second input terminal INB of the second driver 30 and the second driving terminal of the active bridge rectifier circuit 40 both receive a high level signal.

When the first input terminal INA of the second driver 30 receives the high level signal and the second input terminal INB receives the low level signal, the first output terminal OUTA of the second driver outputs the high level signal to the third driving terminal of the active bridge rectifier circuit 40, and the second output terminal OUTB of the second driver outputs the low level signal to the fourth driving terminal of the active bridge rectifier circuit 40, at this time, the first driving terminal and the third driving terminal of the active bridge rectifier circuit 40 receive the high level signal at the same time, and the second driving terminal and the fourth driving terminal receive the low level signal at the same time, so that the first circuit is conducted; when the second input terminal INB of the second driver 30 receives the high level signal and the first input terminal INA receives the low level signal, the second output terminal OUTB outputs the high level signal to the fourth driving terminal of the active bridge rectifier circuit 40, and the first output terminal OUTA outputs the low level signal to the third driving terminal of the active bridge rectifier circuit 40, at this time, the second driving terminal and the fourth driving terminal of the active bridge rectifier circuit 40 receive the high level signal at the same time, the first driving terminal and the third driving terminal receive the low level signal at the same time, and the second loop is turned on.

In this embodiment, the detection clamp circuit 10 further includes a first output terminal and a second output terminal, the first driver 20 includes a first input terminal INA, a second input terminal INB, a first output terminal OUTA and a second output terminal OUTB, the second driver 30 includes a first input terminal INA, a second input terminal INB, a first output terminal OUTA and a second output terminal OUTB, and can receive various types of voltage signals in order, so as to accurately control the active bridge rectifier circuit 40 according to the voltage signals received by the first input terminal and the second input terminal of the detection clamp circuit 10, thereby further improving the working stability of the active bridge rectifier circuit 40 when various types of voltage signals are supplied.

In one embodiment, referring to fig. 6, the detection clamp circuit 10 includes a first MOS transistor Q1, a second MOS transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4;

a D pole (drain) of the first MOS transistor Q1 is a second input end of the detection clamp circuit, a G pole (gate) of the first MOS transistor Q1 is connected to a G pole of the second MOS transistor Q2, an S pole (source) of the first MOS transistor Q1 is respectively connected to the second input end of the first driver 20 and one end of the second resistor R2 through the first resistor, and the other end of the second resistor R2 is grounded; the D pole of the second MOS transistor Q2 is the first input terminal of the detection clamp circuit 10, the S pole of the second MOS transistor Q2 is connected to the first input terminal of the first driver 20 and one end of the fourth resistor R4 through the third resistor R3, and the other end of the fourth resistor R4 is grounded.

In the application process, the input end (including the first input end and the second input end) of the detection clamping circuit 10 can be respectively connected to a mains supply signal (power frequency alternating current) and a direct current voltage signal. If the detection clamping circuit 10 is connected to a mains supply signal, a first input end of the detection clamping circuit is usually connected to a live wire of a mains supply and can be recorded as AC _ L, and a second input end of the detection clamping circuit is usually connected to a zero wire of the mains supply and can be recorded as AC _ N; if the detection clamping circuit is connected with a direct-current voltage signal, a first input end of the detection clamping circuit is normally connected with a positive end of the direct-current voltage and can be recorded as DC +, a second input end of the detection clamping circuit is normally connected with a negative end of the direct-current voltage and can be recorded as negative DC-; thus, in some example illustrations, the first input of the detection clamp 10 may be labeled as AC _ L (DC +) and the second input of the detection clamp 10 may be labeled as AC _ N (DC-).

Specifically, when the D pole of the second MOS transistor Q2 receives a first voltage signal and the D pole of the first MOS transistor Q1 receives a second voltage signal (e.g., an ac positive half cycle signal is input to the first input terminal of the detection clamp 10 and an ac negative half cycle signal is input to the second input terminal of the detection clamp 10, or a dc positive voltage signal is input to the first input terminal of the detection clamp 10 and a dc negative voltage signal is input to the second input terminal of the detection clamp 10), the second MOS transistor Q2 is turned on, the S-pole voltage of the second MOS transistor Q2 is divided by the third resistor R3 and the fourth resistor R4, the voltage received by the first input terminal of the first driver 20 reaches its driving threshold, the first output terminal OUTA of the first driver 20 outputs a high level signal to the first driving terminal of the active bridge rectifier circuit 40 and the first input terminal INA of the second driver 30, respectively, the first output terminal OUTA of the second driver 20 outputs a high level signal to the third driving terminal of the active bridge rectifier circuit 40, the first MOS transistor Q1 is turned off, the second output terminal OUTB of the first driver 20 outputs a low level signal to the second driving terminal of the active bridge rectifier circuit 40 and the second input terminal INB of the second driver 30, respectively, the second output terminal OUTB of the second driver 30 outputs a low level signal to the fourth driving terminal of the active bridge rectifier circuit 40, at this time, the first driving terminal and the third driving terminal of the active bridge rectifier circuit 40 receive the high level signal at the same time, the second driving terminal and the fourth driving terminal receive the low level signal at the same time, and the first loop is turned on;

when the D pole of the second MOS transistor Q2 receives the second voltage signal and the D pole of the first MOS transistor Q1 receives the first voltage signal (e.g., the ac negative half cycle signal is inputted to the first input terminal of the detection clamp 10 and the ac positive half cycle signal is inputted to the second input terminal of the detection clamp 10), or the dc negative voltage signal is inputted to the first input terminal of the detection clamp 10 and the dc positive voltage signal is inputted to the second input terminal of the detection clamp 10), the first MOS transistor Q1 is turned on, the voltage received by the second input terminal INB of the first driver 20 reaches the driving threshold after the S-voltage of the first MOS transistor Q1 is divided by the first resistor R1 and the second resistor R2, the second output terminal OUTB of the first driver 20 outputs a high level signal to the second driving terminal of the active bridge rectifier circuit 40 and the second input terminal INB of the second driver 30, the second output terminal OUTB of the second driver 30 outputs a high level signal to the fourth driving terminal of the active bridge rectifier circuit 40, the second MOS transistor Q2 is turned off, the first output terminal OUTA of the first driver 20 outputs a low level signal to the first driving terminal and the first input terminal of the second driver, respectively, the first output terminal OUTA of the second driver 30 outputs a low level signal to the third driving terminal of the active bridge rectifier circuit 40, at this time, the second driving terminal and the fourth driving terminal of the active bridge rectifier circuit 40 receive a high level signal simultaneously, the first driving terminal and the third driving terminal receive a low level signal simultaneously, and the second loop is turned on.

In particular, the above-mentioned drive threshold is determined by the performance characteristics of the first drive 2. The voltage division ratio between the third resistor R3 and the fourth resistor R4 can be determined according to a driving threshold value and dead time corresponding to two adjacent MOS tubes in the active bridge rectification circuit respectively; correspondingly, the voltage division ratio between the first resistor R1 and the second resistor R2 can also be determined according to the driving threshold and the dead time corresponding to two adjacent MOS transistors in the active bridge rectifier circuit.

In this embodiment, the first MOS transistor Q1, the second MOS transistor Q2, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 may form a detection clamp circuit for detecting the input voltage received by each input terminal in the clamp circuit 10, so that the detection clamp circuit 10 completes the detection of the input voltage through a simple device, and automatically clamps the highest voltage respectively received by the first input terminal and the second input terminal in the first driver 20, so that each input terminal of the first driver 20 is not affected by the level of the input voltage, and thus the corresponding control unit can effectively control the active bridge rectifier circuit 40.

As an embodiment, referring to fig. 7, the control unit of the active bridge rectifier circuit further includes a first power VCC1, a second power VCC2, and a third power VCC 3; in fig. 7, DR _ N _ L denotes a first driving terminal of the active bridge rectifier circuit 40, DR _ L denotes a second driving terminal of the active bridge rectifier circuit 40, DR _ L _ H denotes a third driving terminal of the active bridge rectifier circuit 40, DR _ N _ H denotes a fourth driving terminal of the active bridge rectifier circuit 40, AC _ L (DC +) denotes a first input terminal of the detection clamp circuit 10, and AC _ N (DC-) denotes a second input terminal of the detection clamp circuit 10.

The first power VCC1 is respectively connected to the G electrode of the first MOS transistor Q1, the G electrode of the second MOS transistor Q2, the power supply terminal VCC of the first driver 20, and the first power supply terminal VCC1 of the second driver 30, the first power VCC1 is respectively used for supplying power to the first MOS transistor Q1 and the second MOS transistor Q2, and the first power supply terminals VCC1 of the first driver 10 and the second driver 20; the second power supply VCC2 is connected to the second power supply terminal VCC2 of the second driver 30, and the second power supply VCC2 is used for supplying power to the second power supply terminal VDDA of the second driver 30; the third power supply VCC3 is connected to the third power supply terminal VDDB of the second driver 30, and the third power supply VCC3 is used to supply power to the third power supply terminal VDDB of the second driver 30.

In application, referring to fig. 7, the first power VCC1 may be further connected to a first enable terminal ENA of the first driver 10 and a second enable terminal ENB of the first driver 10, respectively.

In this embodiment, the first power VCC1, the second power VCC2, and the third power VCC3 are three independent power supplies, which can ensure that the related MOS transistor (e.g., the third MOS transistor or the fourth MOS transistor) in the active bridge rectifier circuit 40 has a voltage capable of driving the MOS transistor to be turned on and off under the condition of dc input, thereby ensuring that the related MOS transistor in the active bridge rectifier circuit 40 can be normally turned on when dc input occurs, and achieving the purpose of rectifying various voltage signals by the active bridge rectifier circuit 40.

Specifically, as shown in fig. 7, the control unit of the active bridge rectifier circuit further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3; the first capacitor C1 is connected between the first power VCC1 and ground; the first capacitor C1 is a filter capacitor of the first power source VCC 1. A second capacitor C2 is connected between the second power supply VCC2 and the first input AC _ L (DC +) of the detection clamp 10; the second capacitor C2 is a filter capacitor of the second power supply VCC 2; a third capacitor C3 is connected between a third power supply VCC3 and the second input AC _ N (DC-) of the detection clamp 10; the third capacitor C3 is a filter capacitor for the third power supply VCC 3.

Further, as shown in fig. 7, the first input terminal AC _ L (DC +) of the detection clamp circuit 10 may be further connected to one ground terminal GNDA of the second driver 30, and the second input terminal AC _ N (DC-) of the detection clamp circuit 10 may be further connected to the other ground terminal GNDB of the second driver 30, so that the second driver 30 can stably perform the driving operation.

The present embodiment sets filter capacitors for the first power VCC1, the second power VCC2, and the third power VCC3, respectively, so that the first power VCC1, the second power VCC2, and the third power VCC3 can continuously and stably supply power.

In one embodiment, as shown in fig. 2 and 3, the active bridge rectifier circuit may include a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, and a sixth MOS transistor Q6; the first loop of the active bridge rectifier circuit can be referred to fig. 2, and includes a fourth MOS transistor Q4 and a fifth MOS transistor Q5; the second loop of the active bridge rectifier circuit can be referred to as shown in fig. 3, and includes a third MOS transistor Q3 and a sixth MOS transistor Q6. In the practical application process, the active bridge rectifier circuit generally cannot control the common damage of two adjacent MOS transistors (for example, two adjacent MOS transistors, i.e., the third MOS transistor Q3 and the fifth MOS transistor Q5, and/or two adjacent MOS transistors, i.e., the fourth MOS transistor Q4 and the sixth MOS transistor Q6), and the application risk still exists during reliability tests, such as various alternating current input distortion and lightning stroke tests.

For the problem that the active bridge rectifier circuit has an application risk during a reliability test, referring to fig. 8, the control unit of the active bridge rectifier circuit provided in this embodiment may further include a seventh MOS transistor Q7 and an eighth MOS transistor Q8; the D pole of the seventh MOS transistor Q7 is connected to the first input terminal INA of the first driver 20, the S pole of the seventh MOS transistor Q7 is grounded, and the G pole of the seventh MOS transistor Q7 is connected to the second driving terminal DR _ L of the active bridge rectifier circuit; the seventh MOS transistor Q7 is configured to, when the second output terminal OUTB of the first driver 10 outputs a high level signal, prevent two adjacent MOS transistors in different loops in the active bridge rectifier circuit from being conducted with each other, for example, prevent the third MOS transistor Q3 and the fifth MOS transistor Q5 from being conducted with each other, prevent the fourth MOS transistor Q4 and the sixth MOS transistor Q6 from being conducted with each other, and so on;

the D pole of the eighth MOS transistor Q8 is connected to the second input terminal INB of the first driver 20, the S pole of the eighth MOS transistor Q8 is grounded, and the G pole of the eighth MOS transistor Q8 is connected to the first driving terminal DR _ N _ L of the active bridge rectifier circuit; the eighth MOS transistor Q8 is configured to, when the first output terminal OUTA of the first driver 20 outputs a high level signal, prevent two adjacent MOS transistors in different loops in the active bridge rectifier circuit from being conducted with each other, for example, prevent the third MOS transistor Q3 and the fifth MOS transistor Q5 from being conducted with each other, prevent the fourth MOS transistor Q4 and the sixth MOS transistor Q6 from being conducted with each other, and so on.

In this embodiment, since the eighth MOS transistor Q8 is turned on when the first output terminal OUTA of the first driver 20 outputs a high level, and the seventh MOS transistor Q7 is turned on when the second output terminal OUTB of the first driver 20 outputs a high level, the seventh MOS transistor Q7 and the eighth MOS transistor Q8 form a set of interlock circuit, which can avoid the situation that two adjacent MOS transistors (e.g., two adjacent MOS transistors, i.e., the third MOS transistor Q3 and the fifth MOS transistor Q5, and/or two adjacent MOS transistors, i.e., the fourth MOS transistor Q4 and the sixth MOS transistor Q6) in the active bridge rectifier circuit are turned on together, thereby further ensuring the safety and reliability of the active bridge rectifier circuit during operation.

In this embodiment, the voltage signals input to the first input terminal and the second input terminal of the detection clamp circuit at the same time are the same type of voltage signals (such as direct current voltage signals or alternating current voltage signals) with opposite polarities, and the control unit of the corresponding active bridge rectifier circuit can respectively perform corresponding control on various voltage signals received by the active bridge rectifier circuit, so that the active bridge rectifier circuit can stably perform rectification operation when various voltage signals are supplied with power, and the flexibility of the active bridge rectifier circuit is effectively improved.

Another aspect of the embodiments of the present application provides a rectifying device, which includes a plurality of control units of the active bridge rectifier circuit and the active bridge rectifier circuit described in any one of the embodiments.

The control unit of the active bridge rectifier circuit in the rectifier device has all the advantages brought by the technical solutions of the embodiments, so that the rectifier device has all the advantages brought by the technical solutions of the embodiments, and further description is omitted here.

Specifically, during the operation of the rectifying device, the control unit of the active bridge rectifier circuit may also refer to fig. 9, where the first input terminal of the detection clamp circuit is the first input terminal of the rectifying device and may be referred to as AC _ L (DC +), and the second input terminal of the detection clamp circuit 10 is the second input terminal of the rectifying device and may be referred to as AC _ N (DC-); DR _ N _ L denotes a first driving terminal of the active bridge rectifier circuit, DR _ L denotes a second driving terminal of the active bridge rectifier circuit, DR _ L _ H denotes a third driving terminal of the active bridge rectifier circuit, and DR _ N _ H denotes a fourth driving terminal of the active bridge rectifier circuit; PGND represents a ground terminal, S represents a source of a corresponding MOS transistor, G represents a gate of a corresponding MOS transistor, D represents a drain of a corresponding MOS transistor, IC1 represents a first driver, IC2 represents a second driver, and other ports of the first driver C1 and the second driver IC2 may be connected according to corresponding port characteristics during operation, for example, a ground terminal SGND of the first driver C1 may be grounded, a ground terminal GND1, a DISABLE terminal, and an SLOD terminal of the second driver IC2 may be grounded, a free pin terminal NC may be floating, and the like.

In one embodiment, referring to fig. 2 and 3, the active bridge rectifier circuit includes a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, a fourth capacitor C, and a fifth resistor RL. In the rectifying device provided by this embodiment, the active bridge rectifying circuit can perform corresponding rectifying operations in the AC power supply and DC power supply scenarios, where the first input terminal of the rectifying device can be denoted as AC _ L (DC +), and the second input terminal of the rectifying device can be denoted as AC _ N (DC-).

Specifically, in the active bridge rectifier circuit, the S pole of the third MOS transistor Q3 is connected to the second input terminal of the detection clamp circuit and the D pole of the fifth MOS transistor Q5, respectively, the G pole of the third MOS transistor Q3 is connected to the fourth driving terminal DR _ N _ H of the active bridge rectifier circuit, and the D pole of the third MOS transistor Q3 is connected to the D pole of the fourth MOS transistor Q4; the S pole of the fourth MOS tube Q4 is respectively connected with the first input end of the detection clamping circuit and the D pole of the sixth MOS tube Q6, the G pole of the fourth MOS tube Q4 is connected with the third driving end DR _ L _ H of the active bridge rectification circuit, and the D pole of the fourth MOS tube Q4 is respectively connected with the S pole of the sixth MOS tube Q6 through a fourth capacitor C and a fifth resistor RL; a G pole of the fifth MOS transistor Q5 is connected with a first driving end DR _ N _ L of the active bridge rectification circuit, and an S pole of the fifth MOS transistor Q5 is respectively connected with an S pole and a ground end of the sixth MOS transistor Q6; the G pole of the sixth MOS transistor Q6 is connected with the second driving end DR _ L _ L of the active bridge rectification circuit.

Referring to fig. 2, a first loop of the active bridge rectifier circuit is formed by the first input terminal, the fourth MOS transistor Q4, the fifth resistor RL, the fifth MOS transistor Q5 and the second input terminal, and when an ac positive half-cycle signal is input to the first input terminal of the rectifier device and an ac negative half-cycle signal is input to the second input terminal, the control unit shown in fig. 8 controls the first loop to be turned on, that is, the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are turned on, and the third MOS transistor Q3 and the sixth MOS transistor Q6 are turned off; accordingly, when the dc positive voltage signal is inputted to the first input terminal of the rectifying device, and the dc negative voltage signal is inputted to the second input terminal, the control unit shown in fig. 8 can also control the first loop to be conducted. Referring to fig. 3, a second loop is formed by the second input terminal, the third MOS transistor Q3, the fifth resistor RL, the sixth MOS transistor Q6 and the first input terminal, when an ac negative half-cycle signal is input to the first input terminal and an ac positive half-cycle signal is input to the second input terminal, the control unit shown in fig. 8 controls the second loop to be turned on, that is, the third MOS transistor Q3 and the sixth MOS transistor Q6 are turned on, the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are turned off, and accordingly, when a dc negative voltage signal is input to the first input terminal and a dc positive voltage signal is input to the second input terminal, the control unit shown in fig. 8 controls the second loop to be turned on. Therefore, the rectifying device can respectively execute rectifying operation under various voltage power supply scenes, and the flexibility is high.

The rectifying device provided by the embodiment has the following beneficial effects:

can solve the problem that the traditional active bridge type rectification controller can not support the rectification control application requirement of direct current input

The corresponding control unit controls the on and off of the MOS tube by sampling the input voltage threshold value, does not divide the input polarity, can reliably realize the accurate control of the rectification function under the conditions of AC voltage input (including various AC distortion waveforms) and DC voltage input, and simultaneously has the functions of adjustable dead zone and the interlocking of the on and off of the adjacent MOS tube;

further, according to the control principle of the embodiment, other existing rectification controllers (such as CMDRBR active bridge rectification controller) can be modified into an active bridge rectification controller compatible with the dc input, so as to implement accurate control of the corresponding active bridge rectification circuit in multiple application scenarios.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A control unit for an active bridge rectifier circuit, the control unit comprising:

2. The control unit for an active bridge rectifier circuit of claim 1 wherein a first output of said sense clamp is connected to a first input of said first driver and a second output of said sense clamp is connected to a second input of said first driver; when the first input end of the detection clamping circuit receives a first voltage signal and the second input end of the detection clamping circuit receives a second voltage signal, the detection clamping circuit outputs a high level signal to the first output end of the detection clamping circuit and outputs a low level signal to the second output end of the detection clamping circuit; when the first input end of the first voltage signal receives the second voltage signal and the second input end of the first voltage signal receives the first voltage signal, the first output end of the first voltage signal outputs a low level signal and the second output end of the first voltage signal outputs a high level signal; the first driving signal comprises a high level signal received by a first input end in the first driver and a low level signal received by a second input end in the first driver; the second driving signal comprises a low level signal received by a first input end and a high level signal received by a second input end in the first driver;

3. The control unit of an active bridge rectifier circuit of claim 2, wherein the detection clamp circuit comprises a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, a third resistor and a fourth resistor;

4. The control unit of the active bridge rectifier circuit of claim 3, wherein when the D electrode of the second MOS transistor receives a first voltage signal and the D electrode of the first MOS transistor receives a second voltage signal, the second MOS transistor is turned on, the S-pole voltage of the second MOS transistor is divided by the third resistor and the fourth resistor, the voltage received by the first input terminal of the first driver reaches a driving threshold, the first output terminal of the first driver outputs a high-level signal to the first driving terminal and the first input terminal of the second driver, the first output terminal of the second driver outputs a high-level signal to the third driving terminal, the first MOS transistor is turned off, and the second output terminal of the first driver outputs a low-level signal to the second driving terminal and the second input terminal of the second driver, a second output end of the second driver outputs a low-level signal to the fourth driving end;

5. The control unit for an active bridge rectifier circuit of claim 3 further comprising:

6. The control unit for an active bridge rectifier circuit of claim 5, further comprising:

7. The control unit of the active bridge rectifier circuit according to claim 2, wherein the active bridge rectifier circuit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor; the first loop comprises a fourth MOS tube and a fifth MOS tube; the second loop comprises a third MOS tube and a sixth MOS tube;

the control unit of the active bridge rectifier circuit further comprises:

8. The control unit of an active bridge rectifier circuit according to any one of claims 1 to 7, wherein when said first voltage signal is an AC positive half cycle signal, said second voltage signal is an AC negative half cycle signal; when the first voltage signal is a direct-current positive voltage signal, the second voltage signal is a direct-current negative voltage signal.

9. A rectifying apparatus, characterized by comprising a plurality of control units of an active bridge rectifier circuit according to any one of claims 1 to 8 and an active bridge rectifier circuit.

10. The rectifying device of an active bridge rectifier circuit according to claim 9, wherein said active bridge rectifier circuit comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a fourth capacitor, and a fifth resistor;

and the G pole of the sixth MOS tube is connected with the second driving end.