CN112583243B

CN112583243B - Hardware current limiting method and device for frequency converter and storage medium

Info

Publication number: CN112583243B
Application number: CN202011397963.1A
Authority: CN
Inventors: 吴伟华; 崔海现; 刘国鹰
Original assignee: Jiaxing Dannahe Electronic Technology Co ltd
Current assignee: Jiaxing Dannahe Electronic Technology Co ltd
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2022-02-18
Anticipated expiration: 2040-12-04
Also published as: CN113964797B; CN113964797A; CN112583243A

Abstract

The invention provides a hardware current limiting method and device for a frequency converter and a storage medium, and belongs to the technical field of hardware current limiting. The method solves the problems of inaccurate current flow of the existing hardware and the like. The hardware current limiting method comprises the following steps: a) collecting three-phase output current of a frequency converter, and judging whether the three-phase output current reaches or exceeds a hardware current-limiting threshold value; b) if the three-phase output current reaches or exceeds a hardware current-limiting threshold value, detecting the current output IGBT state; c) judging whether the current motor running state is in an electric state or a power generation state; d) outputting a corresponding frequency converter state to enable the three-phase output current to fall back according to a current sampling configuration mode adopted by the current frequency converter; e) and when the current limiting state reaches or exceeds the hardware current limiting threshold value, timing the current limiting state, obtaining the duration time of the hardware current limiting state, and if the duration time of the hardware current limiting state reaches a preset threshold value, switching off all the IGBT outputs of the frequency converters, and reporting the hardware current limiting fault. The invention has the advantages of accurate current limiting and the like.

Description

Hardware current limiting method and device for frequency converter and storage medium

Technical Field

The invention belongs to the technical field of hardware current limiting, and particularly relates to a hardware current limiting method and device for a frequency converter and a storage medium.

Background

When the inverter drives the motor, when the motor load is too large, the current may exceed the current tolerance of the IGBT in the inverter, resulting in a risk of damage to the inverter. For the situation, the frequency converter generally adopts an overcurrent protection method, and once the output current of the frequency converter is detected to exceed a certain limit value, the frequency converter can directly block all IGBT driving signals to play a role in blocking the output current of the frequency converter, so that the frequency converter is protected. However, in many cases, the occurrence of the overcurrent is accidental, the duration is usually instantaneous, and if the IGBT is blocked by adopting the overcurrent fault method, the IGBT usually needs to be reset manually, and the inverter can be restarted to continue to operate, which increases the workload of the user operation.

Therefore, the general frequency converter can provide 2 methods to solve the condition, one is software current limiting, and the other is hardware current limiting, so that the probability of reporting overcurrent faults of the frequency converter can be reduced, and the smooth use of the frequency converter is guaranteed. Software current limiting is generally performed by a software adjustment method, but the adjustment of the software method requires a period, and the lag time is generally 1 PWM period. At this time, if the current fluctuation changes too fast, and the current detected is too large, the software current limit needs to be adjusted in the next PWM period, and the current is likely to continue to rise until the current fault threshold is exceeded, and at this time, the overcurrent protection fault is still likely to be activated. Therefore, hardware current limiting needs to be added on the basis of software current limiting. The hardware current limiting is to set a current limiting threshold value through hardware, when the output current of the sampled frequency converter exceeds the hardware current limiting threshold value, a hardware current limiting signal is generated, the signal can immediately adjust the IGBT driving output state, the output current of the frequency converter is limited, and the current falls back. Typically, the software current limit is set at 1.6 times the rated current and the hardware current limit is set at about 2 times the rated current (peak).

The current hardware current limiting mode mainly uses the traditional wave-by-wave current limiting mode, and the flow is briefly summarized as follows: the frequency converter samples output current, the output current is compared with a hardware current limiting threshold value to generate a current limiting protection signal, the current limiting protection signal blocks driving signals of all IGBTs in the current period to turn off all the IGBTs, and the current begins to fall back after the IGBTs are turned off. And automatically resetting normal PWM output in the next PWM period in the state of the IGBT of the frequency converter, continuously sampling output current, continuously outputting a normal PWM modulation signal to drive the IGBT if the current falls below an amplitude limiting value, and blocking all IGBTs again if the current does not fall below the amplitude limiting value. The purpose of current limiting is achieved by sequentially detecting and blocking each period, so that hardware blocking is also called wave-by-wave current limiting.

However, the conventional wave-by-wave current limiting method adopts a mode of turning off all IGBTs to limit the increase of current, and the voltage variation of the motor terminal before and after the IGBTs are turned off is large, which causes the problems of poor waveform of output current during the hardware current limiting period of the frequency converter, unstable rotating speed and noise during the current limiting of the motor, so that the patent CN 201611245744-a frequency converter and a current limiting method and system thereof provide an active short-circuit method based on carrier detection to achieve the hardware current limiting effect, and effectively improve the problems of the conventional hardware current limiting mode. However, also this method still has the following disadvantages: first, the method does not consider the problem of the current sensor and the operating quadrant of the frequency converter (the problem of the motor state quadrant or the generator state imagination), and under certain working conditions and hardware conditions, the system can not operate reliably. Second, the problem of switching loss is not considered, and the switching loss of the hardware current-limiting method is increased. Thirdly, the problem of sensor position installation is not considered, and the application has certain limitation.

Aiming at the defects of the two methods, the invention provides a novel hardware current limiting method for a frequency converter, which effectively solves the defects of the methods.

Disclosure of Invention

The present invention provides a method, an apparatus and a storage medium for limiting a current of a frequency converter.

The first object of the present invention can be achieved by the following technical solutions: a hardware current limiting method for a frequency converter is characterized by comprising the following steps: a) collecting three-phase output current of a frequency converter, and judging whether the three-phase output current reaches or exceeds a hardware current-limiting threshold value; b) if the three-phase output current reaches or exceeds a hardware current-limiting threshold value, detecting the current output IGBT state; c) judging whether the current motor running state is in an electric state or a power generation state; d) outputting a corresponding frequency converter state to enable the three-phase output current to fall back according to a current sampling configuration mode adopted by the current frequency converter; e) and when the current limiting state reaches or exceeds the hardware current limiting threshold value, timing the current limiting state, obtaining the duration time of the hardware current limiting state, and if the duration time of the hardware current limiting state reaches a preset threshold value, switching off all the IGBT outputs of the frequency converters, and reporting the hardware current limiting fault.

In the above hardware current limiting method for the frequency converter, the frequency converter is provided with a detection module, and the detection module is used for detecting the output state of the current output IGBT state.

In the above hardware current-limiting method for the frequency converter, the detection module includes a current sensor, the current sampling configuration mode is divided into a sampling configuration mode a and a sampling configuration mode B, the sampling configuration module B indicates that the three-phase current sensor is placed between the lower bridge arm IGBT and the dc negative bus, and the sampling configuration mode a indicates that the three-phase current sensor is placed on the ac output of the frequency converter.

In the above-mentioned hardware current-limiting method for the frequency converter, when the motor is in a power generation state, if the detected three-phase output current reaches or exceeds the hardware current-limiting threshold, the frequency converter does not consider the current sampling configuration mode and the current output state of the frequency converter, and finally all IGBTs are turned off by an output instruction to adjust the current of the frequency converter to fall back.

In the above-mentioned hardware current-limiting method for the frequency converter, when the motor operates in an electric state, and when it is detected that a three-phase output phase current reaches or exceeds a hardware current-limiting threshold value, and the frequency converter is in a sampling configuration mode B, the frequency converter outputs an instruction to turn on all the lower bridge arm IGBTs and turn off all the upper bridge arm IGBTs to adjust the frequency converter current to fall back, regardless of the current output state of the frequency converter.

In the above-mentioned hardware current-limiting method for the frequency converter, when the motor operates in the electric state and detects that the three-phase output phase current reaches or exceeds the hardware current-limiting threshold, the frequency converter needs to adjust the final output state according to the current output state to adjust the output current of the frequency converter, which is specifically as follows: and if the three-phase upper bridge arm IGBTs corresponding to the current output state are detected to be in the on state, outputting a command to turn off all the lower bridge arm IGBTs and turn on all the upper bridge arm IGBTs to adjust the current fallback, otherwise, outputting a command to turn on all the lower bridge arm IGBTs and turn off all the upper bridge arm IGBTs to adjust the current fallback.

In the above hardware current-limiting method for the frequency converter, the hardware current-limiting fault calculation strategy is as follows: the method comprises the steps that a given hardware current-limiting counter is used for timing duration of a hardware current-limiting state, the hardware current-limiting state of a frequency converter is detected once every fixed period T, when the frequency converter is detected to enter the hardware current-limiting state, the counter increments dt1 in an accumulating mode, when the frequency converter is detected to exit the hardware current-limiting state, the counter increments dt2 in an accumulating mode, and finally when the counter exceeds a preset threshold value N, hardware current-limiting fault protection of the frequency converter is triggered.

The second object of the present invention can be achieved by the following technical solutions: a hardware current limiting device for a frequency converter is characterized by comprising: the frequency converter inverter main circuit comprises a direct current bus capacitor Cbus, a power switch device IGBT and a current sensor; one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing a method of hardware current limiting for a frequency converter as described above.

The third object of the present invention can be achieved by the following technical solutions: a storage medium, in which a readable computer program is stored, the computer program being executable by a processor to perform the above-mentioned hardware current limiting method for a frequency converter.

Compared with the prior art, the invention has the advantage of accurate control.

Drawings

Fig. 1 is a flow chart of a hardware current limiting method for a frequency converter according to the present invention.

Fig. 2 is a flow diagram of a hardware current-limited output state strategy employed in the present invention.

Fig. 3 is a schematic structural diagram of a frequency converter inverter main circuit and a current sampling position configuration mode in the invention.

Detailed Description

The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.

As shown in fig. 1 to 3, a first embodiment of the present invention relates to a main inverter circuit that is mainly composed of a dc bus capacitor Cbus, power switching devices IGBT (T1 to T6), and a current sensor. Considering the cost and the power grade of the frequency converter comprehensively, current sensors in different forms can be adopted, and the current sensors can be placed at a current sampling position A or a current sampling position B to sample three-phase current of UVW output by the frequency converter, which is respectively called a sampling configuration mode A and a sampling configuration mode B.

The inverter main circuit of the frequency converter consists of 3-phase bridge arms, each bridge arm consists of an upper IGBT and a lower IGBT, and the output state of the corresponding bridge arm is '1' when the upper bridge arm IGBT is turned ON and the lower bridge arm IGBT is turned OFF; defining that an upper bridge arm IGBT is turned off, a lower bridge arm IGBT is turned on, and the output state of the corresponding bridge arm is '0'; when the upper bridge arm IGBT and the lower bridge arm IGBT are both turned off, the output state of the corresponding bridge arm is 'z', and the state that the upper bridge arm IGBT and the lower bridge arm IGBT are both turned on is not allowed, because the state can cause the direct connection of a positive direct current bus and a negative direct current bus. Taking U-phase as an example, the relationship between the output state of the U-phase bridge arm and the IGBT state of the corresponding bridge arm is shown in table 1.

T1	T4	U phase output state
			ON	OFF	1
OFF	ON	0
			OFF	OFF	z
ON	ON	Illegal state, forbidden

TABLE 1

When the frequency converter three-phase UVW outputs zzz, according to the above definition, it is called a free-stop state (FreeWheel). When a U-V-W outputs 000 or 111, it is called an active short circuit condition (ASC). When the maximum value of the three-phase current of the frequency converter reaches or exceeds the hardware current-limiting current threshold value of the frequency converter, the frequency converter enters a hardware current-limiting state, at the moment, the frequency converter should adjust 3-phase output, and the adjustment current falls back.

Generally, when the inverter output is in a free-standing state (zzz), the inverter current may be reduced by reversing the terminal voltage applied to the UVW by the inverter from the state voltage prior to output of zzz. When the frequency converter outputs an active short-circuit state (000 or 111), the terminal voltage applied to UVW by the frequency converter becomes 0, and the current of the frequency converter can also be reduced. Therefore, when the frequency converter is in overcurrent, three hardware current-limiting output states are available for adjusting the current to fall back: 000, 111 and zzz. The strategy of hardware current limiting finally focuses on which of the three states should be selected to regulate current drop-back.

Selecting which output state to perform hardware current limiting adjustment needs to consider the following principles:

1) when the hardware current limiting is in an output state, the current sensor can still correctly sample to obtain the maximum value of the output three-phase current. Therefore, even during the hardware current-limiting output period, if other more serious current problems (such as output short circuit, grounding and the like) occur, the frequency converter can monitor the current and further activate short circuit and grounding fault faults, and all IGBTs are turned off to protect the frequency converter.

2) When the hardware current-limiting output state is switched, the selected output state should ensure that the number (state turning times) of all IGBTs from on to off or from off to on is the least as much as possible, so as to reduce the switching loss of the frequency converter.

3) The output state adopted by the hardware current limiting can not cause other problems, such as self-excitation power generation of a motor, current oscillation and the like.

The hardware current-limiting output state strategy adopted by the invention is as follows.

The first step is as follows: and detecting the three-phase current value of the frequency converter, and judging whether the current of the current three-phase current reaches or exceeds a given hardware current-limiting threshold value. If all phases are below the hardware current limit threshold, there is no operation. Otherwise, the second step is entered.

The second step is that: and detecting whether the motor runs in a power-driven state or a power-generating state, and if the motor runs in the power-generating state, directly outputting a zzz state by the frequency converter UVW (all IGBTs are turned off). Otherwise, entering the third step.

The third step: and (4) determining whether the current sensor of the frequency converter is in a sampling configuration mode B, and if so, outputting a 000 state (all upper bridge IGBTs are turned off, and the lower bridge arm IGBT is turned on) by the UVW of the frequency converter. Otherwise, entering the fourth step.

The fourth step: and detecting the current output state of the frequency converter, if the three-phase upper bridge arm IGBTs corresponding to the current output state are detected to be in a conducting state, outputting 111 (all the lower bridge arm IGBTs are turned off, all the upper bridge arm IGBTs are turned on) to adjust the current to fall back, otherwise, outputting 000 (all the lower bridge arm IGBTs are turned on, all the upper bridge arm IGBTs are turned off) to adjust the current to fall back, and finally outputting the relation as shown in a table 2.

Current UVW output state	Hardware current limiting UVW output state
		000	000
100	000
		110	111
010	000
		011	111
001	000
		101	111
111	111

TABLE 2

The reasons and benefits of using the above strategy are specified below:

firstly, under the power generation state: if a certain phase current reaches or exceeds the hardware current limiting threshold value in the generator state, if the state is switched to an active short-circuit state (000 or 111), the active state is equivalent to short-circuit the output of the three-phase winding of the motor in consideration of the residual magnetism of the asynchronous motor. At this time, because the three-phase winding of the motor has a current loop, under the dragging of an external prime mover load, the asynchronous motor runs at the self-excited power generation state, so that the output current value cannot drop back smoothly (even the current may be increased). Therefore, for the reliable operation of the frequency converter, the three-phase winding is disconnected in a zzz output mode usually in a power generation state, so as to ensure that the current can smoothly fall back after the hardware current-limiting output state is adjusted.

Considering the electromotive state, the mounting position of the current sensor needs to be considered.

When the inverter main circuit adopts a mode B configured by current sampling positions, if a large current occurs, the inverter main circuit adopts an output zzz state to limit the current, and the inverter main circuit has the following disadvantages: the switching loss of zzz is relatively large; before underflow interrupt PWM reset comes, the risk that the maximum value of the output phase current cannot be correctly detected exists; the variation of the UVW output voltage is large. However, if the current limiting is performed in the output 111 state, there are the following disadvantages: the frequency converter cannot correctly monitor the phase current of the motor during the hardware current limiting period. Since the current of the phase in which the maximum current occurs may not flow through the current sensor under the lower bridge arm, the corresponding current is not sampled. At the moment, an output 000 state is adopted, which is equivalent to that the UVW winding is in short circuit through 3 IGBTs of a lower bridge arm, 3-phase current of the motor can flow through a sampling resistor under the bridge arm of the frequency converter, the frequency converter can ensure that the maximum value of the three-phase current is monitored during the hardware current-limiting output period, the current type fault of the frequency converter can be monitored and protected even during the hardware current-limiting output period, and the frequency converter is prevented from being damaged by more serious faults during the hardware current-limiting output period.

When the inverter main circuit adopts a sampling configuration mode A, the current sampling sensor is placed on the output UVW, so that the frequency converter can detect the maximum value of the three-phase current of the motor no matter the output of the motor is in any state. Therefore, one more output state can be selected in the output strategy, and only the reduction of the switching times needs to be considered. The corresponding state adjustment strategies and the number of required switching IGBTs (state switching times) under different hardware current limiting methods for the frequency converter are shown in the following table. As can be seen from the table, when the switching loss index is obtained by summing the switching losses generated in all the switching states, the most preferable method is the method, the switching loss index is 2 × 6 to 12, the next method is method a, the switching loss index is 3 × 8 to 24, and the worst method is B, because the worst case of the method requires 2 reversals per cycle, and the switching loss index is 48.

TABLE 3

Table 3 is explained as follows:

1) the method A is a traditional hardware wave-by-wave current limiting method through output zzz, and the method B refers to a hardware wave-by-wave current limiting strategy provided by a patent CN201611245744, a frequency converter and a current limiting method and a system thereof.

2) The switching times represent switching losses, the turn-on losses and the turn-off losses of the IGBTs are assumed to be the same, the corresponding loss index of one-time switching is 1, the switches are assumed to appear in one period, and the switching losses which possibly appear represent the performance index of the switching losses in a summing mode.

The differences between the method and the method A and the method B are as follows:

1) method a is the simplest to implement and requires the least resources (no need to detect PWM state, no need to detect motoring or generating state). The device is suitable for the electric state and the power generation state. However, the method a does not consider (is not optimal) the output voltage change rate before and after the hardware current-limiting output switching state, and does not consider (is not optimal) the switching times.

2) In the method B, a sensor position configuration mode is considered, and in the sampling configuration mode A, the situation that the phase current reaches the hardware current-limiting amplitude value and is not detected possibly occurs, and other over-current measures are needed to make up for the secondary shortage.

3) In the method B, the change rate of the voltage of the output end is considered, but the optimized switching times are not considered, and the switching loss is high. (reduce the switching frequency, be favorable to reducing the switching loss, just can reduce the converter temperature rise, and then the converter volume can be done for a short time, and then reduce cost).

4) The method B divides a symmetrical triangular carrier into 2 half periods, and carries out 2 times of detection and 2 times of adjustment. (can understand half-wave current-limiting, adjust and detect the number of times many, it is big to master control singlechip resource demand), this patent is that a symmetrical triangular carrier only examines 1 time, adjusts 1 time, and is little to master control singlechip resource demand.

5) The method B needs to detect the current up-counting or down-counting stage of the PWM symmetrical triangular wave, and the method detects the actual output UVW state or the output states of 6 PWM pins.

6) Method B distinguishes between sensor locations: only the current sampling position pattern a is considered, but the method B cannot be applied when the sampling arrangement pattern B appears.

7) Method B does not distinguish between motoring and generating states. Under the power generation state, under the action of residual magnetism, under the dragging of an external prime motor, if the hardware current limiting is carried out in a three-phase short circuit mode, the self-excitation power generation phenomenon of the asynchronous motor can be possibly caused, the smooth falling of the current cannot be realized, and the method B has defects in the aspect of reliability.

Aiming at the consideration of coping under the condition of long-time hardware current limiting, the method also provides a hardware current limiting fault protection method, which prevents the IGBT in the frequency converter from being damaged due to overheating or overload caused by repeated oscillation of the frequency converter near a hardware current limiting threshold value for a long time. The method has the idea that the hardware current-limiting state of the frequency converter is counted in an inverse time limit mode, the hardware current-limiting state of the frequency converter is detected once every fixed period T, when the frequency converter is detected to enter the hardware current-limiting state, the counter increments dt1, and when the frequency converter is detected to exit the hardware current-limiting state, the counter increments dt 2. And finally, when the counter exceeds a threshold value N, the duration of the hardware current limiting state is considered to be too long, the hardware current limiting fault of the frequency converter needs to be triggered, all IGBTs are turned off, and then the frequency converter can continue to operate after the frequency converter fault is reset, wherein preferably, T is 1ms, dt1 is 2, dt2 is 1, and N is 200, which is equivalent to that the allowable duration of the hardware current limiting state is allowed to be 100ms, and the hardware current limiting fault of the frequency converter needs to be triggered.

A second embodiment of the invention relates to a storage medium for storing a computer-readable program for causing a computer to perform some or all of the above method embodiments.

That is, those skilled in the art can understand that all or part of the steps in the method according to the above embodiments may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, etc.) or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.

Although a large number of terms are used here more, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.

Claims

1. A hardware current limiting method for a frequency converter is characterized by comprising the following steps:

a) collecting three-phase output current of a frequency converter, and judging whether the three-phase output current reaches or exceeds a hardware current-limiting threshold value;

b) if the three-phase output current reaches or exceeds a hardware current-limiting threshold value, detecting the current output IGBT state;

c) judging whether the current motor running state is in an electric state or a power generation state;

d) outputting a corresponding frequency converter state to enable the three-phase output current to fall back according to a current sampling configuration mode adopted by the current frequency converter;

e) timing the current limiting state when the current limiting state reaches or exceeds the hardware current limiting threshold value, obtaining the duration time of the hardware current limiting state, and if the duration time of the hardware current limiting state reaches the preset threshold value, turning off all the IGBT outputs of the frequency converters, and reporting the hardware current limiting fault;

the frequency converter is provided with a detection module, the detection module is used for detecting the output state of the current output IGBT state, the detection module comprises a current sensor, the current sampling configuration mode is divided into a sampling configuration mode A and a sampling configuration mode B, the sampling configuration mode B means that the position of the three-phase current sensor is placed between the lower bridge arm IGBT and the direct current negative bus, and the sampling configuration mode A means that the three-phase current sensor is placed on the alternating current output of the frequency converter.

2. The method as claimed in claim 1, wherein when the motor is in a power generation state, if the detected three-phase output current reaches or exceeds the hardware current limit threshold, the frequency converter does not consider the current sampling configuration mode and the current output state of the frequency converter, and finally all the IGBTs are turned off by outputting a command to adjust the frequency converter current to fall back.

3. The hardware current-limiting method for the frequency converter according to claim 1, wherein when the motor is in an electric state, and when it is detected that a three-phase output phase current reaches or exceeds a hardware current-limiting threshold value, and the frequency converter is in a sampling configuration mode B, the frequency converter outputs a command to turn on all lower bridge arm IGBTs and turn off all upper bridge arm IGBTs to adjust a frequency converter current to fall back, regardless of a current frequency converter output state.

4. The method of claim 1, wherein the hardware current-limiting fault calculation strategy is as follows: the method comprises the steps that a given hardware current-limiting counter is used for timing duration of a hardware current-limiting state, the hardware current-limiting state of a frequency converter is detected once every fixed period T, when the frequency converter is detected to enter the hardware current-limiting state, the counter increments dt1 in an accumulating mode, when the frequency converter is detected to exit the hardware current-limiting state, the counter increments dt2 in an accumulating mode, and finally when the counter exceeds a preset threshold value N, hardware current-limiting fault protection of the frequency converter is triggered.

5. A hardware current limiting apparatus for a frequency converter, comprising: the frequency converter inverter main circuit comprises a direct current bus capacitor Cbus, a power switch device IGBT and a current sensor; one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing a method of hardware current limiting for a frequency converter as claimed in any one of claims 1 to 4.

6. A storage medium, characterized in that a readable computer program is stored, which computer program is executable by a processor to perform a method for hardware current limiting for a frequency converter according to any of claims 1 to 4.