CN112582405A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN112582405A
CN112582405A CN202011052596.1A CN202011052596A CN112582405A CN 112582405 A CN112582405 A CN 112582405A CN 202011052596 A CN202011052596 A CN 202011052596A CN 112582405 A CN112582405 A CN 112582405A
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China
Prior art keywords
layer
source
contact
drain
disposed
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CN202011052596.1A
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Chinese (zh)
Inventor
林诗哲
黄柏瑜
王朝勋
赵高毅
王美匀
张峰瑜
林睿哲
林威戎
高承远
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/984,884 external-priority patent/US11532561B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112582405A publication Critical patent/CN112582405A/en
Pending legal-status Critical Current

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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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Abstract

Embodiments of the invention relate to semiconductor devices and methods of forming the same. An example interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first and second vias extend to and physically contact the first and second source/drain contacts, respectively. The first thickness of the first through hole is the same as the second thickness of the second through hole. The third via physically contacts the gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Description

Semiconductor device and method of forming the same
Technical Field
Embodiments of the invention relate to semiconductor devices and methods of forming the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs, each of which has smaller and more complex circuits than the previous generation. During IC evolution, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometry (i.e., the size and/or dimensions of IC components and/or the spacing between IC components) decreases. In general, scaling is limited only by the ability of lithography to define ever decreasing geometries of IC components. However, as reduced geometries are implemented to achieve ICs with faster operating speeds (e.g., by reducing the distance electrical signals propagate), resistance-capacitance (RC) delays have become a serious challenge, offsetting some of the advantages achieved by scaling and limiting further scaling of ICs. RC delay generally represents a delay that occurs in the speed of an electrical signal through an IC due to the product of resistance (R) (i.e., the material's ability to resist the flow of current) and capacitance (C) (i.e., the material's ability to store charge). Therefore, it is desirable to reduce resistance and capacitance to reduce RC delay and optimize performance of scaled ICs. Interconnects of ICs that physically and/or electrically connect IC components of the IC and/or IC components are particularly problematic in their contribution to RC delay. Accordingly, there is a need for improved interconnects of ICs and/or methods of fabricating interconnects.
Disclosure of Invention
An embodiment of the present invention provides a semiconductor device including: a first source/drain contact disposed in the dielectric layer, wherein the first source/drain contact physically contacts the first source/drain feature; a second source/drain contact disposed in the dielectric layer, wherein the second source/drain contact physically contacts a second source/drain feature; a first via having a first via layer configuration and disposed in the dielectric layer, wherein the first via extends into and physically contacts the first source/drain contact; a second via having a second via layer configuration and disposed in the dielectric layer, wherein the second via extends into and physically contacts the second source/drain contact, the second via layer configuration is different from the first via layer configuration, and a first thickness of the first via is the same as a second thickness of the second via.
Another embodiment of the present invention provides a semiconductor device including: a gate structure disposed over a substrate, wherein the gate structure is disposed between a first source/drain feature and a second source/drain feature; a first source/drain contact and a second source/drain contact disposed in a dielectric layer, wherein the first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature; and a first via, a second via, and a third via disposed in the dielectric layer, wherein: the first via physically contacts the first source/drain contact, the second via physically contacts the second source/drain contact, and the third via physically contacts the gate structure, the first via includes a first metal fill layer having a first sidewall physically contacting the dielectric layer, the second via includes a second metal fill layer having a second sidewall physically contacting the dielectric layer, and the third via includes a third metal fill layer disposed over a metal barrier layer, wherein the metal barrier layer is disposed between the third metal fill layer and the dielectric layer such that a third sidewall of the third metal fill layer does not physically contact the dielectric layer.
Yet another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a first source/drain contact and a second source/drain contact in the dielectric layer, wherein the first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature; forming a first via opening and a second via opening in the dielectric layer, wherein the first via opening exposes the first source/drain contact and the second via opening exposes the second source/drain contact; recessing the first source/drain contact to extend the first via opening and recessing the second source/drain contact to extend the second via opening; performing a bottom-up deposition process to form a first via body layer in the first via opening and a second via body layer in the second via opening, wherein a first thickness of the first via body layer is different than a second thickness of the second via body layer; forming a first via blocking layer over the first via body layer and the second via body layer; forming a third via body layer over the first via blocking layer; performing a planarization process to remove any of the third via body layer, the first via blocking layer, the second via body layer, and the first via body layer disposed over the top surface of the dielectric layer, thereby forming a first via having a third thickness and a first via layer configuration and a second via having the third thickness and a second via layer configuration different from the first via layer configuration; forming a third via opening in the dielectric layer exposing the gate structure; forming a second via blocking layer partially filling the third via opening; forming a fourth via body layer over the second via blocking layer, wherein the fourth via body layer fills a remaining portion of the third via opening; and performing a planarization process to remove any of the fourth via body layer and the second via blocking layer disposed over the top surface of the dielectric layer, thereby forming a third via having a third via layer configuration that is different from the first via layer configuration and the second via layer configuration.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1A and 1B illustrate a flow diagram of a method for fabricating portions of a multilevel interconnect structure in accordance with various aspects of the invention.
Fig. 2-6, 7A-11A, 7B-11B, 7C-11C, and 12-16 are partial schematic diagrams of portions or the entirety of an integrated circuit device at various stages of fabricating a multilayer interconnect structure, such as a method for fabricating the multilayer interconnect structure of the integrated circuit device of fig. 1A and 1B, according to some embodiments of the invention.
Fig. 17A-17C are partial schematic diagrams of a portion or an entirety of an integrated circuit device having a multi-level interconnect structure that may be fabricated by the methods of fig. 1A and 1B, according to other embodiments of the invention.
Detailed Description
The present invention relates generally to integrated circuit devices and, more particularly, to multilayer interconnect structures for integrated circuit devices.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Also, to facilitate describing the relationship between one component and another component of the invention, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "under," "upward," "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used. Spatially relative terms are intended to cover different orientations of the device including the features. Further, as will be understood by those of ordinary skill in the art, when values or ranges of values are described with "about", "approximately", etc., the terms are intended to encompass the values within a reasonable range, taking into account variations that inherently occur during manufacture. For example, a value or range of values encompasses a reasonable range including the stated value, such as within +/-10% of the stated value, based on known manufacturing tolerances associated with manufacturing components having the characteristics associated with the value. For example, a material layer having a thickness of "about 5 nm" may encompass a dimensional range from between 4.5nm to 5.5nm, where manufacturing tolerances associated with depositing the material layer are known to one of ordinary skill in the art to be +/-10%. Still further, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
As IC technology expands to technology nodes below 20nm, shrinking critical dimensions (e.g., gate length, gate pitch, fin pitch, etc.) at the device layer of an IC has resulted in a corresponding shrinking critical dimensions (e.g., via size, metal line size, via pitch, metal line pitch, etc.) of interconnects, which facilitates operation of the device layer. This presents unique challenges. For example, typically, vias to source/drain contacts (connected to source/drain features) and vias to gate structures have the same configuration and are fabricated using the same method-filling via openings in a dielectric layer with a metal fill layer disposed over a metal paste/barrier layer configured to enhance adhesion between the vias and the dielectric layer (e.g., the metal paste/barrier layer lines sidewalls of the via openings defined by the dielectric layer), reduce contact resistance and/or prevent diffusion of via constituents into the surrounding environment. As the via CD shrinks, the metal paste/barrier layer consumes more space in the via opening, thereby reducing the remaining portion of the via opening for the metal fill layer. This results in poor metal gap filling, where the metal fill layer cannot fill the remainder of the via opening without forming a gap (or void), which significantly increases contact resistance. One solution is to eliminate the metal paste/barrier layer and make the via hole free of the barrier. However, it has been observed that some vias (e.g., vias to gate structures) require metal paste/barrier layers to optimize the reduction of contact resistance, while other vias (such as vias to source/drain contacts) require the elimination of metal paste/barrier layers to optimize the reduction of contact resistance.
Accordingly, the present invention proposes hybrid via configurations to accommodate different via interface requirements. For example, the present invention proposes to fabricate vias (e.g., via at via zero (M0), via at the bottommost via level) at the same level of a multilayer interconnect (MLI) structure with different configurations/structures to optimize the reduction of contact resistance. In some embodiments, the vias to the gate structures include a metal paste/barrier layer, while the vias to the source/drain contacts do not include a metal paste/barrier layer. For vias to the source/drain contacts, the proposed via fabrication method includes forming a via opening in the dielectric layer exposing the source/drain contact, recessing the source/drain contact to extend the via opening, filling the extended via opening with a first metal fill material using a bottom-up deposition process, forming a metal paste/barrier layer over the first metal fill material (e.g., by a conformal deposition process), forming a second metal fill material over the metal paste/barrier layer (e.g., by a blanket deposition process), and performing a planarization process that removes any second metal fill material, metal paste/barrier layer, and/or first metal fill material disposed over the top surface of the dielectric layer. For vias to the gate structures, the proposed via fabrication method includes forming a via opening in the dielectric layer that exposes the gate structure, forming a second metal paste/barrier layer along sidewalls of the via opening defined by the dielectric layer and a bottom of the via opening defined by the gate structure (e.g., by a conformal deposition process), forming a third metal fill material over the second metal paste/barrier layer and filling a remaining portion of the via opening (e.g., by a blanket deposition process), and performing a planarization process that removes any second metal paste/barrier layer and/or third metal fill material disposed over a top surface of the dielectric layer. In some embodiments, the vias to the gate structures are formed before the vias to the source/drain contacts are formed. In some embodiments, the vias to the gate structures are formed after the vias to the source/drain contacts are formed.
Recessing the source/drain contacts increases the contact area between the vias and the source/drain contacts. Process variations in the bottom-up deposition process result in different heights of the first metallic fill material. For example, the first metallic fill material may completely fill the first via opening to the first source/drain contact, while the first metallic fill material may partially fill the second via opening to the second source/drain contact. In some embodiments, the first metallic fill material completely fills the first via opening and extends over the top surface of the dielectric layer to form a via rivet head. As the height of the via rivet head increases (defined between the topmost surface of the via rivet head and the top surface of the dielectric layer), internal stresses within the first metallic filler material increase, which may lead to cracks during continued growth of the first metallic filler material and/or during subsequent processing. In some embodiments, the bottom-up deposition process is adjusted to limit the height of the via rivet head to a predetermined height that may minimize internal stresses of the first metallic fill material. In some embodiments, a metal paste/barrier layer is formed over the first metal fill material prior to forming the second metal fill material (which is required to fill the remainder of the via opening that is partially filled by the first metal fill material) to reduce the internal stress of the first metal fill material and prevent cracking of the metal fill layer of the via. This method of fabrication results in some vias to the source/drain contacts having barrier-free interfaces and some vias to the source/drain contacts having partial barrier interfaces. Details of the proposed method for fabricating the vias and the resulting via structures and/or configurations are described herein.
Fig. 1A and 1B are a flow diagram of a method 10 for fabricating a portion of a multilayer interconnect structure for an integrated circuit device in accordance with various aspects of the present invention. The portion of the multilayer interconnect structure fabricated by method 10 may reduce the capacitance and/or resistance associated with the IC device, thereby reducing the associated RC delay. At block 20, the method 10 includes forming a first source/drain contact and a second source/drain contact in a dielectric layer. The first source/drain contact physically contacts the first source/drain feature. The second source/drain contact physically contacts the second source/drain feature. At block 30, the method 10 includes forming a first via opening and a second via opening in a dielectric layer. The first via opening exposes the first source/drain contact and the second via opening exposes the second source/drain contact. At block 40, the method 10 includes recessing the first source/drain contact to extend the first via opening and recessing the second source/drain contact to extend the second via opening. At block 50, a bottom-up deposition process is performed to form a first via body layer in the first via opening and a second via body layer in the second via opening. In some embodiments, the first thickness of the first via body layer is different (e.g., greater or less) than the second thickness of the second via body layer. In some embodiments, the first thickness of the first via body layer is the same as the second thickness of the second via body layer. At blocks 60 and 70, a first via barrier layer is formed over the first via body layer and the second via body layer, respectively, and a third via body layer is formed over the first via body layer.
At block 80, the method 10 includes performing a planarization process to remove any of the third via body layer, the first via blocking layer, the second via body layer, and the first via body layer disposed over the top surface of the dielectric layer, thereby forming a first via having a third thickness and a first via layer configuration, and a second via having a third thickness and a second via layer configuration different from the first via layer configuration. At blocks 90, 100, and 110, a third via opening exposing the gate structure is formed in the dielectric layer, a second via blocking layer is formed partially filling the third via opening, and a fourth via body layer is formed over the second via blocking layer, respectively. The fourth via body layer fills the remaining portion of the third via opening. At block 120, the method 10 includes performing a planarization process to remove any of the fourth via body layer and the second via blocking layer disposed over the top surface of the dielectric layer, thereby forming a third via having a third via layer configuration that is different from the first via layer configuration and the second via layer configuration. In some embodiments, the first via, the second via, and the third via are part of a bottommost via layer of the multilayer interconnect structure. In some embodiments, fabrication may proceed to form additional layers of the multilayer interconnect structure, such as respective wires located over and in physical contact with the first, second, and third vias. Additional processing is contemplated by the present invention. Additional steps may be provided before, during, and after method 10, and some of the steps described may be removed, replaced, or eliminated with respect to additional embodiments of method 10. The following discussion provides an interconnect that may be fabricated according to method 10.
Fig. 2-6, 7A-11A, 7B-11B, 7C-11C, and 12-16 are partial schematic diagrams of a portion or all of an Integrated Circuit (IC) device 200 at various stages of fabricating a multilayer interconnect structure of the IC device 200, such as those associated with the method 10 in fig. 1A-1B, in accordance with various aspects of the present invention. Fig. 2-6, 7A-11A, and 12-16 are partial cross-sectional views of an IC device 200 in the X-Z plane at various stages of fabrication according to various aspects of the invention. Fig. 7B-11B and 7C-11C are partial cross-sectional views of the portion of the IC device 200 in fig. 7A-11A in the Y-Z plane along lines at various stages of fabrication according to various aspects of the present invention. The IC device 200 may be included in a microprocessor, memory, and/or other IC device. In some embodiments, the IC device 200 may be part of an IC chip, a system on a chip (SoC), or portions thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type fets (pfets), n-type fets (nfets), metal oxide semiconductor fets (mosfets), complementary mos (cmos) transistors, Bipolar Junction Transistors (BJTs), laterally diffused mos (ldmos) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The various transistors may be planar transistors or multi-gate transistors, such as finfets, depending on the design requirements of the IC device 200. For clarity, fig. 2 through 6, 7A through 11A, 7B through 11B, 7C through 11C, and 12 through 16 have been simplified to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 200.
Turning to fig. 2, the IC device 200 includes a substrate (wafer) 210. In the illustrated embodiment, substrate 210 comprises silicon. Alternatively or additionally, substrate 210 includes another elemental semiconductor, such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Optionally, substrate 210 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and/or other suitable methods. Substrate 210 includes doped regions formed by an ion implantation process, a diffusion process, and/or other suitable doping processes. In some embodiments, the substrate 210 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 210 includes n-type doped regions (e.g., n-type wells) doped with n-type dopants, such as phosphorous, arsenic, other n-type dopants, or combinations thereof. In some embodiments, the substrate 210 includes a doped region formed with a combination of p-type dopants and n-type dopants. Various doped regions may be formed directly on and/or in substrate 210, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof.
Isolation features may be formed over and/or in the substrate 210 to isolate various regions of the IC device 200, such as a device region. For example, the isolation features define and electrically isolate active device regions and/or passive device regions from one another. The isolation feature comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or combinations thereof. The isolation feature may include different structures such as a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, and/or a local oxidation of silicon (LOCOS) structure. In some embodiments, the isolation features are formed by etching a trench (trenches) in the substrate 210 and filling the trench with an insulator material (e.g., using a Chemical Vapor Deposition (CVD) process or a spin-on-glass process). A Chemical Mechanical Polishing (CMP) process may be performed to remove excess insulator material and/or to planarize the top surface of the isolation features. In some embodiments, the isolation features may be formed by depositing an insulator material over the substrate 210 after forming the fin structures (in some embodiments, such that the insulator material fills gaps (trenches) between the fin structures) and etching back the insulator material. In some embodiments, the isolation feature comprises a multi-layer structure filling the trench, such as a bulk dielectric layer disposed over a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer comprise a material depending on design requirements (e.g., a bulk dielectric layer comprising silicon nitride is disposed over a liner dielectric layer comprising thermal oxide). In some embodiments, the isolation feature includes a dielectric layer disposed over a doped liner layer including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG).
Various gate structures are disposed over substrate 210, such as gate structure 230A, gate structure 230B, and gate structure 230C. Each of the gate structures 230A-230C interfaces with a respective channel region defined between a respective source region and a respective drain region (hereinafter referred to as source/drain regions) such that current may flow between the respective source/drain regions during operation. In some embodiments, gate structures 230A-230C are formed over the fin structures such that each of gate structures 230A-230C wraps around a portion of the fin structure and is interposed between respective source/drain regions of the fin structure. Each of the gate structures 230A-230C includes a Metal Gate (MG) stack 232. MG stack 232 is formed by a deposition process, a photolithography process, an etching process, other suitable processes, or a combination thereof. Deposition processes include CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), high density plasma CVD (hdpcvd), metal organic CVD (mocvd), remote plasma CVD (rpcvd), plasma enhanced CVD (pecvd), low pressure CVD (lpcvd), atomic layer CVD (alcvd), atmospheric pressure CVD (apcvd), plasma enhanced ALD (peald), plating, other suitable methods, or combinations thereof. The lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithographic exposure process may be assisted, implemented or replaced by other methods, such as maskless lithography, electron beam writing or ion beam writing. The etching process includes a dry etching process, a wet etching process, other etching processes, or a combination thereof. MG stack 232 is fabricated according to a gate-last process, a gate-first process, or a hybrid gate-last/gate-first process. In a gate last process embodiment, gate structures 230A-230C include dummy gate stacks, which are then replaced, in whole or in part, by MG stacks 232. The dummy gate stack includes, for example, an interface layer (e.g., a silicon oxide layer) and a dummy gate electrode layer (e.g., a polysilicon layer) disposed over the interface layer. In such an embodiment, the dummy gate electrode layer is removed, thereby forming an opening filled with MG stack 232. In some embodiments, the dummy gate stack includes a dummy gate dielectric layer disposed between the interface layer and the dummy gate electrode layer, which may be removed during the gate replacement process. In some embodiments, the dummy gate dielectric layer and/or the interfacial layer are not removed during the gate replacement process and form part of MG stack 232.
The MG stacks 232 are configured to achieve a desired function according to the design requirements of the IC device 200, such that the MG stacks 232 of the gate structures 230A-230C may include the same or different layers and/or materials from each other. In some embodiments, MG stack 232 includes a gate dielectric (e.g., a gate dielectric layer) and a gate electrode (e.g., a work function layer and a bulk conductive layer). MG stack 232 may include many other layers, such as capping layers, interfacial layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some embodiments, a gate dielectric layer is disposed over the interfacial layer (comprising a dielectric material, such as silicon oxide), and a gate electrode is disposed over the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric materials include hafnium oxide (HfO)2) HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, hafnia-alumina (HfO)2-Al2O3) Alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials that have a high dielectric constant (k value) relative to the dielectric constant of silicon dioxide (k ≈ 3.9). For example, high-k dielectric materials have a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrode comprises a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN,Other conductive materials or combinations thereof. In some embodiments, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and the conductor layer is a metal layer formed over the work function layer. In some embodiments, the work function layer comprises an n-type work function material, such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function material, or combinations thereof. In some embodiments, the work function layer comprises a p-type work function material, such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2、MoSi2、TaSi2、NiSi2WN, other suitable p-type work function material, or combinations thereof. The bulk (or fill) conductive layer comprises a suitable conductive material, such as Al, W, and/or Cu. The bulk conductive layer may additionally or collectively comprise polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof.
Gate structures 230A-230C also include gate spacers 236, gate spacers 236 being disposed adjacent to MG stack 232 (e.g., along sidewalls of MG stack 232). The gate spacers 236 are formed by any suitable process and comprise a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may be deposited over the substrate 210, followed by anisotropic etching of the dielectric layer to form the gate spacers 236. In some embodiments, the gate spacer 236 comprises a multi-layer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or primary spacers, are formed adjacent to MG stack 232. In such embodiments, the sets of spacers may comprise materials having different etch rates. For example, a first dielectric layer comprising silicon and oxygen (e.g., silicon oxide) may be deposited over substrate 210 and etched to form a first set of spacers adjacent to MG stack 232, and a second dielectric layer comprising silicon and nitrogen (e.g., silicon nitride) may be deposited over substrate 210 and etched to form a second set of spacers adjacent to the first set of spacers. Before and/or after forming the gate spacers 236, an implantation, diffusion, and/or annealing process may be performed to form lightly doped source and drain (LDD) features and/or heavily doped source and drain (HDD) features in the substrate 210.
Epitaxial source/drain features (referred to as epitaxial source/drain features), such as epitaxial source/drain features 240A, epitaxial source/drain features 240B, epitaxial source/drain features 240C, and epitaxial source/drain features 240D, are disposed in the source/drain regions of substrate 210. The gate structure 230A is interposed between the epitaxial source/drain features 240A and the epitaxial source/drain features 240B such that a channel region is defined between the epitaxial source/drain features 240A and the epitaxial source/drain features 240B. The gate structure 230B is interposed between the epitaxial source/drain features 240B and the epitaxial source/drain features 240C such that a channel region is defined between the epitaxial source/drain features 240B and the epitaxial source/drain features 240C. The gate structure 230C is interposed between the epitaxial source/drain feature 240C and the epitaxial source/drain feature 240D such that a channel region is defined between the epitaxial source/drain feature 240C and the epitaxial source/drain feature 240D. In some embodiments, the gate structure 230A, the epitaxial source/drain features 240A, and the epitaxial source/drain features 240B form portions of a first transistor; the gate structure 230B, the epitaxial source/drain feature 240B, and the epitaxial source/drain feature 240C form part of a second transistor; and gate structure 230C, epitaxial source/drain feature 240C, and epitaxial source/drain feature 240D form portions of the third transistor.
In some embodiments, a semiconductor material is epitaxially grown on the substrate 210 and/or from the substrate 210 to form epitaxial source/drain features 240A-240D over source/drain regions of the substrate 210. In some embodiments, an etch process is performed on the drain/drain regions of the substrate 210 to form source/drain recesses, wherein the epitaxial source/drain features 240A-240D are grown to fill the source/drain recesses. In some embodiments, where the substrate 210 represents a portion of a fin structure, the epitaxial source/drain features 240A-240D wrap around source/drain regions of the fin structure and/or are disposed in source/drain recesses of the fin structure. The epitaxial process may implement a CVD deposition technique (e.g., Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and/or liquid precursors that interact with the components of the substrate 210. The epitaxial source/drain features 240A-240D are doped with n-type dopants and/or p-type dopants. In some embodiments, epitaxial source/drain features 240A-240D are epitaxial layers comprising silicon and/or carbon, wherein the epitaxial layer comprising silicon or the epitaxial layer comprising silicon carbon is doped with phosphorus, other n-type dopants, or a combination thereof. In some embodiments, epitaxial source/drain features 240A-240D are epitaxial layers comprising silicon and germanium, wherein the epitaxial layers comprising silicon and germanium are doped with boron, other p-type dopants, or combinations thereof. In some embodiments, the epitaxial source/drain features 240A-240D include materials and/or dopants that achieve a desired tensile stress and/or compressive stress in the channel region. In some embodiments, the epitaxial source/drain features 240A-240D are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source/drain features 240A-240D are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process is performed to activate dopants in the epitaxial source/drain features 240A-240D and/or other source/drain features (e.g., HDD regions and/or LDD regions).
A multilayer interconnect (MLI) component 250 is disposed over the substrate 210. The MLI component 250 electrically couples various devices (e.g., transistors, resistors, capacitors, and/or inductors) and/or components (e.g., the gate structures 230A-230C and/or the source/drain components 240A-240D) of the IC device 200 such that the various devices and/or components may operate according to the design requirements of the IC device 200. MLI component 250 includes a combination of dielectric and conductive layers (e.g., metal layers) configured to form various interconnects. The conductive layers are configured to form vertical interconnects (such as device level contacts and/or vias) and/or horizontal interconnects (such as wires). The vertical interconnects typically connect horizontal interconnects in different layers (or different planes) of the MLI component 250. During operation of the IC device 200, the interconnects route and/or distribute signals (e.g., clock signals, voltage signals, and/or ground signals) between devices and/or components of the IC device 200 and to devices and/or components external to the IC device 200. MLI component 250 is depicted with a given number of dielectric and conductive layers. The present invention contemplates MLI components 250 having more or fewer dielectric and/or conductive layers, depending on design requirements.
The MLI component 250 includes one or more insulating layers disposed over the substrate 210, such as an inter-layer dielectric (ILD) layer 252(ILD-0), an inter-layer dielectric (ILD) layer 254(ILD-1), a Contact Etch Stop Layer (CESL)262, and a Contact Etch Stop Layer (CESL) 264. ILD layer 252 is disposed over substrate 210 and ILD layer 254 is disposed over ILD layer 252. CESL262 is disposed between the ILD layer 252 and the substrate 210, the epitaxial source/drain features 240A-240C, and/or the gate structures 230A-230C (particularly the gate spacers 236). CESL264 is disposed between ILD layer 252, ILD layer 254, and/or gate structures 230A-230C. In some embodiments, ILD layer 252 has a thickness of about 10nm to about 25nm, ILD layer 254 has a thickness of about 10nm to about 25nm, CESL262 has a thickness of about 1nm to about 10nm, and CESL264 has a thickness of about 1nm to about 10 nm. The ILD layers 252, 254 and/or CESL262, 264 are formed over the substrate 210 by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods, or combinations thereof. In some embodiments, ILD layer 252 and/or ILD layer 254 are formed by a High Aspect Ratio Process (HARP), such as HDPCVD, which generally refers to a deposition process having parameters configured to achieve sufficient fill in high aspect ratio structures. In some embodiments, ILD layer 252 and/or ILD layer 254 are formed by a flowable cvd (fcvd) process that includes, for example, depositing a flowable material (such as a liquid compound) over substrate 210 and converting the flowable material to a solid material by a suitable technique (such as thermal annealing and/or treatment with ultraviolet radiation). After deposition of ILD layer 252, ILD layer 254, CESL262, and/or CESL264, a CMP process and/or other planarization process may be performed such that ILD layers 252, 254 and/or CESL262, 264 have a substantially planar surface.
ILD layers 252, 254 comprise dielectric materials including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, Tetraethylorthosilicate (TEOS), PSG, BSG, boron-doped phosphosilicate glass (BPSG), fluorosilicate glass (FSG),
Figure BDA0002710003020000141
(applied materials, Inc. of Santa Clara, Calif.), xerogels, aerogels, amorphous carbon fluorides, parylene, benzocyclobutene (BCB) -based dielectric materials, SiLK (Dow chemical company of Midland, Mich.), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layers 252, 254 comprise a low-k dielectric material, which generally refers to a dielectric material having a low dielectric constant relative to the dielectric constant of silicon dioxide (k ≈ 3.9). For example, low-k dielectric materials have dielectric constants less than about 3.9. In some embodiments, the low-k dielectric material has a dielectric constant of less than about 2.5, which may be referred to as an extremely low k (elk) dielectric material. In the illustrated embodiment, ILD layers 252, 254 comprise ELK dielectric materials (and thus may be referred to as ELK dielectric layers), such as silicon dioxide (SiO)2) (e.g., porous silica), silicon carbide (SiC), and/or carbon-doped oxides (e.g., SiCOH-based materials (e.g., with Si-CH)3A bond)), each material is tuned/configured to exhibit a dielectric constant of less than about 2.5. CESL262, 264 comprise a different material than ILD layers 252, 254, such as a different dielectric material than the dielectric material of ILD layers 252, 254. For example, wherein ILD layers 252, 254 comprise silicon and oxygen (e.g., SiCOH, SiO, for example)xOr other materials including silicon and oxygen having a dielectric constant less than about 2.5), the CESL262, 264 may include silicon and nitrogen and/or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and/or SiCO) (and thus may be referred to as a silicon nitride layer). In some embodiments, CESL262, 264 includes a metal oxide and/or metal nitride layer. The ILD layers 252, 254 and/or CESL262, 264 may comprise a multilayer structure with multiple dielectric materials.
Turning to fig. 3, one or more interconnect openings, such as interconnect opening 270A and interconnect opening 270B, are formed in the dielectric layer by a patterning process. Interconnect openings 270A and 270B extend vertically through ILD layer 254, CESL264, ILD layer 252, and CESL262 to expose epitaxial source/drain features 240B and epitaxial source/drain features 240C, respectively. The interconnect openings 270A, 270B may thus be referred to as source/drain contact (plug) openings. The interconnect opening 270A includes a sidewall 272A (defined by the ILD layer 254, CESL264, ILD layer 252, and CESL262), a sidewall 274A (defined by the ILD layer 254, CESL264, ILD layer 252, and CESL262), and a bottom 276A (defined by the epitaxial source/drain feature 240B) extending between the sidewall 272A and the sidewall 274A. The interconnect opening 270B includes a sidewall 272B (defined by the ILD layer 254, CESL264, ILD layer 252, and CESL262), a sidewall 274B (defined by the ILD layer 254, CESL264, ILD layer 252, and CESL262), and a bottom 276B (defined by the epitaxial source/drain feature 240C) extending between the sidewall 272B and the sidewall 274B. In fig. 3, each of the interconnect openings 270A, 270B has a trapezoidal shape, but the present invention contemplates interconnect openings 270A, 270B having other shapes, such as rectangular. The sidewalls 272A, 274A are tapered such that the bottom width of the interconnect opening 270A exposing the epitaxial source/drain features 240B is less than the top width of the interconnect opening 270A at the top surface of the ILD layer 254. The width of the interconnect opening 270A thus decreases along the z-direction from the top width of the interconnect opening 270A to the bottom width of the interconnect opening 270A. The sidewalls 272B, 274B are tapered such that the bottom width of the interconnect opening 270B exposing the epitaxial source/drain features 240C is less than the top width of the interconnect opening 270B at the top surface of the ILD layer 254. The width of the interconnect opening 270B thus decreases along the z-direction from the top width of the interconnect opening 270B to the bottom width of the interconnect opening 270B.
In some embodiments, the patterning process includes performing a photolithography process to form a patterned mask layer 278 having openings 279A (substantially aligned with the epitaxial source/drain features 240B) and openings 279B (substantially aligned with the epitaxial source/drain features 240C) therein over the ILD layer 254, and performing an etching process to transfer the pattern defined in the patterned mask layer 278 to the underlying dielectric layer (here, ILD layer 254, CESL264, ILD layer 252, and CESL 262). The photolithography process may include forming a photoresist layer on ILD layer 254 (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiant energy, such as Ultraviolet (UV) light, Deep Ultraviolet (DUV) light, or Extreme Ultraviolet (EUV) light, wherein the mask blocks, transmits, and/or reflects radiation to the photoresist layer depending on the mask pattern and/or the mask type of the mask (e.g., binary mask, phase-shift mask, or EUV mask), such that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiant energy, depending on the characteristics of the photoresist layer and the characteristics of the developer solution used in the development process, the exposed portions of the photoresist layer chemically change and the exposed (or unexposed) portions of the photoresist layer dissolve during the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. Alternatively, the exposure process may be performed by other methods, such as maskless lithography, electron beam writing, and/or ion beam writing, or replaced.
In some embodiments, the patterned photoresist layer is a patterned masking layer 278. In such embodiments, the patterned photoresist layer is used as an etch mask to remove portions of the underlying dielectric layer (here, ILD layer 254, CESL264, ILD layer 252, and/or CESL262) exposed by openings 279A, 279B. In some embodiments, a patterned photoresist layer is formed over a mask layer formed over an underlying dielectric layer prior to forming the photoresist layer, and the patterned photoresist layer is used as an etch mask to remove portions of the mask layer formed over the underlying dielectric layer, thereby forming a patterned mask layer 278. In such embodiments, the patterned masking layer is used as an etch mask to remove portions of ILD layer 254, CESL264, ILD layer 252, and CESL262 exposed by openings 279A, 279B. The etching process may include a dry etching process (e.g., a Reactive Ion Etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. Various selective etch processes may be performed to form the interconnect openings 270A, 270B. For example, the etching process may include: a first etch that selectively etches the ILD layer 254 relative to the patterned mask layer 278 and CESL264 such that the first etch stops when CESL264 is reached; a second etch that selectively etches CESL264 relative to ILD layers 254, 252 such that the second etch stops when ILD layer 252 is reached; a third etch that selectively etches the ILD layer 252 relative to the CESL262, 264 such that the third etch stops when CESL262 is reached; and a fourth etch that etches CESL262 selectively with respect to the ILD layers 252, 254 and the epitaxial source/drain features 240B, 240C, such that the fourth etch stops when the epitaxial source/drain features 240B, 240C are reached. In some embodiments, the first etch, the second etch, the third etch, and the fourth etch may be configured to be slightly over-etched. For example, the first etch may partially etch CESL264, the second etch may partially etch ILD layer 252, the third etch may partially etch CESL262, and/or the fourth etch may partially etch epitaxial source/drain features 240B, 240C. In some embodiments, the first etch, the second etch, the third etch, and the fourth etch are similar to the etch processes described herein for etching the ILD and CESL. In some embodiments, the etching process may include multiple steps for etching the CESL262, 264. In some embodiments, the etching process employs an etchant with low etch selectivity between ILD layers 254, 252 and CESL262, 264, such that interconnect openings 270A, 270B are formed by a single etch step, e.g., on a time basis. In some embodiments, patterned masking layer 278 is removed from ILD layer 254 after the etching process (in some embodiments, by a photoresist strip process). In some embodiments, patterned masking layer 278 is removed during the etching of ILD layer 254, CESL264, ILD layer 252, and/or CESL 262.
Turning to fig. 4, a silicide layer 280 is formed on the epitaxial source/drain features 240B, 240C. Silicide layer 280 extends through CESL 262. In the illustrated embodiment, the top surface of silicide layer 280 is disposed higher than the top surface of CESL262 relative to the top surface of substrate 210. In some embodiments, a top surface of silicide layer 280 is disposed below a top surface of CESL262 and/or is substantially planar with the top surface of CESL262 relative to the top surface of substrate 210. In some embodiments, the top surface of the silicide layer 280 is disposed lower than the top surface of the substrate 210. The silicide layer 280 may be formed by depositing a metal layer over the epitaxial source/drain features 240B, 240C and heating the IC device 200 (e.g., subjecting the IC device 200 to an annealing process) to react a component of the epitaxial source/drain features 240B, 240C (e.g., silicon and/or germanium) with a metal component of the metal layer. The metal layer includes any metal composition suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, yttrium, zirconium, other suitable metals, or combinations thereof. The silicide layer 280 thus includes a metal composition and a composition of the epitaxial source/drain features 240B, 240C, such as silicon and/or germanium. In some embodiments, silicide layer 280 comprises nickel silicide, titanium silicide, or cobalt silicide. Any unreacted metal, such as remaining portions of the metal layer, may be removed selectively with respect to the silicide layer 280 and/or the dielectric material, for example, by an etching process.
Then, source/ drain contacts 282A and 282B are formed in the interconnect openings 270A and 270B, respectively. Each of the source/ drain contacts 282A, 282B extends through the ILD layer 254, CESL264, and ILD layer 252 to the silicide layer 280 such that the source/ drain contacts 282A, 282B are disposed on the silicide layer 280 on the epitaxial source/drain features 240B, 240C, respectively. In some embodiments, source/ drain contacts 282A, 282B may extend partially or fully through CESL262 depending on the configuration of silicide layer 280. Each of the source/ drain contacts 282A, 282B includes a contact barrier 284 and a contact body layer 286 disposed over the contact barrier 284. A contact barrier 284 is disposed on the sidewalls 272A, 272B, sidewalls 274A, 274B, and bottoms 276A, 276B of the interconnect openings 270A, 270B, respectively. For example, the contact barrier 284 physically contacts the sidewalls 272A, 272B, sidewalls 274A, 274B, and bottoms 276A, 276B of the interconnect openings 270A, 270B, respectively. In some embodiments, the source/ drain contacts 282A, 282B are formed by performing a first deposition process to form a contact blocking material over the ILD layer 254 that partially fills the interconnect openings 270A, 270B and performing a second deposition process to form a contact material over the contact blocking material, wherein the contact material fills the remaining portions of the interconnect openings 270A, 270B. In such embodiments, contact barrier material and contact material are disposed in the interconnect openings 270A, 270B and over the top surface of the ILD layer 254. The first deposition process and the second deposition process may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, the contact barrier 284 has a substantially uniform thickness along the sidewalls 272A, 272B, 274A, 274B, and bottoms 276A, 276B of the interconnect openings 270A, 270B, respectively. The contact barrier 284 can thus be formed by a conformal deposition process. A CMP process and/or other planarization process is performed to remove excess contact material and contact barrier material, for example, from over the top surface of ILD layer 254, resulting in source/ drain contacts 282A, 282B (in other words, contact barrier 284 and contact body layer 286 fill interconnect openings 270A, 270B). The CMP process planarizes the top surfaces of the source/ drain contacts 282A, 282B such that, in some embodiments, the top surface of the ILD layer 254 and the top surfaces of the source/ drain contacts 282A, 282B form a substantially planar surface.
Contact barrier 284 comprises a material that promotes adhesion between the surrounding dielectric material (here, ILD layer 254, CESL264, and/or ILD layer 252) and contact body layer 286. The material of the contact barrier 284 may further prevent diffusion of metal components (e.g., metal atoms/ions) from the source/ drain contacts 282A, 282B into the surrounding dielectric material. In some embodiments, contact barrier 284 comprises titanium, titanium alloys, tantalum alloys, cobalt alloys, ruthenium alloys, molybdenum alloys, palladium alloys, other suitable compositions configured to promote and/or enhance adhesion between a metallic material and a dielectric material and/or prevent diffusion of metallic components from the metallic material to the dielectric material, or combinations thereof. For example, contact barrier layer 284 comprises tantalum, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, tantalum carbide, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbide, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt nitride, ruthenium, palladium, or combinations thereof. In some embodiments, contact barrier 284 comprises multiple layers. For example, the contact barrier 284 may include a first sublayer including titanium and a second sublayer including titanium nitride. In another example, contact barrier 284 may include a first sublayer comprising tantalum and a second sublayer comprising tantalum nitride. Contact layer 286 includes tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal composition, alloys thereof, or combinations thereof. In the illustrated embodiment, contact layer 286 includes tungsten, ruthenium, and/or cobalt. In some embodiments, the source/ drain contacts 282A, 282B do not include the contact barrier 284 (i.e., the source/ drain contacts 282A, 282B are non-barrier contacts) such that the contact layer 286 physically contacts the ILD layer 254, CESL264, ILD layer 252, silicide layer 280, and/or epitaxial source/drain features 240B, 240C. In some embodiments, the source/ drain contacts 282A, 282B are partially barrier-free, with the contact barrier layer 284 disposed between the dielectric layer of the MLI component 250 and portions of the contact body layer 286. In some embodiments, the contact layer 286 includes multiple layers.
Turning to fig. 5, processing continues to form another dielectric layer of MLI component 250. For example, an ILD layer 292 is formed over ILD layer 254 and source/ drain contacts 282A, 282B. ILD layer 292 is similar to ILD layer 254. For example, the ILD layer 292 is formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition methods, or combinations thereof. ILD layer 292 comprises a dielectric material including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS, PSG, BSG, BPSG, FSG, Black Diamond (applied materials, santa clara, california), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, SiLK (dow chemical company, midland, michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 292 comprises a low-k dielectric material. For example, in the illustrated embodiment, the ILD layer 292 comprises an ELK dielectric material, such as silicon dioxide (SiO)2) (e.g. porous silica), carbonizationSilicon (SiC) and/or carbon doped oxides (e.g., SiCOH based materials (e.g., with Si-CH)3A bond), each material being tuned/configured to exhibit a dielectric constant of less than 2.5. In some embodiments, the ILD layer 292 may comprise a multilayer structure having a plurality of dielectric materials. In some embodiments, the ILD layer 292 has a thickness t1 of about 10nm to about 120 nm. After depositing the ILD layer 292, a CMP process and/or other planarization process may be performed such that the ILD layer 292 has a substantially planar surface.
In some embodiments, CESL294 is formed over the ILD layer 254 and the source/ drain contacts 282A, 282B prior to forming the ILD layer 292, such that the CESL294 is disposed between the ILD layer 292 and the ILD layer 254 and the source/ drain contacts 282A, 282B. CESL294 is similar to CESL 264. For example, CESL294 comprises a different material than the ILD layer 292, such as a different dielectric material than the dielectric material of the ILD layer 292, to achieve etch selectivity during subsequent etch processes, such as those used to form interconnect openings that expose the source/ drain contacts 282A, 282B. In other words, CESL294 and its surrounding layers will comprise materials with different etch sensitivities to a given etchant. For example, the etch rate of the material of CESL294 to the etchant is less than the etch rate of the material of ILD layer 292, such that the material of CESL294 serves as an etch stop layer during the etching of the overlying ILD layer 292. The material of CESL294 may also be configured to promote adhesion between CESL294 and ILD layer 292. In some embodiments, CESL294 includes silicon and nitrogen and/or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and/or SiCO). In some embodiments, CESL294 includes a metal oxide layer and/or a metal nitride layer. The metal may include aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. In some embodiments, CESL294 includes multiple layers. CESL294 is formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition methods, or combinations thereof. In some embodiments, CESL294 has a thickness t2 of about 1nm to about 30 nm. After depositing CESL294, a CMP process and/or other planarization process may be performed such that CESL294 has a substantially planar surface.
Turning to fig. 6, one or more interconnect openings, such as interconnect opening 300A and interconnect opening 300B, are formed in the dielectric layer (e.g., ILD layer 292 and CESL 294) by a patterning process. The interconnect opening 300A extends vertically through the ILD layer 292 and CESL294 to expose the source/drain contact 282A. The interconnect opening 300B extends vertically through the ILD layer 292 and CESL294 to expose the source/drain contact 282B. The interconnect openings 300A, 300B may therefore be referred to as via openings. The interconnect opening 300A includes a sidewall 302A (defined by the ILD layer 292 and CESL 294), a sidewall 304A (defined by the ILD layer 292 and CESL 294), and a bottom 306A (defined by the source/drain contact 282A) extending between the sidewall 302A and the sidewall 304A. The interconnect opening 300B includes a sidewall 302B (defined by the ILD layer 292 and CESL 294), a sidewall 304B (defined by the ILD layer 292 and CESL 294), and a bottom 306B (defined by the source/drain contact 282B) extending between the sidewall 302B and the sidewall 304B. The interconnect openings 300A, 300B have a width x1 defined between the sidewalls 302A, 302B and the sidewalls 304A, 304B, respectively, and a depth d1 defined between the top surface of the ILD layer 292 and the source/ drain contacts 282A, 282B, respectively. In some embodiments, the width x1 is about 10nm to about 30nm and the depth d1 is about 10nm to about 150nm (e.g., about 20nm to about 80 nm). As the CD of the interconnect openings 300A, 300B shrinks for advanced IC technology nodes, any subsequently formed metal paste/barrier layer will consume more space in the interconnect openings 300A, 300B, thereby reducing the remaining portion of the interconnect openings 300A, 300B for the subsequently formed metal fill layer. This may result in poor metal gap filling, where the metal fill layer cannot fill the remaining portions of the interconnect openings 300A, 300B without forming gaps (or voids), which significantly increases contact resistance. In some embodiments, the aspect ratio (e.g., d1/x1) of the interconnect openings 300A, 300B is greater than or equal to about 3. In some embodiments, the aspect ratio is about 5 to about 15. Since aspect ratios greater than or equal to about 3 can cause gap filling problems, as described further below, the present invention reduces the aspect ratio of the interconnect openings 300A, 300B (e.g., an aspect ratio less than about 3) prior to forming the metal paste/barrier layer, which can prevent or minimize the formation of gaps within interconnects formed in the interconnect openings 300A, 300B. In fig. 6, each of the interconnect openings 300A, 300B has a trapezoidal shape, but the present invention contemplates that the interconnect openings 300A, 300B have other shapes, such as rectangular. The sidewalls 302A, 304A are tapered such that the bottom width of the interconnect opening 300A exposing the source/drain contact 282A is less than the top width of the interconnect opening 300A at the top surface of the ILD layer 292. The width x1 of the interconnect opening 300A thus decreases along the z-direction from the top width of the interconnect opening 300A to the bottom width of the interconnect opening 300A. The sidewalls 302B, 304B are tapered such that the bottom width of the interconnect opening 300B exposing the source/drain contact 282B is less than the top width of the interconnect opening 300B at the top surface of the ILD layer 292. The width x1 of the interconnect opening 300B thus decreases along the z-direction from the top width of the interconnect opening 300B to the bottom width of the interconnect opening 300B. In the illustrated embodiment, the bottom width of the interconnect openings 300A, 300B is greater than the width of the source/ drain contacts 282A, 282B, such that the interconnect openings 300A, 300B also expose portions of the ILD layer 254. In some embodiments, the bottom width is less than the width of the source/ drain contacts 282A, 282B or substantially the same as the width of the source/ drain contacts 282A, 282B.
In some embodiments, the patterning process includes performing a photolithography process to form a patterned mask layer 308 having an opening 309A (substantially aligned with the source/drain contact 282A) and an opening 309B (substantially aligned with the source/drain contact 282B) therein over the ILD layer 292, and performing an etching process to transfer a pattern defined in the patterned mask layer 308 to the ILD layer 292 and CESL 294. The photolithography process may include forming a photoresist layer on the ILD layer 292 (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiant energy (such as UV light, DUV light, or EUV light), where, depending on the mask pattern and/or the mask type of the mask (e.g., binary mask, phase shift mask, or EUV mask), the photoresist blocks, transmits, and/or reflects the radiation to the photoresist layer such that an image is projected onto the photoresist layer corresponding to the mask pattern. Because the photoresist layer is sensitive to radiant energy, depending on the characteristics of the photoresist layer and the characteristics of the developer solution used in the development process, the exposed portions of the photoresist layer chemically change and the exposed (or unexposed) portions of the photoresist layer dissolve during the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. Alternatively, the exposure process may be performed by other methods, such as maskless lithography, electron beam writing, and/or ion beam writing, or replaced. In some embodiments, the patterned photoresist layer is a patterned masking layer 308. In such embodiments, the patterned photoresist layer is used as an etch mask to remove portions of ILD layer 292 and CESL294 exposed by openings 309A, 309B. In some embodiments, a patterned photoresist layer is formed over the mask layer formed over the ILD layer 292 and is used as an etch mask to remove portions of the mask layer formed over the ILD layer 292 to form the patterned mask layer 308 prior to forming the photoresist layer. In such embodiments, the patterned mask layer is used as an etch mask to remove portions of ILD layer 292 and CESL294 exposed by openings 309A, 309B. In some embodiments, the patterned masking layer 308 is removed from the ILD layer 292 (in some embodiments, by a photoresist strip process) after the etching process. In some embodiments, patterned masking layer 308 is removed during etching of ILD layer 292 and/or CESL 294.
The etching process may include a dry etching process, a wet etching process, other suitable etching process, or a combination thereof. For example, the etching process is a dry etching process, such as an RIE process, that removes material of the ILD layer 292 (e.g., material comprising silicon and oxygen) and material of the CESL294 (e.g., material comprising silicon and nitrogen) at a higher rate than material of the patterned mask layer 308 and/or the source/ drain contacts 282A, 282B (e.g., material comprising metal) (i.e., the etchant has a high etch selectivity with respect to the ILD layer 292 and CESL 294). In some embodiments, the dry etch process is configured to generate a fluorine-containing plasma from a fluorine-containing etch gas, such that the dry etch process removes the ILD layer 292 and CESL294 using plasma-excited fluorine-containing species. The fluorine-containing etching gas comprises fluorine(F2) Fluoromethane (e.g. CH)3F) Difluoromethane (e.g. CH)2F2) Trifluoromethane (e.g., CHF)3) Tetrafluoromethane (e.g. CF)4) Hexafluoroethane (e.g. C)2F6) Sulfur hexafluoride (e.g. SF)6) Nitrogen trifluoride (e.g., NF)3) Other fluorine-containing etchants, or combinations thereof. The dry etch may alternatively or additionally use a hydrogen-containing etch gas (e.g., H)2And/or CH4) Nitrogen-containing etching gases (e.g., N)2And/or NH3) Chlorine-containing etching gas (e.g., Cl)2、CHCl3、CCl4And/or BCl3) Oxygen-containing etching gas (e.g., O)2) Bromine-containing etching gas (e.g., HBr and/or CHBr)3) An iodine-containing etching gas, other suitable etching gas, or combinations thereof. The dry etch may be configured to generate a plasma from any of the etch gases disclosed herein, such that the dry etch uses plasma-excited species to remove the ILD layer 292 and CESL 294. In some embodiments, a carrier gas is used to deliver the fluorine-containing etching gas and/or other etching gases. The carrier gas may be an inert gas such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof.
In some embodiments, the dry etch utilizes a composition comprising CF4To selectively etch the ILD layer 292 and CESL 294. In some embodiments, the dry etch utilizes a composition comprising CF4And O2、N2And/or H2The combined etching gas of (1). Can adjust CF4Flow rate of (C), O2Flow rate of, N2Flow rate of H2Flow of, CF4And O2、N2And/or H2Ratio of etching time, etching temperature, etching pressure and/or RF power to achieve the desired etching selectivity. In some embodiments, CF4The flow rate of (c) is about 10sccm to about 1000 sccm. In some embodiments, the duration of the dry etch is from about 5 seconds to about 50 seconds. In some embodiments, the RF power used to generate the fluorine-containing plasma is about 100W to about 1000W. In some embodiments, maintained in a process chamber during dry etchingThe pressure is about 10mTorr to about 1000 mTorr. In some embodiments, the temperature maintained in the process chamber during dry etching is from about 18 ℃ to about 100 ℃. In some embodiments, the etch process is a multi-step (staged) etch process including a first etch step that selectively etches the ILD292 and a second etch step that selectively etches the CESL 294. For example, the first etch step is configured to remove the ILD layer 292 but not remove or substantially not remove the CESL294 such that the first etch stops upon reaching the CESL294, while the second etch step is configured to remove the CESL294 but not remove or substantially not remove the ILD292 and the source/ drain contacts 282A, 282B such that the second etch stops upon reaching the source/ drain contacts 282A, 282B. Various etch parameters may be adjusted to achieve selective etching of the ILD layer 292 and CESL 294. For example, for the first etch step, an etchant for the etch process is selected that etches the material of the ILD layer 292 at a higher rate than the material of the CESL294 (i.e., the etchant has a high etch selectivity with respect to the material of the ILD layer 292). For the second etch step, an etchant for the etch process is selected that etches the material of CESL294 at a higher rate than the material of ILD layer 292 (i.e., the etchant has a high etch selectivity with respect to the material of CESL 294). In some embodiments, the first etch step etch and the second etch step may use the same etchant, but different etchant flow rates and/or composition concentrations. In some embodiments, the first etching step and/or the second etching step may be configured to slightly over-etch. In such embodiments, the first etch step may partially etch CESL294, and/or the second etch step may partially etch the source/ drain contacts 282A, 282B. In some embodiments, the second etching step may include a plurality of steps for selectively etching each layer of CESL294, wherein each step is configured to selectively etch a respective layer of CESL 294.
Turning to fig. 7A-7C, an etch process is performed to recess the source/ drain contacts 282A, 282B. Such processes may be referred to as contact etch back, contact recess, and/or plug recess (or etch back). The etching process is a dry etching process, a wet etching process, or other suitable etching processOr a combination thereof. In the illustrated embodiment, the contact etch-back is a wet etch that removes material (e.g., a metal material) of the source/ drain contacts 282A, 282B (i.e., the etchant has a high etch selectivity with respect to the source/ drain contacts 282A, 282B) at a higher rate than the material (e.g., a dielectric material, such as a silicon and oxygen-containing material) of the ILD layer 292 and the material (e.g., a dielectric material, such as a silicon and nitrogen-containing material) of the CESL 294. In the illustrated embodiment, the wet etchant solution removes the material of contact layer 286 at a higher rate than the material of contact barrier layer 284 (i.e., the etchant has a high etch selectivity with respect to contact layer 286), such that the contact etch back removes contact layer 286 but does not remove, or substantially does not remove, contact barrier layer 284. For example, the wet etching process uses a wet etchant solution including hydrofluoric acid (HF), nitric acid (HNO)3) Hydrochloric acid (HCl), ammonia (NH)4OH), hydrogen peroxide (H)2O2) Water (H)2O), other suitable wet etchant solution compositions, or combinations thereof. In some embodiments, the pH, etch temperature, and/or etch time of the wet etchant solution may be adjusted to achieve a desired etch selectivity. In some embodiments, the pH of the wet etchant solution is about 5.5 to about 8.5. In some embodiments, the temperature of the wet etchant solution is about 18 ℃ to about 100 ℃. In some embodiments, the duration of the wet etch is from about 10 seconds to about 200 seconds. As described further below, the contact etch back increases the contact area between the source/ drain contacts 282A, 282B and subsequently formed vias, which may improve the performance of the IC device 200 and/or improve the structural integrity of the vias and/or interconnect structures including the vias. In some embodiments, the contact etch back partially removes contact barrier 284 such that the thickness of contact barrier 284 varies along ILD layer 254. In some embodiments, the contact etch back completely removes the contact barrier 284.
After contact etch back, the interconnect opening 300A has an upper portion 310A and a lower portion 311A, and the interconnect opening 300B has an upper portion 310B and a lower portion 311B. The upper portions 310A, 310B are substantially identical in the X-Z plane and the Y-Z plane. For example, in the X-Z plane, the upper portions 310A, 310B are defined between the sidewalls 302A, 302B and the sidewalls 304A, 304B, respectively, and have a width w1 and a depth d1, as described above. In the Y-Z plane, upper portions 310A, 310B have a width Y1 defined between sidewalls 312A, 312B and sidewalls 313A, 313B, respectively, and a depth d1 defined between a top surface of ILD layer 292 and a bottom surface of CESL 294. Sidewalls 312A, 312B and sidewalls 313A, 313B are defined by ILD layer 292 and CESL 294. In some embodiments, width y1 is substantially the same as width x1 (e.g., about 10nm to about 30 nm). In some embodiments, width y1 is greater than or less than width x 1. The upper portions 310A, 310B also have a trapezoidal shape in the Y-Z plane, but the present invention contemplates the upper portions 310A, 310B having other shapes, such as rectangular. The sidewalls 312A, 312B and sidewalls 313A, 313B taper such that the bottom width of the upper portions 310A, 310B is less than the top width of the upper portions 310A, 310B. Thus, the width y2 decreases along the z-direction from the top width to the bottom width of the upper portions 310A, 310B. The present invention contemplates embodiments in which the upper portions 310A, 310B are configured differently in the X-Z plane and the Y-Z plane.
The lower portions 311A, 311B are configured differently in the X-Z plane and the Y-Z plane. For example, lower portions 311A, 311B have a trapezoidal shape in the X-Z plane (FIG. 7A) and a semicircular shape in the Y-Z plane (FIGS. 7B and 7C), although the present invention contemplates lower portions 311A, 311B having other shapes in the X-Z plane and the Y-Z plane, respectively. In fig. 7A, lower portion 311A is defined by sidewall 314A (defined by contact barrier 284), sidewall 315A (defined by contact barrier 284), and bottom 316A (defined by contact layer 286) extending between sidewall 314A and sidewall 315A; and lower portion 311B is defined by sidewall 314B (defined by contact barrier 284), sidewall 315B (defined by contact barrier 284), and bottom 316B (defined by contact layer 286) extending between sidewall 314B and sidewall 315B. A width x2 is defined between sidewalls 314A, 314B and sidewalls 315A, 315B, respectively. In the embodiment shown, the width x2 is less than the width x1 because the contact etch back selectively removes the contact layer 286 relative to the contact barrier 284. In some embodiments, the width x2 is about 8nm to about 30 nm. In some embodiments, the width x2 is greater than or substantially equal to the width x 1. Sidewalls 314A, 314B and sidewalls 315A, 315B are tapered such that the bottom width of lower portions 311A, 311B is less than the top width of lower portions 311A, 311B. Thus, width x2 decreases along the z-direction from the top width to the bottom width of lower portions 311A, 311B. A depth d2 is defined between the top and bottom surfaces 316A, 316B, respectively, of ILD layer 254. In some embodiments, the depth d2 is less than the depth d 1. In some embodiments, the depth d2 is less than or equal to about 30 nm.
In fig. 7B and 7C, lower portions 311A, 311B also include curved sidewalls 318A, 318B, respectively (defined by contact layer 286). A depth d2 is further defined between the top surface of ILD layer 254 and curved sidewalls 318A, 318B in the Y-Z plane, respectively. Thus, in the illustrated embodiment, the depth d2 is substantially the same along the x-direction, but varies along the y-direction. Width y2 is also defined by curved sidewalls 318A, 318B, respectively. In the embodiment shown, because the contact etch-back is isotropic in nature (in other words, the contact etch-back removes portions of the contact layer 286 laterally (e.g., along the x-direction and y-direction) and vertically (e.g., along the z-direction)), the top width of the lower portions 311A, 311B is greater than the bottom width of the upper portions 310A, 310B. For example, width y2 is greater than width y 1. In some embodiments, width y2 is about 10nm to about 50 nm. In some embodiments, width y2 is about 10nm to about 20nm greater than width y 1. In some embodiments, the contact etch back exposes portions of the bottom surface of CESL294, such as CESL surface 320A and CESL surface 320B. In some embodiments, the width y3 of the exposed CESL surface 320A, 320B is less than or equal to about 10 nm. The curved sidewalls 318A, 318B also result in the lower portions 311A, 311B having a tapered width in the Y-Z plane such that the width Y2 decreases along the Z-direction from the top to the bottom of the lower portions 311A, 311B.
Turning to fig. 8A-8C, via body material 330 is formed in the interconnect openings 300A, 300B by a bottom-up deposition process. The via body material 330 includes tungsten, tungsten alloys, ruthenium alloys, cobalt alloys, copper alloys, aluminum alloys, iridium alloys, palladium alloys, platinum alloys, nickel alloys, other low resistivity metal constituents and/or alloys thereof or combinations thereof. A bottom-up deposition process generally refers to a deposition process that fills the opening from bottom to top (which may also be referred to as bottom-up filling of the opening).In some embodiments, the bottom-up deposition process is selective CVD, wherein various parameters of the selective CVD are adjusted to selectively grow tungsten, ruthenium, cobalt, or alloys thereof from the contact body layer 286 and/or the contact barrier layer 284 while limiting (or preventing) the growth of tungsten, ruthenium, cobalt, or alloys thereof from the ILD layer 292 and/or CESL 294. The various parameters include deposition precursors (e.g., metal precursors and/or reactants), deposition precursor flow rates, deposition temperatures, deposition times, deposition pressures, other suitable deposition parameters, or combinations thereof. In the illustrated embodiment, various parameters of selective CVD are adjusted to selectively grow polycrystalline tungsten on contact layer 286 using a reduction reaction. In such embodiments, selective CVD includes subjecting a tungsten-containing precursor (e.g., WF)x(wherein x represents the number of F atoms and x.gtoreq.1), WCly(where y represents the number of Cl atoms and y ≧ 1), other suitable tungsten-containing gases, or combinations thereof) and a reactant precursor (e.g., H2Other suitable reactant gases, or combinations thereof) into the process chamber to deposit the via body material 330 on the contact layer 286 in the interconnect openings 300A, 300B. In some embodiments, a carrier gas is used to deliver the tungsten-containing precursor gas and/or the reactant gas to the process chamber. The carrier gas may be an inert gas such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, where the tungsten-containing precursor is tungsten hexafluoride (e.g., WF)6) In the case of (a), as provided in the following exemplary reduction reaction, it may be by H2Reduction of tungsten hexafluoride:
WF6+3H2→W+6HF
in some embodiments, where the tungsten-containing precursor is tungsten pentachloride (e.g., WCl)5) In the case of (a), as provided in the following exemplary reduction reaction, it may be by H2Reducing tungsten pentachloride:
2WCl5+5H2→2W+5HCl
in some embodiments, a tungsten-containing precursor is mixed with a reactant gas (e.g., H)2) Mixed and the ratio of tungsten containing precursor to reactant gas is about 0.1% to about 1.5%. In some embodiments, in selectingThe pressure maintained in the process chamber during sexual CVD is from about 1torr to about 50 torr. In some embodiments, the temperature of the IC device 200 (e.g., the substrate 210) during selective CVD is about 200 ℃ to about 400 ℃. In some embodiments, various parameters of the bottom-up deposition process are adjusted to minimize variations in the via body material 330 in the interconnect opening across the IC device 200, such as described below and herein. In some embodiments, the bottom-up deposition process is ALD, in which various parameters of ALD are adjusted to selectively grow tungsten, ruthenium, cobalt, or alloys thereof from the contact body layer 286 and/or the contact barrier layer 284 while limiting (or preventing) the growth of tungsten, ruthenium, cobalt, or alloys thereof from the ILD layer 292 and/or CESL 294. In some embodiments, multiple ALD cycles are performed to form the via body material 330. In some embodiments, the bottom-up deposition process is a plurality of cycles of deposition/etch steps, including, for example, depositing via body material over the IC device 200, and then sequentially etching back the via body material.
As shown in fig. 8A-8C, the bottom-up deposition process may not uniformly deposit via body material 330 in interconnect openings (such as interconnect opening 300A and interconnect opening 300B) across the IC device 200. For example, the via body material 330 partially fills the interconnect opening 300A, while completely filling the interconnect opening 300B. In the illustrated embodiment, the via body material 330 completely fills the lower portions 311A, 311B, partially fills the upper portion 310A, and completely fills the upper portion 310B. As such, the via body material 330 filling the interconnect opening 300A has a height (or thickness) h1 defined between the source/drain contact 282A (specifically, the top surface of the contact layer 286) and the top surface 332A of the via body material 330, and the via body material 330 filling the interconnect opening 300B has a height (or thickness) h2 defined between the source/drain contact 282B (specifically, the top surface of the contact layer 286) and the top surface 332B of the via body material 330. In some embodiments, height h1 is about 20nm to about 50nm, and height h2 is about 40nm to about 130 nm. In some embodiments, the ratio of height h 1to height h2 is about 1: 2 to about 1: 7. in some embodiments, the height (growth) variation ah between the via body material 330 deposited (grown) in the interconnect openings (such as interconnect openings 300A, 300B) of the IC device 200 is about 20nm to about 80 nm. In the illustrated embodiment, the top surface 332A and the top surface 332B have different surface profiles. For example, top surface 332A is a substantially flat surface and top surface 332B is a substantially curved surface, although the present disclosure indicates that both flat and curved surfaces may include irregularities and/or roughness that naturally result from a bottom-up deposition process (i.e., the flat and curved surfaces may not be completely smooth as shown). In some embodiments, top surface 332A and top surface 332B are substantially flat surfaces or substantially curved surfaces. In some embodiments, top surface 332A is a substantially curved surface, while top surface 332B is a substantially flat surface. The remaining (unfilled) portion of interconnect opening 300A has a depth d1 ', which depth d 1' is defined between the top surface of ILD layer 292 and the top surface 332A of via body material 330. In some embodiments, the depth d 1' is less than about 30 nm. The depth d 1' is less than the depth d1, which reduces the aspect ratio of the interconnect openings 300A, 300B. In some embodiments, the aspect ratio (e.g., d 1'/x 1) of the interconnect openings 300A, 300B is less than about 5, and in some embodiments, less than about 3, after the bottom-up deposition process. Reducing the aspect ratio of the interconnect openings 300A, 300B may prevent or minimize the formation of gaps within interconnects formed in the interconnect openings 300A, 300B. In the embodiment shown, the via body material 330 overfills the interconnect openings 300B and extends over and above the top surface of the ILD layer 292. For example, portions of via body material 330 form a via rivet head having a height (or thickness) h3 defined between the top surface of ILD layer 292 and top surface 332B of via body material 330. In some embodiments, the height h3 is about 5nm to about 20 nm. The width of the through-hole rivet head is greater than the width y 1. In the embodiment shown, the via body material 330 of the via rivet head extends above the top surface of ILD layer 292. In such embodiments, the portion of the top surface of the ILD layer 292 covered by the via body material 330 has a width y4 of about 5nm to about 15 nm. In some embodiments, as shown, width y4 is greater than width y 3. In some embodiments, width y4 is less than or substantially equal to width y 3. As the height h3 of the via rivet head increases, internal stresses within the via body material 330 increase, which may lead to continued growth and/or cracking of the via body material 330 during subsequent processing. Thus, in some embodiments, the bottom-up deposition process is adjusted to constrain the height h3 to a predetermined height, which may minimize internal stress of the via body material 330, while also ensuring that the height h1 is sufficient to reduce the aspect ratio of the interconnect openings 300A, 300B within a range that enhances metal gap filling. For example, in some embodiments, the bottom-up deposition process is adjusted to ensure that the height h3 is less than or equal to 20nm to minimize internal stress of the via body material 330, while the height h1 is within a target height range that achieves a depth d 1' of less than about 30nm to provide an interconnect opening 300A, 300B with an aspect ratio having improved metal gap-fill characteristics. In such an example, when the height h3 is greater than 20nm, the via body material 330 may exhibit a degree of internal stress that causes cracking in the via body material 330, which may negatively impact the performance of the IC device 200.
Turning to fig. 9A-9C, a via blocking layer 335 (also referred to as a via liner layer) is formed over the via body material 330. A via blocking layer 335 is formed over the top surface of ILD layer 292, top surfaces 332A, 332B of via body material 330, and sidewalls 302A, 304A defining the remaining portion of upper portion 310A. A via blocking layer 335 is formed in the interconnect opening 300A and partially fills the interconnect opening 300A. When deposited, the via blocking layer 335 floats over the source/drain contact 282A within the interconnect opening 300A and does not physically contact the source/drain contact 282A. In the illustrated embodiment, the via blocking layer 335 has a thickness t3 above the top surface of the ILD layer 292 and the top surfaces 332A, 332B of the via body material 330, and a thickness t4 above the sidewalls 302A, 304A defining the remaining portion of the upper portion 310A. In the illustrated embodiment, thickness t3 is greater than thickness t 4. For example, the thickness t3 is about 4nm to about 8nm, and the thickness t4 is about 1nm to about 3 nm. A thickness t4 of greater than about 3nm may leave insufficient space for subsequently formed via material, which may lead to gap-filling problems (e.g., voids within the via). In some embodiments, the via blocking layer 335 is conformally deposited over the IC device 200 such that the thickness t3 is substantially the same as the thickness t 4. In some embodiments, thickness t3 is less than thickness t4, depending on process conditions. In some embodiments, a via blocking layer 335 is formed over the via body material 330 to reduce internal stress and prevent cracking in the via body material 330. In some embodiments, the via body material 330 may completely fill both interconnect openings 300A, 300B (and in some embodiments, all interconnect openings on the wafer). In such embodiments, via blocking layer 335 may still be formed (and subsequently via body material as described below) to reduce internal stress and prevent cracking in via body material 330, for example during the planarization process. The via blocking layer 335 comprises a material that promotes adhesion between the dielectric material (here, ILD layer 292) and the subsequently formed metal material used to fill the remaining portions of the interconnect opening 300A. For example, via barrier layer 335 comprises titanium, a titanium alloy, tantalum, a tantalum alloy, cobalt, a cobalt alloy, ruthenium, a ruthenium alloy, molybdenum, a molybdenum alloy, tungsten, a tungsten alloy, other suitable compositions configured to promote and/or enhance adhesion between a metallic material and a dielectric material, or combinations thereof. In the illustrated embodiment, via blocking layer 335 comprises tantalum and nitrogen (e.g., tantalum nitride), titanium and nitrogen (e.g., titanium nitride), tungsten and nitrogen (e.g., tungsten nitride), or tungsten. In some embodiments, via blocking layer 335 comprises multiple layers. For example, the via blocking layer 335 includes a first sublayer including titanium and a second sublayer disposed over the first sublayer, the second sublayer including titanium nitride. In another example, via blocking layer 335 includes a first sublayer comprising tantalum and a second sublayer comprising tantalum nitride.
The via blocking layer 335 is deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. In some embodiments, the via blocking layer 335 is a titanium nitride layer formed by performing PVD to deposit a titanium layer over the IC device 200, and then performing a nitrogen plasma treatment on the titanium layer. In some embodiments, the pressure maintained in the process chamber during PVD is about 10mTorr to about 1 Torr. In some embodiments, the temperature maintained in the process chamber during PVD is from about 300 ℃ to about 450 ℃. In some embodiments, the PVD is a Radio Frequency (RF) sputtering process. In such embodiments, the RF sputtering process may employ about 1 kilowatt (kW) to about 2kWRF power. In some embodiments, the nitrogen plasma treatment includes exposing the titanium layer to a nitrogen-containing plasma (i.e., bombarding the titanium layer with plasma-excited nitrogen-containing species to drive nitrogen into the titanium layer). In some embodiments, the via blocking layer 335 comprises a titanium nitride layer disposed over a titanium layer, wherein the titanium layer is formed by performing PVD and the titanium nitride layer is formed by performing CVD. In some embodiments, the pressure maintained in the process chamber during PVD is between about 10mTorr and about 150 mTorr. In some embodiments, the temperature maintained in the process chamber during PVD is from about 400 ℃ to about 500 ℃. In embodiments where PVD is an RF sputtering process, PVD may employ about 3kW to about 5kW of RF power. In some embodiments, CVD employs a titanium-containing precursor, such as tetrakis (dimethylamino) titanium (TDMAT). In some embodiments, the pressure maintained in the process chamber during CVD is about 1torr to about 5 torr. In some embodiments, the temperature maintained in the process chamber during CVD is from about 100 ℃ to about 500 ℃. In some embodiments, via blocking layer 335 comprises a tungsten-containing layer formed by CVD using a tungsten-containing precursor, such as tungsten hexacarbonyl (w (co)6). In some embodiments, the CVD process employs a tungsten-containing precursor and hydrogen (H)2) Silane (SiH)4) And/or boranes (e.g., diborane (B)2H6) Mixtures of (a) and (b).
Turning to fig. 10A-10C, a via body material 340 is formed over via blocking layer 335. A via body material 340 is formed in the interconnect opening 300A and fills the remaining portion of the upper portion 310A of the interconnect opening 300A. In the illustrated embodiment, via body material 340 is disposed over and covers the top surface of ILD layer 292 and top surface 332B of via body material 330. In some embodiments, via body material 340 does not cover or only partially covers top surface 332B, depending on the thickness of via body material 340. Via material 340 comprises tungsten, tungsten alloys, ruthenium alloys, cobalt alloys, copper alloys, aluminum alloys, iridium alloys, palladium alloys, platinum alloys, nickel alloys, other low resistivity metal constituents, and/or alloys or combinations thereof. In the illustrated embodiment, the via body material 340 and the via body material 330 compriseIncluding the same metals. For example, via body material 340 and via body material 330 comprise tungsten. In some embodiments, via body material 340 and via body material 330 comprise different metals. In the illustrated embodiment, the via body material 340 and the via body material 330 are formed by different processes. For example, a blanket deposition process, such as blanket CVD, is performed to deposit via body material 340 over via blocking layer 335. The blanket deposition process deposits the via body material 340 over the entire exposed surface of the IC device 200. In some embodiments, blanket CVD includes subjecting a tungsten-containing precursor (e.g., WF)6Or WCl5And reactant precursors (e.g., H)2Other suitable reactant gases, or combinations thereof) into the process chamber. In some embodiments, a carrier gas is used to deliver the tungsten-containing precursor gas and/or the reactant gas to the process chamber. The carrier gas may be an inert gas such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the pressure maintained in the process chamber during blanket CVD is from about 1torr to about 500 torr. In some embodiments, the temperature maintained in the process chamber during blanket CVD is from about 200 ℃ to about 400 ℃. In some embodiments, the blanket deposition process is PVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof.
Turning to fig. 11A-11C, a CMP process and/or other planarization process is performed to remove excess via body material 340, via blocking layer 335, and via body material 330 (such as the material disposed over the top surface of ILD layer 292), resulting in via 350A and via 350B of MLI component 250. Vias 350A electrically and/or physically couple source/drain contacts 282A to a conductive component of MLI component 250, such as a first conductive line of a metal layer of MLI component 250 (e.g., a metal 1(M1) layer), and vias 350B electrically and/or physically couple source/drain contacts 282B to a conductive component of MLI component 250, such as a second conductive line of a metal layer of MLI component 250 (e.g., an M1 layer). The vias 350A, 350B may thus be referred to as vias to contacts. The CMP process may planarize the top surfaces of vias 350A, 350B such that the top surface of ILD layer 292 and the top surfaces of vias 350A, 350B are substantially planar surfaces. Vias 350A, 350B include via body material 340, via blocking layer 335, and/or via body material 330 remaining in interconnect openings 300A, 300B after the planarization process, referred to as via body layer 340 ', via blocking layer 335 ', and via body layer 330 ', respectively. Via 350A has a lower via portion AL and an upper via portion AU, and via 350B has a lower via portion BL and an upper via portion BU. The lower via portions AL, BL extend into the source/ drain contacts 282A, 282B, respectively. In particular, the lower via portions AL, BL extend from the top surface of the ILD layer 254 to the top surfaces of the contact layers 286 of the source/ drain contacts 282A, 282B, respectively. The lower via portion AL, BL has a width x2 along the x direction, a width y2 along the y direction, and a thickness t5 along the z direction. In the illustrated embodiment, thickness t5 is approximately equal to depth d2 (e.g., thickness t5 is less than or equal to about 10 nm). Upper via portions AU, BU extend, for example, from the top surface of ILD layer 292, through ILD layer 292 and CESL294, to the top surface of ILD layer 254. The upper through-hole portion AU, BU has a width x1 along the x direction, a width y1 along the y direction, and a thickness t6 along the z direction. In the illustrated embodiment, the thickness t6 is approximately equal to the depth d1 (e.g., the thickness t6 is about 20nm to about 80 nm). In the illustrated embodiment, the width of lower via portions AL, BL is less than the width of upper via portions AU, BU in the X-Z plane (i.e., width X2 is less than width X1), and the width of lower via portions AL, BL is greater than the width of upper via portions AU, BU in the Y-Z plane (i.e., width Y2 is greater than width Y1). In some embodiments, the width of lower via portions AL, BL in the X-Z plane is greater than or about equal to the width of upper via portions AU, BU. In some embodiments, the width of lower via portions AL, BL in the Y-Z plane is less than or about equal to the width of upper via portions AU, BU.
The lower via portion AL and the lower via portion BL are substantially the same. For example, each of the lower via portions AL, BL includes a lower portion of the via body layer 330' in physical contact with the contact barrier layer 284 and the contact body layer 286 of the source/ drain contacts 282A, 282B, respectively. In the X-Z plane, the lower portion of the via body layer 330' has tapered, substantially planar side surfaces that meet the contact barrier 284 of the source/ drain contacts 282A, 282B, respectively, and a substantially planar bottom surface that meets the contact body layer 286 of the source/ drain contacts 282A, 282B, respectively. Contact barrier 284 separates the lower tapered, substantially planar side surfaces of via body layer 330' from ILD layer 254. In the Y-Z plane, the lower portion of the via body layer 330' has a substantially curved surface that meets the contact body layer 286 of the source/ drain contacts 282A, 282B, respectively. A contact layer 286 and a contact barrier 284 separate the lower, substantially curved surface of the via body layer 330' from the ILD layer 254. The lower via portions AL, BL increase the contact area between the vias 350A, 350B and the source/ drain contacts 282A, 282B, which reduces the resistance between the vias 350A, 350B and the source/ drain contacts 282A, 282B, thereby improving the overall performance of the IC device 200. For example, instead of vias 350A, 350B having a single interface (e.g., between the bottom surface of the via 350A, 350B and the top surface of the source/ drain contact 282A, 282B, respectively), the lower via portions AL, BL are surrounded by the source/ drain contact 282A, 282B, respectively, and have multiple interfaces (e.g., bottom and sidewall interfaces) with the source/ drain contact 282A, 282B, respectively. The increased contact area provided by the lower via portions AL, BL also improves the mechanical strength of the vias 350A, 350B, and thus improves structural stability. Furthermore, the portions of the via body layer 330' that extend below the CESL surfaces 320A, 320B and engage the CESL surfaces 320A, 320B, respectively, in the Y-Z plane secure the vias 350A, 350B to the source/ drain contacts 282A, 282B, further improving the mechanical strength of the vias 350A, 350B, and thus the structural stability.
Because the growth (and thus the height) of the via body material 330 varies in the interconnect openings of the IC device 200, the via body layer 335' is randomly located within the vias of the IC device 200, resulting in vias to source/drain contacts having different configurations on the IC device 200. For example, in fig. 11A-11C, because via body material 330 partially fills interconnect opening 300A and completely fills interconnect opening 300B, upper via portion AU of via 350A includes via body layer 330 ', via blocking layer 335', and via body layer 340 ', while upper via portion BU of via 350B includes only via body layer 330'. The upper via part AU may be divided into an upper via part AU-1 and an upper via part AU-2. Upper via portion AU-1 is similar to upper via portion BU, except that upper via portion AU-1 has a thickness that is less than a thickness of upper via portion BU. For example, each of the upper via portions AU-1, BU includes an upper portion of the via body layer 330'. The upper portion of via body layer 330 'has a thickness t6 in via 350B, while the upper portion of via body layer 330' has a thickness t7 in via 350A that is less than thickness t 6. The upper portion of the via body layer 330' has tapered, substantially planar side surfaces in physical contact with and bordering the ILD layer 292 and CESL294 in the X-Z plane and the Y-Z plane. Thus, there is no barrier (or liner) layer between the upper via portions AU-1, BU and the dielectric layers (e.g., CESL294 and ILD layer 292) of the MLI component 250. In the illustrated embodiment, the via 350B may be referred to as a barrier-free via because no barrier layer is disposed between the via body layer 330' and the ILD layer 292 or CESL 294. In contrast, via 350A may be referred to as a partial barrier-free via since upper via portion AU-1 does not have a barrier layer disposed between via body layer 330 'and ILD layer 292 or CESL294, but upper via portion AU-2 includes a via barrier layer 335' disposed between via body layer 340 and ILD 292. In fig. 11A-11C, via blocking layer 335 'is also disposed between via body layer 340' and via body layer 330 'such that via blocking layer 335' floats within via 350A and does not physically contact source/drain contact 282A. The upper via portion AU-2 has a thickness t8 along the z direction. In the illustrated embodiment, thickness t8 is approximately equal to depth d 1' (e.g., thickness t8 is about 1nm to about 50 nm). In some embodiments, the ratio of the thickness t8 to the width x1 (e.g., t8/x1) of the upper via portion AU-2 is less than about 5, and in some embodiments, less than about 3. The thickness t8 may be greater or less than the thickness t7 depending on the growth of the via body material 330.
In another example, such as shown in fig. 17A-17C, because the growth (and thus height) of the via body material 330 varies in the interconnect openings of the IC device 200, instead of the via body material 330 partially filling the interconnect openings 300A and completely filling the interconnect openings 300B, the via body material 330 partially fills the interconnect openings 300A and 300B, but has a different thickness. In such embodiments, each of upper via portion AU of via 350A and upper via portion BU of via 350B includes via layer 330 ', via barrier layer 335 ', and via layer 340 '. The upper via portion AU may be divided into an upper via portion AU-1 and an upper via portion AU-2, and the upper via portion BU may be divided into an upper via portion BU-1 and an upper via portion BU-2. Upper via portion AU-1 is similar to upper via portion BU-1, except that upper via portion AU-1 has a thickness that is less than a thickness of upper via portion BU-1. For example, each of the upper via portions AU-1, BU-1 includes an upper portion of the via body layer 330 ', but the upper portion of the via body layer 330 ' has a thickness t9 in the via 350B, and the upper portion of the via body layer 330 ' has a thickness t7 in the via 350A that is less than the thickness t 9. The thickness t7 and the thickness t9 are both smaller than the thickness t6 of the upper through-hole portions AU, BU. The upper portion of the via body layer 330' has tapered, substantially planar side surfaces in physical contact with and bordering the ILD layer 292 and CESL294 in the X-Z plane and the Y-Z plane. Thus, there is no barrier (or liner) layer between the upper via portions AU-1, BU-1 and the dielectric layers (e.g., CESL294 and ILD layer 292) of the MLI component 250. In the illustrated embodiment, via layers 350A, 350B may be referred to as partial unbaffled vias because upper via portions AU-1, BU-1 do not have a barrier layer disposed between via layer 330 'and ILD layer 292 or CESL294, but upper via portions AU-2, BU-2 include a via barrier layer 335' disposed between via layer 340 and ILD 292. In fig. 17A-17C, a via blocking layer 335 'is also disposed between the via body layer 340' and the via body layer 330 'such that the via blocking layer 335' floats within the vias 350A and 350B and does not physically contact the source/ drain contacts 282A, 282B. Thickness t10 of upper via portion BU-2 is less than thickness t8 of upper via portion AU-2 such that via blocking layer 335 'is positioned differently within via 350A than via blocking layer 335' is positioned within via 350B. For example, in the illustrated embodiment, the distance between the top surface of substrate 210 and via blocking layer 335 'of via 350A (specifically, the bottom surface of via blocking layer 335') is less than the distance between the top surface of substrate 210 and via blocking layer 335 'of via 350B (specifically, the bottom surface of via blocking layer 335'). In some embodiments, in fig. 17A-17C, the ratio of thickness t8 to width x1 of upper through-hole portion AU-2 (e.g., t8/x1) and the ratio of thickness t10 to width x1 of upper through-hole portion BU-2 (e.g., t10/x1) are each less than about 5, and in some embodiments, less than about 3. In the illustrated embodiment, the ratio of thickness t8 to width x1 is greater than the ratio of thickness t10 to width x 1.
Turning to fig. 12-15, vias are formed to one or more gate structures (such as gate structure 230B) of the IC device 200. Turning to fig. 12, an interconnect opening 360 is formed in the dielectric layer by a patterning process such as described herein. The interconnect opening 360 extends vertically through the ILD layer 292, CESL294, ILD layer 254, and CESL264 to the metal gate stack 232 of the gate structure 230B. The interconnect opening 360 may be referred to as a gate contact (plug) opening. Interconnect opening 360 includes a sidewall 362 (defined by ILD layer 292, CESL294, ILD layer 254, and CESL 264), a sidewall 364 (defined by ILD layer 292, CESL294, ILD layer 254, and CESL 264), and a bottom 366 (defined by metal gate stack 232) extending between sidewall 362 and sidewall 364. In fig. 12, the interconnect opening 360 has a trapezoidal shape, but the present invention contemplates that the interconnect opening 360 has other shapes (such as rectangular). The sidewalls 362, 364 are tapered such that the bottom width of the interconnect opening 360 exposing the metal gate stack 232 of the gate structure 230B is less than the top width of the interconnect opening 360 at the top surface of the ILD layer 292. Accordingly, the width of the interconnect opening 360 decreases from the top to the bottom of the interconnect opening 360 along the z-direction. In some embodiments, the width of the interconnect opening 360 increases along the z-direction. In some embodiments, the width of the interconnect opening 360 is substantially the same along the z-direction.
In some embodiments, the patterning process includes performing a photolithography process to form a patterned mask layer 365 having an opening 367 (substantially aligned with the metal gate stack 232 of the gate structure 232B), and performing an etching process to transfer a pattern defined in the patterned mask layer 365 to the underlying dielectric layers (here, ILD layer 292, CESL294, ILD layer 254, and CESL 264). The patterning process used to form patterned masking layer 365 and interconnect openings 360 can be similar to the patterning process used to form patterned masking layer 278 and interconnect openings 300A, 300B as described above. In some embodiments, patterned masking layer 365 is a patterned photoresist layer. In such embodiments, the patterned photoresist layer is used as an etch mask to remove portions of the underlying dielectric layer exposed by openings 367. In some embodiments, a patterned photoresist layer is formed over a mask layer formed over an underlying dielectric layer prior to forming the photoresist layer, and the patterned photoresist layer is used as an etch mask to remove portions of the mask layer formed over the underlying dielectric layer, thereby forming a patterned mask layer 365. In such embodiments, the patterned masking layer is used as an etch mask to remove portions of the underlying dielectric layer exposed by openings 367. Various selective etch processes may be performed to form the interconnect opening 360. For example, the etching process may include: a first etch that selectively etches the ILD layer 292 relative to the patterned mask layer 365 and CESL294 such that the first etch stops when CESL294 is reached; a second etch that selectively etches CESL294 relative to ILD layers 294, 254, such that the second etch stops when ILD layer 254 is reached; a third etch that selectively etches the ILD layer 254 relative to CESL294, 264 such that the third etch stops when CESL264 is reached; and a fourth etch that selectively etches the CESL264 relative to the ILD layers 292, 254 and the metal gate stack 232 of the gate structure 230B such that the fourth etch stops when the metal gate stack 232 is reached. In some embodiments, the first etch, the second etch, the third etch, and the fourth etch may be configured to be slightly over-etched, as described herein. In some embodiments, the etching process may include multiple steps for etching CESL294, 264. In some embodiments, the etch process employs an etchant with low etch selectivity between the ILD layers 292, 254 and CESL294, 264, such that the interconnect opening 360 is formed in a single etch step based on, for example, time. In some embodiments, after the etching process, the patterned masking layer 365 is removed from the ILD layer 292 (in some embodiments, by a photoresist strip process). In some embodiments, patterned masking layer 365 is removed during etching of ILD layer 292, CESL294, ILD layer 254, and/or CESL 264.
Turning to fig. 13, a via blocking layer 370 (also referred to as a via liner layer) is formed over the IC device 200. For example, a via barrier layer 370 is formed over the top surface of the ILD layer 292, the top surfaces of the vias 350A, 350B, the sidewalls 362, 364 of the interconnect opening 360A, and the bottom 366 of the interconnect opening 360. A via blocking layer 370 is formed in the interconnect opening 360 and partially fills the interconnect opening 360. In the illustrated embodiment, the via barrier layer 370 has a thickness t9 above the top surface of the ILD layer 292 and the top surfaces of the vias 350A, 350B, and a thickness t10 above the sidewalls 362, 364 of the interconnect opening 360. In the illustrated embodiment, thickness t9 is greater than thickness t 10. For example, the thickness t9 is about 4nm to about 8nm, and the thickness t10 is about 1nm to about 3 nm. In some embodiments, the via blocking layer 370 is conformally deposited over the IC device 200 such that the thickness t9 is substantially the same as the thickness t 10. In some embodiments, thickness t9 is less than thickness t10, depending on process conditions. The via blocking layer 370 comprises a material that promotes adhesion between the dielectric material (here, ILD292, CESL294, ILD 254, and CESL 264) and the subsequently formed metal material used to fill the remaining portions of the interconnect opening 360. For example, via barrier layer 370 includes titanium, a titanium alloy, tantalum, a tantalum alloy, cobalt, a cobalt alloy, ruthenium, a ruthenium alloy, molybdenum, a molybdenum alloy, tungsten, a tungsten alloy, other suitable compositions configured to promote and/or enhance adhesion between a metallic material and a dielectric material, or combinations thereof. In the illustrated embodiment, via barrier layer 370 comprises tantalum and nitrogen (e.g., tantalum nitride), titanium and nitrogen (e.g., titanium nitride), tungsten and nitrogen (e.g., tungsten nitride), or tungsten. In some embodiments, via blocking layer 370 comprises multiple layers. For example, the via blocking layer 370 includes a first sub-layer including titanium and a second sub-layer including titanium nitride disposed over the first sub-layer. In another example, the via blocking layer 370 includes a first sublayer including tantalum and a second sublayer including tantalum nitride. The via blocking layer 370 is deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. In some embodiments, via blocking layer 370 is similar to via blocking layer 335 and is formed using a process similar to that described above for forming via blocking layer 335.
Turning to fig. 14, a via body layer 375 is formed over the via blocking layer 370. Via body layer 375 is formed in interconnect opening 360 and fills the remaining portion of interconnect opening 360. In the illustrated embodiment, the via body layer 375 is disposed over and covers the top surface of the ILD layer 292 and the top surfaces of the vias 350A, 350B. Via body layer 375 comprises tungsten, tungsten alloys, ruthenium alloys, cobalt alloys, copper alloys, aluminum alloys, iridium alloys, palladium alloys, platinum alloys, nickel alloys, other low resistivity metal constituents and/or alloys or combinations thereof. In the illustrated embodiment, the via body layer 375 comprises tungsten. The via body layer 375 is deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. In some embodiments, via body layer 375 is similar to via body material 340 and is formed using a process similar to that described above for forming via body material 340. For example, a blanket deposition process, such as blanket CVD, is performed to deposit a via body layer 375 over the via barrier layer 370.
Turning to fig. 15, a CMP process and/or other planarization process is performed to remove excess via body layer 375 and via barrier layer 370 (such as those disposed over the top surface of ILD layer 292 and the top surfaces of vias 350A, 350B), resulting in a via 380 of MLI component 250. The via 380 includes a via body layer 375 and a via barrier layer 370, referred to as via body layer 375 'and via barrier layer 370', respectively, that remain in the interconnect opening 360 after the planarization process. The vias 380 electrically and/or physically couple the metal gate stack 232 of the gate structure 230B to a conductive component of the MLI component 250, such as a third wire of a metal layer (e.g., the M1 layer) of the MLI component 250. Via 380 may thus be referred to as a via to the gate. Via 380 extends through ILD layer 292, CESL294, ILD layer 254, and CESL 264. The via 380 has a width x4 along the x-direction and a thickness t11 along the z-direction. In the illustrated embodiment, the thickness t11 is greater than the thickness t6 of the vias 350A, 350B, and the width x4 is less than the width x1 of the vias 350A, 350B. The CMP process may planarize the top surface of via 380 such that the top surface of ILD layer 292, the top surfaces of vias 350A, 350B, and the top surface of via 380 are substantially planar surfaces.
Turning to fig. 16, fabrication of the MLI component 250 can continue, for example, by forming additional dielectric and metal layers of the MLI component 250. For example, CESL 390 (similar to CESL262, 264, 294) is formed over ILD layer 292, vias 350A, 350B, and via 380, ILD layer 392 (similar to ILD layers 252, 254, 292) is formed over CESL 390, and one or more conductive lines (e.g., conductive line 394A, conductive line 394B, and conductive line 394C) are formed in ILD layer 392 and CESL 390. The conductive lines 394A-394C include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low resistivity metal compositions, alloys thereof, or combinations thereof. In some embodiments, forming conductive lines 394A-394C includes performing a photolithography and etching process to form three interconnect openings in ILD layer 392 and CESL 390 (where vias 350A, 350B and 380 are exposed), filling the interconnect openings with conductive material, and performing a planarization process that removes excess conductive material so that the conductive material and ILD layer 392 have a substantially planar surface. The interconnect opening has sidewalls defined by the ILD layer 392 (and CESL 390) and a bottom defined by the corresponding via. The conductive material is formed by a deposition process (e.g., PVD, CVD, ALD, and/or other suitable deposition processes) and/or an annealing process. In some embodiments, the conductive lines 394A-394C include a body layer (also referred to as a conductive plug). In some embodiments, the conductive lines 394A-394C include barrier layers, adhesion layers, and/or other suitable layers disposed between the bulk layer and the ILD layer 392 (and CESL 390). In such embodiments, the barrier and/or adhesion layer conforms to the interconnect opening such that the barrier and/or adhesion layer is disposed on the ILD layer 392 (and CESL 390) and the bulk layer is disposed on the barrier and/or adhesion layer. In some embodiments, the barrier layer, adhesion layer, and/or other suitable layer include titanium, titanium alloys (e.g., TiN), tantalum alloys (e.g., TaN), other suitable compositions, or combinations thereof. In the illustrated embodiment, the wires 394A-394C have a rectangular cross-section. For example, the conductive lines 394A-394C have substantially planar bottom surfaces, substantially planar top surfaces, and substantially planar side walls. In some embodiments, the sidewalls of conductive lines 394A-394C are tapered such that the thickness of conductive lines 394A-394C decreases from the top surface of ILD layer 390 to the top surface of ILD layer 292. In the embodiment shown, wire 394A physically contacts via 350A, wire 394C physically contacts via 380, and wire 394B physically contacts via 350B. In some embodiments, a wire 394A and a wire 394B electrically couple the epitaxial source/drain features 240B, 240C, respectively, to a first voltage, and a wire 394C electrically couples the metal gate 232 to a second voltage.
In fig. 16, the MLI component 250 includes a metal 0(M0) layer (including source/ drain contacts 282A, 282B), a metal 1(M1) layer (including conductive lines 394A-394C), and a via 0(V0) layer (including vias 350A, 350B and via 380) that physically and electrically connects the M0 layer to the M1 layer. The M0 layer is the lowest, bottom-most contact/metal layer of the MLI cell 250 and physically contacts the device features (e.g., source/drain features and/or gate structures) at the substrate level, the V0 layer is the lowest, bottom-most via layer of the MLI cell 250, and the M1 layer is the second lowest, bottom-most contact/metal layer of the MLI cell 250. The M0 layer may also be referred to as a contact layer, a local interconnect layer, or a device level contact layer. In the embodiment shown, via 380 directly and physically contacts gate structure 230B. In some embodiments, the M0 layer further includes a gate contact disposed between via 380 and gate structure 230B, wherein via 380 physically contacts the gate contact and the gate contact physically contacts gate structure 230B. In such embodiments, the gate contacts may be configured similar to the source/ drain contacts 282A, 282B. For example, the gate contact may include a contact body layer (such as contact body layer 286) disposed over a contact barrier layer (such as contact barrier 284). In such embodiments, in contrast to the contact layer 286 of the source/ drain contacts 282A, 282B, when the via 380 is formed, the contact layer of the gate contact is not recessed such that the contact barrier layer of the gate contact is not disposed along portions of the sidewalls of the via 380. In some embodiments, the present invention contemplates recessing the contact layer of the gate contact prior to forming the via 380 such that the via 380 extends into the gate contact similar to the vias 350A, 350B. Although not shown, it should be understood that the MLI component 250 may include additional metal and/or via layers formed above the M1 layer, such as a via 2(V2) layer disposed above the M1 layer, a metal 2(M2) layer disposed above the V2 layer, and the like, to provide the required electrical connections for the IC device 200. Fabrication may then continue to fabricate MLI component 250. For example, additional levels of MLI components 250 may be formed above the M1 layer, such as an M2 layer to an Mn layer, where n represents the number of metal layers in the MLI component 250, and each of the M2 layer to the Mn layer includes conductive lines, similar to the conductive lines 394A-394C disposed in a dielectric material. Vias similar to vias 350A, 350B may be fabricated to connect directly adjacent metal layers, such as connecting the M2 layer to the M3 layer. In some embodiments, vias may connect non-adjacent metal layers.
From the foregoing, it can be seen that the vias described in the present invention provide advantages over conventional vias. However, it is to be understood that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the vias to the contacts and the vias to the gate are provided with different configurations (in particular, different interface configurations) to optimize the reduction of contact resistance. For example, the vias to the contacts are at least partially free of barriers to increase the size of the via openings of the contacts, which improves metal filling (in some embodiments, reduces or eliminates voids within the vias to the contacts) and reduces the resistance of the vias to the contacts, while the vias to the gates have via barriers to ensure minimal via resistance to the gates. The present invention indicates that when a via blocking layer is employed in both the via to contact and the via to gate, the interface in the via to contact (e.g., between the via blocking layer and the source/drain contact) cannot achieve the same resistance reduction as the interface in the via to gate (e.g., between the via blocking layer and the metal gate), and any resistance reduction provided by the via blocking layer in the via to contact does not significantly exceed the risk of voids forming in the via to contact when the via blocking layer is incorporated therein. Thus, removing the via blocking layer from the via to the contact reduces any risk of forming voids, thus minimizing the resistance of the via to the contact and no greater than the resistance of the via to the contact with the via blocking layer. For example, a via to a contact having a via blocking layer may have a void therein, resulting in an increase in resistance of the via to the contact greater than that provided by any decrease in resistance provided by the incorporation of the via blocking layer. In another example, via body material of a via to a contact formed by a bottom-up deposition process exhibits low resistance characteristics, as described herein. In yet another example, forming the via barrier layer and the additional via body layer after the bottom-up deposition process ensures complete filling of the via opening to the contact (taking into account growth variations resulting from the bottom-up deposition process) and/or minimizes internal stress of the via body layer, thus reducing or eliminating cracking of the via body layer during planarization and/or other subsequent processing. Accordingly, the disclosed via fabrication methods take into account various via interface requirements and/or considerations.
The present invention provides many different embodiments. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first and second vias extend to and physically contact the first and second source/drain contacts, respectively. The first thickness of the first through hole is the same as the second thickness of the second through hole. The third via physically contacts a gate structure disposed between the first source/drain contact and the second source/drain contact. In some embodiments, the first via includes a first upper portion disposed above the first lower portion, and the second via includes a second upper portion disposed above the second lower portion. In such embodiments, the dielectric layer physically contacts the sidewalls of the first upper portion and the first source/drain contact physically contacts the sidewalls of the first lower portion, and the dielectric layer physically contacts the sidewalls of the second upper portion and the second source/drain contact physically contacts the sidewalls of the second lower portion. In some embodiments, each of the first and second vias has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction. The first direction is different from the second direction and the first cross-sectional profile is different from the second cross-sectional profile. In some embodiments, each of the first and second vias has a first bottom interface profile with the first and second source/drain contacts, respectively, along the first direction and a second bottom interface profile with the first and second source/drain contacts, respectively, along the second direction. The first direction is different from the second direction, the first bottom interface profile is defined by a substantially planar surface, and the second bottom interface profile is defined by a substantially curved surface.
In some embodiments, the dielectric layers include a first interlayer dielectric layer, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a contact etch stop layer disposed between the first interlayer dielectric layer and the second interlayer dielectric layer. First and second source/drain contacts are disposed in and extend through the first interlayer dielectric layer. The first via and the second via are disposed in and extend through the second interlayer dielectric layer and the contact etch stop layer. In such embodiments, a first portion of the first via that extends into the first source/drain contact physically contacts the bottom surface of the etch stop layer, and a second portion of the second via that extends into the second source/drain contact physically contacts the bottom surface of the etch stop layer.
In some embodiments, a first via having a first via layer configuration includes a first via body layer, a second via body layer disposed over the first via body layer, and a via blocking layer disposed between the first via body layer and the second via body layer. The first via body layer is in physical contact with the dielectric layer, and a via barrier layer is also disposed between the second via body layer and the dielectric layer. In further such embodiments, the second via having the second via layer configuration comprises a third via body layer in physical contact with the dielectric layer. The first via body layer and the third via body layer comprise the same material, the third via body layer has a second thickness, and the first via body layer has a third thickness that is less than the first thickness. In some embodiments, the first source/drain contact includes a first contact barrier layer and a first contact body layer, and the second source/drain contact includes a second contact barrier layer and a second contact body layer. In some embodiments, a first portion of the first contact barrier layer is disposed between the first contact body layer and the dielectric layer, and a second portion of the first contact barrier layer is disposed between the first via body layer and the dielectric layer. In some embodiments, a first portion of the second contact barrier layer is disposed between the second contact body layer and the dielectric layer, and a second portion of the second contact barrier layer is disposed between the third via body layer and the dielectric layer.
In some embodiments, a first via having a first via layer configuration includes a first via body layer, a second via body layer disposed over the first via body layer, and a first via barrier layer disposed between the first via body layer and the second via body layer. The first via body layer is in physical contact with the dielectric layer, and a first via blocking layer is also disposed between the second via body layer and the dielectric layer. In further such embodiments, the second via having the second via layer configuration includes a third via body layer, a fourth via body layer disposed over the third via body layer, and a second via blocking layer disposed between the third via body layer and the fourth via body layer. The third via body layer is in physical contact with the dielectric layer, and the second via blocking layer is also disposed between the fourth via body layer and the dielectric layer. In some embodiments, the first and third via body layers comprise a first material, the second and fourth via body layers comprise a second material, and the first and second via blocking layers comprise a third material. In some embodiments, a first distance between the first via blocking layer and the substrate is different from a second distance between the second via blocking layer and the substrate. In some embodiments, the first source/drain contact includes a first contact barrier layer and a first contact body layer, and the second source/drain contact includes a second contact barrier layer and a second contact body layer. A first portion of the first contact barrier layer is disposed between the first contact body layer and the dielectric layer, and a second portion of the first contact barrier layer is disposed between the first via body layer and the dielectric layer. A first portion of the second contact barrier layer is disposed between the second contact body layer and the dielectric layer, and a second portion of the second contact barrier layer is disposed between the third via body layer and the dielectric layer.
An exemplary device includes a gate structure disposed over a substrate. The gate structure is disposed between the first source/drain feature and the second source/drain feature. The device also includes a first source/drain contact and a second source/drain contact disposed in the dielectric layer. The first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature. The device also includes a first via, a second via, and a third via disposed in the dielectric layer. The first via physically contacts the first source/drain contact, the second via physically contacts the second source/drain contact, and the third via physically contacts the gate structure. The first via includes a first metal fill layer having a first sidewall in physical contact with the dielectric layer. The second via includes a second metal fill layer having a second sidewall in physical contact with the dielectric layer. The third via includes a third metal fill layer disposed over the metal barrier layer. The metal barrier layer is disposed between the third metal fill layer and the dielectric layer such that the third sidewall of the third metal fill layer does not physically contact the dielectric layer. In some embodiments, the first and second vias have a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction. The first direction is different from the second direction. The first bottom of the first via and the second bottom of the second via have substantially flat surfaces in the first cross-sectional profile and substantially curved surfaces in the second cross-sectional profile.
In some embodiments, the metal barrier layer is a first metal barrier layer. In such embodiments, the first via has a first portion including a first metal fill layer and a second portion disposed over the first portion. The second portion includes a fourth metallic fill layer disposed over the second metallic barrier layer, the second metallic barrier layer disposed between the fourth metallic fill layer and the dielectric layer such that a fourth sidewall of the fourth metallic fill layer does not physically contact the dielectric layer, and the second metallic barrier layer disposed between the first metallic fill layer and the fourth metallic fill layer. In some embodiments, the first via and the second via have a first thickness, the first metal fill layer has a second thickness that is less than the first thickness, and the second metal fill layer has a third thickness that is equal to the first thickness. In some embodiments, the second via has a third portion comprising a second metal fill layer and a fourth portion disposed over the third portion. The fourth portion includes a fifth metallic fill layer disposed over the third metallic barrier layer, the third metallic barrier layer disposed between the fifth metallic fill layer and the dielectric layer such that a fifth sidewall of the fifth metallic fill layer does not physically contact the dielectric layer, and the third metallic barrier layer disposed between the second metallic fill layer and the fifth metallic fill layer. In some embodiments, the first via and the second via have a first thickness, the first metal fill layer has a second thickness less than the first thickness, the second metal fill layer has a third thickness less than the first thickness, and the third thickness is different than the second thickness.
In some embodiments, the first source/drain contact includes a first contact body layer disposed over the first contact barrier layer, and the second source/drain contact includes a second contact body layer disposed over the second contact barrier layer. A first portion of the first sidewall of the first metallic filler layer physically contacts the dielectric layer and a second portion of the first sidewall of the first metallic filler layer physically contacts the first contact barrier layer such that the first contact barrier layer is disposed between the second portion of the first sidewall of the first metallic filler layer and the dielectric layer. The third portion of the second sidewall of the second metal fill layer physically contacts the dielectric layer and the fourth portion of the second sidewall of the second metal fill layer physically contacts the second contact barrier layer such that the second contact barrier layer is disposed between the fourth portion of the second sidewall of the second metal fill layer and the dielectric layer.
An example method includes forming a first source/drain contact and a second source/drain contact in a dielectric layer. The first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature. The method also includes forming a first via opening and a second via opening in the dielectric layer. The first via opening exposes the first source/drain contact and the second via opening exposes the second source/drain contact. The method also includes recessing the first source/drain contact to extend the first via opening and recessing the second source/drain contact to extend the second via opening, and performing a bottom-up deposition process to form a first via body layer in the first via opening and a second via body layer in the second via opening. The first thickness of the first via body layer is different from the second thickness of the second via body layer. The method further comprises the following steps: forming a first via blocking layer over the first via body layer and the second via body layer; forming a third via body layer over the first via blocking layer; and performing a planarization process to remove any third via body layer, first via blocking layer, second via body layer, and first via body layer disposed over the top surface of the dielectric layer, thereby forming a first via having a third thickness and a first via layer configuration and a second via having a third thickness and a second via layer configuration different from the first via layer configuration. The method further comprises the following steps: forming a third via opening in the dielectric layer exposing the gate structure; forming a second via blocking layer partially filling the third via opening; and forming a fourth via body layer over the second via blocking layer. The fourth via body layer fills the remaining portion of the third via opening. The method also includes performing a planarization process to remove any of the fourth via body layer and the second via blocking layer disposed over the top surface of the dielectric layer, thereby forming a third via having a third via layer configuration that is different from the first via layer configuration and the second via layer configuration. In some embodiments, forming the first and second via openings in the dielectric layer includes performing a dry etch process, and recessing the first and second source/drain contacts includes performing a wet etch process. In some embodiments, each of the first source/drain contact and the second source/drain contact includes a contact body layer disposed over the contact barrier layer, and recessing the first source/drain contact and the second source/drain contact includes etching the contact body layer without substantially etching the contact barrier layer. In some embodiments, forming the third via body layer and forming the fourth via body layer each comprise performing a blanket deposition process.
Another exemplary method includes forming source/drain contacts to the source/drain features, forming first vias to the source/drain contacts, and forming second vias to the gate structures in the first dielectric layer. Forming the first via includes forming a second dielectric layer over the first dielectric layer and forming a first via opening in the second dielectric layer. The first via opening exposes the source/drain contact. Forming the first via further includes recessing the source/drain contact to extend the first via opening, performing a bottom-up deposition process to fill the extended first via opening with a first metal layer, forming a second metal layer over the first metal layer and the second dielectric layer, forming a third metal layer over the second metal layer, and performing a planarization process to remove any of the first metal layer, the second metal layer, and the third metal layer disposed over a top surface of the second dielectric layer. Forming the second via includes forming a second via opening in the second dielectric layer and the first dielectric layer. The second via opening exposes the gate structure. Forming the second via further includes forming a fourth metal layer to partially fill the second via opening and forming a fifth metal layer over the fourth metal layer to fill a remaining portion of the second via opening. In some embodiments, forming the first metal layer comprises forming a first tungsten-containing layer, and forming the third metal layer comprises forming a second tungsten-containing layer. In some embodiments, forming the second metal layer comprises forming a titanium-containing layer.
In some embodiments, the extended first via opening has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction. The first direction is different from the second direction. In such embodiments, the bottom of the extended first via opening is defined by a substantially flat surface in the first cross-sectional profile and a substantially curved surface in the second cross-sectional profile. In some embodiments, forming the second metal layer includes depositing a first glue layer and depositing a second glue layer over the first glue layer. In such an embodiment, the first glue layer may comprise titanium and the second glue layer may comprise titanium and nitrogen. In some embodiments, the first metal layer completely fills the first via opening such that the first via includes the first metal layer. In some embodiments, forming the first metal layer includes filling a bottom of the first via opening with the first metal layer such that a top of the first via opening remains after forming the first metal layer. In such embodiments, forming the second metal layer includes partially filling a top portion of the first via opening with the second metal layer, and forming the third metal layer includes filling a remaining portion of the top portion of the first via opening with the third metal layer.
In some embodiments, forming the first via opening includes performing a dry etch process, and recessing the source/drain contact includes performing a wet etch process. In some embodiments, the source/drain contact includes a metal fill layer disposed over the metal glue layer, and recessing the source/drain contact includes etching the metal fill layer without substantially etching the metal glue layer. In some embodiments, the gate structure has a first dimension along a first direction and a second dimension along a second direction substantially perpendicular to the first direction. In such embodiments, recessing the source/drain contact to extend the first via opening extends the first via opening along the second direction to below the second dielectric layer without extending the first via opening along the first direction to below the second dielectric layer. In some embodiments, the first dimension is a gate length and the second dimension is a gate width.
In some embodiments, the source/drain contact is a first source/drain contact and the source/drain feature is a first source/drain feature. In such embodiments, the method may further include forming a second source/drain contact in the first dielectric layer to the second source/drain feature. The gate structure is disposed between the first source/drain feature and the second source/drain feature. In such embodiments, the method may further include forming a third via in the second dielectric layer to the second source/drain contact while forming the first via to the first source/drain contact. Forming the third via includes forming a third via opening in the second dielectric layer. The third via opening exposes the second source/drain contact. Forming the third via further includes recessing the second source/drain contact to extend the third via opening, performing a bottom-up deposition process to fill the extended third via opening with a first metal layer, forming a second metal layer over the first metal layer and the second dielectric layer, forming a third metal layer over the second metal layer, and performing a planarization process to remove any of the first metal layer, the second metal layer, and the third metal layer disposed over a top surface of the second dielectric layer. In some embodiments, the first metal layer partially fills the first via opening and completely fills the third via opening and extends over the second dielectric layer, forming a first portion of the first metal layer disposed in the first via opening and a second portion of the first metal layer disposed in the third via opening. In some embodiments, the second metal layer partially fills the first via opening and is disposed over a first portion of the first metal layer disposed in the first via opening, and the second metal layer is disposed over a second portion of the first metal layer disposed in the third via opening. In some embodiments, a third metal layer partially fills the remaining portion of the first via opening and is disposed over the second metal layer.
Another exemplary device includes a gate structure disposed over a substrate. The gate structure is disposed between the first source/drain feature and the second source/drain feature. The device also includes a first source/drain contact and a second source/drain contact disposed in the dielectric layer. The first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature. The device also includes a first via, a second via, and a third via disposed in the dielectric layer. The first via physically contacts the first source/drain contact, the second via physically contacts the second source/drain contact, and the third via physically contacts the gate structure. Each of the first via and the second via includes a first metal fill layer in physical contact with the dielectric layer. The third through hole is provided with a second metal filling layer and a metal adhesive layer. The metal glue layer is arranged between the second metal filling layer and the dielectric layer. In some embodiments, the metal glue layer is a first metal glue layer, the first via has a first portion, wherein the first metal fill layer physically contacts the dielectric layer, and the first via has a second portion, wherein the second metal glue layer is disposed between the first metal fill layer and the dielectric layer. In some embodiments, each of the first source/drain contact and the second source/drain contact includes a third metal glue layer disposed between the third metal fill layer and the dielectric layer. In such embodiments, the first via further comprises a third portion, wherein the third metal glue layer is disposed between the first metal fill layer and the dielectric layer, and the second via comprises a portion, wherein the third metal glue layer is disposed between the first metal fill layer and the dielectric layer. In some embodiments, the first and second vias have a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction. The first direction is different from the second direction. In such embodiments, the bottom of the first via and the bottom of the second via are defined by a substantially flat surface in the first cross-sectional profile and a substantially curved surface in the second cross-sectional profile.
The present disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:
a first source/drain contact disposed in the dielectric layer, wherein the first source/drain contact physically contacts the first source/drain feature;
a second source/drain contact disposed in the dielectric layer, wherein the second source/drain contact physically contacts a second source/drain feature;
a first via having a first via layer configuration and disposed in the dielectric layer, wherein the first via extends into and physically contacts the first source/drain contact;
a second via having a second via layer configuration and disposed in the dielectric layer, wherein the second via extends into and physically contacts the second source/drain contact, the second via layer configuration is different from the first via layer configuration, and a first thickness of the first via is the same as a second thickness of the second via.
2. The semiconductor device of claim 1, wherein:
the first via includes a first upper portion disposed over a first lower portion, wherein the dielectric layer physically contacts a sidewall of the first upper portion and the first source/drain contact physically contacts a sidewall of the first lower portion; and is
The second via includes a second upper portion disposed above a second lower portion, wherein the dielectric layer physically contacts sidewalls of the second upper portion and the second source/drain contact physically contacts sidewalls of the second lower portion.
3. The semiconductor device of claim 1, wherein each of the first and second vias has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction, wherein the first direction is different from the second direction and the first cross-sectional profile is different from the second cross-sectional profile.
4. The semiconductor device of claim 1, wherein:
each of the first and second vias has a first bottom interface profile along a first direction with the first and second source/drain contacts, respectively, and a second bottom interface profile along a second direction with the first and second source/drain contacts, respectively; and is
The first direction is different from the second direction, the first bottom interface profile is defined by a flat surface, and the second bottom interface profile is defined by a curved surface.
5. The semiconductor device of claim 1, wherein:
the dielectric layers include a first interlayer dielectric layer, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a contact etch stop layer disposed between the first interlayer dielectric layer and the second interlayer dielectric layer;
the first and second source/drain contacts disposed in and extending through the first interlayer dielectric layer; and is
The first and second vias are disposed in and extend through the second interlayer dielectric layer and the contact etch stop layer, wherein a first portion of the first via that extends into the first source/drain contact physically contacts a bottom surface of the contact etch stop layer and a second portion of the second via that extends into the second source/drain contact physically contacts a bottom surface of the contact etch stop layer.
6. The semiconductor device of claim 1, wherein:
the first via having the first via layer configuration comprises:
a first through-hole body layer formed on the substrate,
a second via body layer disposed over the first via body layer, and
a via barrier layer disposed between the first via body layer and the second via body layer, wherein the first via body layer is in physical contact with the dielectric layer and the via barrier layer is further disposed between the second via body layer and the dielectric layer; and is
The second via having the second via layer configuration comprises:
a third via body layer in physical contact with the dielectric layer, wherein the first and third via body layers comprise the same material, the third via body layer has the second thickness, and the first via body layer has a third thickness that is less than the first thickness.
7. The semiconductor device of claim 6, wherein:
the first source/drain contact comprises a first contact barrier layer and a first contact bulk layer, wherein a first portion of the first contact barrier layer is disposed between the first contact bulk layer and the dielectric layer and a second portion of the first contact barrier layer is disposed between the first via bulk layer and the dielectric layer; and is
The second source/drain contact includes a second contact barrier layer and a second contact bulk layer, wherein a first portion of the second contact barrier layer is disposed between the second contact bulk layer and a dielectric layer and a second portion of the second contact barrier layer is disposed between the third via bulk layer and the dielectric layer.
8. The semiconductor device of claim 1, wherein:
the first via having the first via layer configuration comprises:
a first through-hole body layer formed on the substrate,
a second via body layer disposed over the first via body layer, and
a first via blocking layer disposed between the first via body layer and the second via body layer, wherein the first via body layer is in physical contact with the dielectric layer and the first via blocking layer is further disposed between the second via body layer and the dielectric layer;
the second via having the second via layer configuration comprises:
a third through-hole body layer formed on the substrate,
a fourth via body layer disposed above the third via body layer, an
A second via blocking layer disposed between the third via body layer and the fourth via body layer, wherein the third via body layer physically contacts the dielectric layer and the second via blocking layer is further disposed between the fourth via body layer and the dielectric layer;
wherein the first and third via body layers comprise a first material, the second and fourth via body layers comprise a second material, and the first and second via blocking layers comprise a third material; and is
A first distance between the first via blocking layer and a substrate is different from a second distance between the second via blocking layer and the substrate.
9. A semiconductor device, comprising:
a gate structure disposed over a substrate, wherein the gate structure is disposed between a first source/drain feature and a second source/drain feature;
a first source/drain contact and a second source/drain contact disposed in a dielectric layer, wherein the first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature; and
a first via, a second via, and a third via disposed in the dielectric layer, wherein:
the first via physically contacts the first source/drain contact, the second via physically contacts the second source/drain contact, and the third via physically contacts the gate structure,
the first via includes a first metal fill layer having a first sidewall in physical contact with the dielectric layer,
the second via includes a second metal fill layer having a second sidewall in physical contact with the dielectric layer, and
the third via includes a third metallic fill layer disposed over a metallic barrier layer, wherein the metallic barrier layer is disposed between the third metallic fill layer and the dielectric layer such that a third sidewall of the third metallic fill layer does not physically contact the dielectric layer.
10. A method of forming a semiconductor device, comprising:
forming a first source/drain contact and a second source/drain contact in the dielectric layer, wherein the first source/drain contact physically contacts the first source/drain feature and the second source/drain contact physically contacts the second source/drain feature;
forming a first via opening and a second via opening in the dielectric layer, wherein the first via opening exposes the first source/drain contact and the second via opening exposes the second source/drain contact;
recessing the first source/drain contact to extend the first via opening and recessing the second source/drain contact to extend the second via opening;
performing a bottom-up deposition process to form a first via body layer in the first via opening and a second via body layer in the second via opening, wherein a first thickness of the first via body layer is different than a second thickness of the second via body layer;
forming a first via blocking layer over the first via body layer and the second via body layer;
forming a third via body layer over the first via blocking layer;
performing a planarization process to remove any of the third via body layer, the first via blocking layer, the second via body layer, and the first via body layer disposed over the top surface of the dielectric layer, thereby forming a first via having a third thickness and a first via layer configuration and a second via having the third thickness and a second via layer configuration different from the first via layer configuration;
forming a third via opening in the dielectric layer exposing the gate structure;
forming a second via blocking layer partially filling the third via opening;
forming a fourth via body layer over the second via blocking layer, wherein the fourth via body layer fills a remaining portion of the third via opening; and
performing a planarization process to remove any of the fourth via body layer and the second via blocking layer disposed over the top surface of the dielectric layer to form a third via having a third via layer configuration that is different from the first via layer configuration and the second via layer configuration.
CN202011052596.1A 2019-09-30 2020-09-29 Semiconductor device and method of forming the same Pending CN112582405A (en)

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