CN112582340B - Method for forming metal cobalt interconnection layer and contact hole layer - Google Patents

Method for forming metal cobalt interconnection layer and contact hole layer Download PDF

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CN112582340B
CN112582340B CN202011479297.6A CN202011479297A CN112582340B CN 112582340 B CN112582340 B CN 112582340B CN 202011479297 A CN202011479297 A CN 202011479297A CN 112582340 B CN112582340 B CN 112582340B
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layer
hole
tungsten
contact hole
forming
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CN112582340A (en
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张文广
朱建军
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Shanghai IC R&D Center Co Ltd
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Shanghai IC R&D Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Abstract

The method for forming metal cobalt interconnection layer and contact hole layer comprises providing a substrate with interconnection layer structure, and forming dielectric layer on the substrate; carrying out photoetching technology on the dielectric layer to form a through hole layer; performing tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to fill the through holes in the through hole layer with metal tungsten to form first parts of the through holes; depositing a TIN bonding layer by ALD or CVD process, and filling the through holes in the through hole layer with metal tungsten by CVD tungsten process to form second parts of the through holes; depositing a TIN bonding layer by ALD or CVD process, filling the through holes in the through hole layer with metal tungsten by CVD tungsten process to form second parts of the through holes, and removing the TIN bonding layer by dry etching or wet etching process. According to the invention, through holes in the through hole layer are partially filled by a selective tungsten deposition process, and the penetration of CMP grinding fluid is blocked by using a TIN bonding layer deposited subsequently, so that the problem of cobalt deficiency of nodes of 7nm and below is solved.

Description

Method for forming metal cobalt interconnection layer and contact hole layer
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a method for forming a metal cobalt interconnection layer and a contact hole layer, which is used for solving the cobalt deficiency of an interconnection line layer in a node manufacturing process of 7nm and below.
Background
As the size of semiconductor devices is reduced, the contact hole or contact trench CD is reduced, and the RS (Sheet Resistance) is increased, so that the contribution of the adhesion layer (Ti/TiN) to the RS is more and more obvious. At present, several international research institutions have conducted research on a selective tungsten deposition process (selective W deposition) technology without a bonding layer, and particularly, the research is applied to filling of a Via layer Via 0 (V0) of a technology node of 10nm and below, and certain achievements have been achieved, because 7nm starts to have higher requirements on RS of contact grooves in an interconnection line layer (M0), and cobalt metal with lower RS is generally required to replace the conventional tungsten metal.
In the prior art, the formation method of the metal cobalt interconnection layer and the contact hole layer adopts a selective metal tungsten deposition process without a bonding layer.
However, it is clear to those skilled in the art that if the via layer is formed by a selective metal tungsten deposition process without an adhesive layer, then the adhesion of the via layer to the silicon oxide/silicon nitride dielectric layer of the sidewall is not good, which can result in subsequent tungsten in the via layer to attack the active cobalt in the underlying layer (interconnect layer) by the CMP slurry through this interface during the chemical mechanical polishing (tungsten polishing W CMP) fabrication process, creating a cobalt deficiency problem.
Disclosure of Invention
The invention aims to provide a method for forming a metal cobalt interconnection layer and a contact hole layer, which is used for solving the defect of 7nm and below node cobalt, and is used for blocking the permeation of CMP grinding fluid by using a TiN bonding layer deposited subsequently by partially filling a through hole in a through hole layer through a selective tungsten deposition process.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a method for forming a metallic cobalt interconnection layer and a contact hole layer comprises the following steps:
step S1: providing a substrate with an interconnection line layer structure, and forming a dielectric layer on the substrate, wherein the interconnection line material in the interconnection line layer structure comprises metallic cobalt;
step S2: performing standard photoetching technology on the dielectric layer to form a patterned through hole layer; wherein, the through holes in the through hole layer penetrate through the dielectric layer;
step S3: performing tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to fill the through holes in the through hole layer with metal tungsten to form first parts of the through holes; wherein the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer;
step S4: depositing a TIN bonding layer by ALD or CVD process, and filling the through holes in the through hole layer with metal tungsten by CVD tungsten process to form second parts of the through holes; wherein the bottom of the second part of the through hole is higher than the upper surface of the TIN bonding layer;
step S5: performing a tungsten chemical mechanical planarization process on the through hole layer, and removing a second part of the through hole to stop on the TIN bonding layer positioned on the upper surface of the first part of the through hole;
step S6: and removing the TIN bonding layer by adopting a dry etching or wet etching process.
Further, the dielectric layer sequentially comprises a contact hole etching stop layer and a silicon oxide layer from bottom to top.
Further, the material of the contact hole etching stop layer is silicon nitride or nitrogen-doped silicon carbide.
Further, the wet etching process is an SPM process.
Further, the step S4 further includes performing a compressive stress process on the surface of the via layer to increase the compressive stress between the dielectric in the dielectric layer and the metal tungsten and the sidewall in the via.
Further, the compressive stress process is a plasma bias bombardment process.
Further, the plasma bias bombardment process is a heavy ion plasma bias bombardment process.
Further, the heavy ions are Ar ions.
Further, the dielectric layer sequentially comprises a contact hole etching stop layer and a flowing chemical vapor deposition silicon oxide layer from bottom to top, and the step S4 further comprises a vapor annealing process for the flowing chemical vapor deposition silicon oxide layer so as to further increase the compressive stress between the dielectric in the dielectric layer and the side wall of the through hole tungsten plug.
Further, the interconnection line layer structure is an interconnection line layer structure M0; the through hole layer is a through hole layer V0.
According to the technical scheme, after forming the through holes by etching the through hole layer, the tungsten is partially filled in the through holes of the through hole layer by using a selective tungsten deposition process, then a TIN bonding layer and tungsten are deposited to fill the through holes of the through hole layer, and then the TIN material on the selectively deposited tungsten metal in the through holes of the through hole layer is ground again by using a CMP process; the polishing solution is blocked by the TIN in the CMP process, so that the lower layer M0 cobalt cannot be corroded, and finally the TIN is removed by a dry etching or wet etching process, so that the problem of cobalt deficiency is solved, and the process is not complicated from the aspect of process integration.
Drawings
FIG. 1 is a flow chart showing a method for forming a metal cobalt interconnect layer and a contact hole layer in an embodiment of the invention
FIGS. 2-7 are schematic diagrams illustrating the formation of a cobalt interconnect layer and a contact hole layer in accordance with a preferred embodiment of the present invention
Detailed Description
The following describes embodiments of the present invention in further detail with reference to FIGS. 1-7.
The method for forming the metal cobalt interconnection layer and the contact hole layer is a method for blocking the penetration of CMP grinding fluid by using a TIN bonding layer deposited later by partially filling the through holes of the through hole layer through a selective tungsten deposition process. Specifically, the invention is characterized in that tungsten is partially filled in the through hole of the through hole layer by using a selective tungsten deposition process after the through hole is formed by etching the through hole layer, and then a TIN bonding layer and tungsten are deposited to fill the through hole of the through hole layer, and then a subsequent CMP is performed to grind TIN materials on tungsten metal selectively deposited in the through hole of the through hole layer. The polishing liquid is blocked by the TIN bonding layer in the CMP process, so that M0 cobalt metal on the lower layer cannot be corroded, and finally, the TIN layer is removed by a dry etching or wet etching process, so that the problem of cobalt deficiency caused by corrosion of cobalt in the lower layer (interconnection line layer) by the polishing liquid of the CMP in the chemical mechanical polishing (tungsten polishing W CMP) manufacturing process of tungsten in the subsequent through hole layer is avoided.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for forming a cobalt interconnect layer and a contact hole layer according to an embodiment of the invention. In the embodiment of the invention, the method for forming the metal cobalt interconnection layer and the contact hole layer specifically comprises the following steps:
step S1: providing a substrate with an interconnection line layer structure, and forming a dielectric layer on the substrate, wherein the interconnection line material in the interconnection line layer structure comprises metallic cobalt;
step S2: performing standard photoetching technology on the dielectric layer to form a patterned through hole layer; wherein, the through holes in the through hole layer penetrate through the dielectric layer;
step S3: performing tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to fill the through holes in the through hole layer with metal tungsten to form first parts of the through holes; wherein the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer;
step S4: depositing a TIN bonding layer by ALD or CVD process, and filling the through holes in the through hole layer with metal tungsten by CVD tungsten process to form second parts of the through holes; wherein the bottom of the second part of the through hole is higher than the upper surface of the TIN bonding layer;
step S5: performing a tungsten chemical mechanical planarization process on the through hole layer, and removing a second part of the through hole to stop on the TIN bonding layer positioned on the upper surface of the first part of the through hole;
step S6: and removing the TIN bonding layer by adopting a dry etching or wet etching process.
Further, the interconnection line layer structure is an interconnection line layer structure M0; the through hole layer is a through hole layer V0.
The technical scheme of the invention is exemplified by a specific embodiment.
In the embodiment of the invention, the dielectric layer sequentially comprises a contact hole etching stop layer (Contact Etch Stop Layer, CESL for short) and a silicon oxide layer from bottom to top. Preferably, the material of the contact hole etching stop layer is silicon nitride or nitrogen-doped silicon carbide.
Referring to fig. 2-7, fig. 2-7 are schematic views illustrating a process of forming a cobalt interconnect layer and a contact hole layer according to a preferred embodiment of the invention. As shown in fig. 2, a substrate 1 including an interconnect layer structure 2 is provided, and a dielectric layer 3 (silicon nitride 31 and silicon oxide 32) is formed on the substrate 1, wherein the interconnect material in the interconnect layer structure 2 includes cobalt metal, and the silicon nitride 31 is a contact hole etch stop layer (CESL).
As shown in fig. 3, the result graph of the standard photoetching process is shown after the dielectric layer is subjected to the standard photoetching process, namely a patterned through hole layer is formed; wherein the via in the via layer penetrates the dielectric layer, that is, the via in the via layer has been etched through a Contact Etch Stop Layer (CESL), stopping on the surface of the interconnect line in the interconnect line layer structure.
As shown in fig. 4, the via layer is shown being tungsten deposited using a selective tungsten deposition process such that tungsten metal fills the vias in the via layer to form a first portion of the vias; wherein, the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer.
In one embodiment of the present invention, to further increase the compressive stress between the dielectric in the dielectric layer and the metal tungsten in the via and the sidewall, the step S4 further includes performing a compressive stress process on the surface of the via layer to increase the compressive stress between the dielectric in the dielectric layer and the metal tungsten in the via and the sidewall.
Further, the compressive stress process is a plasma bias bombardment process. Preferably, the plasma bias bombardment process is a heavy ion plasma bias bombardment process. For example, the heavy ions are Ar ions.
In another embodiment of the present invention, the dielectric layer includes a contact hole etching stop layer and a flow type chemical vapor deposition silicon oxide layer sequentially from bottom to top, and the step S4 further includes performing a vapor annealing process on the flow type chemical vapor deposition silicon oxide layer to further increase the compressive stress between the dielectric in the dielectric layer and the metal tungsten and the sidewall in the through hole.
As shown in fig. 5, an atomic layer deposition (Atomic layer deposition, ALD) or chemical vapor deposition (Chemical Vapor Deposition, CVD) process is used to deposit a TIN adhesion layer and a chemical vapor deposition tungsten process is used to fill the via in the via layer with metallic tungsten to form a second portion of the via.
As shown in fig. 6, a tungsten chemical mechanical planarization process is performed on the via layer to remove the second portion of the via to stop on the TIN adhesive layer located on the upper surface of the first portion of the via. That is, the tungsten chemical mechanical planarization process is performed through the via layer, not only removing the second portion of the via, but also removing the TIN adhesion layer on the upper surface and part of the sidewall of the silicon oxide 32, and removing the silicon oxide 32 material higher than the bottom of the second portion of the via.
As shown in fig. 7, the TIN bonding layer on the upper surface of the first portion of the through hole is removed by adopting a dry etching or wet etching process, so that the upper surface of the first portion of the through hole is exposed, and the manufacture of the metal cobalt interconnection layer and the contact hole layer is completed. Preferably, the wet etching process is an SPM process, wherein H is generally used in the SPM process 2 SO 4 、H 2 O 2 、H 2 And (3) mixing liquid of O.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.

Claims (10)

1. The method for forming the metal cobalt interconnection layer and the contact hole layer is characterized by comprising the following steps of:
step S1: providing a substrate with an interconnection line layer structure, and forming a dielectric layer on the substrate, wherein the interconnection line material in the interconnection line layer structure comprises metallic cobalt;
step S2: performing standard photoetching technology on the dielectric layer to form a patterned through hole layer; wherein, the through holes in the through hole layer penetrate through the dielectric layer;
step S3: performing tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to fill the through holes in the through hole layer with metal tungsten to form first parts of the through holes; wherein the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer;
step S4: depositing a TIN bonding layer by ALD or CVD process, and filling the through holes in the through hole layer with metal tungsten by CVD tungsten process to form second parts of the through holes;
step S5: performing a tungsten chemical mechanical planarization process on the through hole layer, and removing a second part of the through hole to stop on the TIN bonding layer positioned on the upper surface of the first part of the through hole;
step S6: and removing the TIN bonding layer by using a dry etching or wet etching process.
2. The method for forming a metal cobalt interconnect layer and a contact hole layer according to claim 1, wherein the dielectric layer comprises a contact hole etch stop layer and a silicon oxide layer in sequence from bottom to top.
3. The method of forming a metal cobalt interconnect layer and a contact hole layer of claim 2, wherein the contact hole etch stop layer is of a material of silicon nitride or nitrogen doped silicon carbide.
4. The method of forming a metal cobalt interconnect layer and a contact hole layer according to claim 3, wherein the wet etching process is an SPM process.
5. The method of forming a metal cobalt interconnect layer and a contact hole layer of claim 2, wherein step S4 further comprises performing a compressive stress process on the via layer surface to increase the compressive stress between the dielectric in the dielectric layer and the metal tungsten and sidewalls in the via.
6. The method of forming a metal cobalt interconnect layer and a contact hole layer according to claim 5, wherein the compressive stress process is a plasma bias bombardment process.
7. The method of forming a metal cobalt interconnect layer and a contact hole layer of claim 6, wherein the plasma bias bombardment process is a heavy ion plasma bias bombardment process.
8. The method of forming a metal cobalt interconnect layer and a contact hole layer according to claim 7, wherein the heavy ion plasma bias bombardment process employs heavy ions of Ar ions.
9. The method of forming a metal cobalt interconnect layer and a contact hole layer according to claim 1, wherein the dielectric layer comprises a contact hole etch stop layer and a flowable chemical vapor deposited silicon oxide layer in sequence from bottom to top, and step S4 further comprises performing a vapor annealing process on the flowable chemical vapor deposited silicon oxide layer to further increase a compressive stress between the dielectric in the dielectric layer and the sidewall of the via tungsten plug.
10. The method of forming a metal cobalt interconnect layer and a contact hole layer according to claim 1, wherein the interconnect line layer structure is an interconnect line layer structure M0; the through hole layer is a through hole layer V0.
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